Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 2 | /* |
chenhui zhao | 568336e | 2011-09-15 14:52:34 +0800 | [diff] [blame] | 3 | * Copyright 2004, 2011 Freescale Semiconductor. |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 4 | * |
| 5 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 8 | #include <common.h> |
Simon Glass | 2cf431c | 2019-11-14 12:57:47 -0700 | [diff] [blame^] | 9 | #include <init.h> |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 10 | #include <pci.h> |
Simon Glass | 2189d5f | 2019-11-14 12:57:20 -0700 | [diff] [blame] | 11 | #include <vsprintf.h> |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 12 | #include <asm/processor.h> |
Jon Loeliger | aa11d85 | 2008-03-17 15:48:18 -0500 | [diff] [blame] | 13 | #include <asm/mmu.h> |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 14 | #include <asm/immap_85xx.h> |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 15 | #include <fsl_ddr_sdram.h> |
Wolfgang Denk | 2d5df63 | 2005-07-21 16:14:36 +0200 | [diff] [blame] | 16 | #include <ioports.h> |
Jon Loeliger | a30a549 | 2008-03-04 10:03:03 -0600 | [diff] [blame] | 17 | #include <spd_sdram.h> |
Masahiro Yamada | b08c8c4 | 2018-03-05 01:20:11 +0900 | [diff] [blame] | 18 | #include <linux/libfdt.h> |
Kumar Gala | b90d254 | 2007-11-29 00:11:44 -0600 | [diff] [blame] | 19 | #include <fdt_support.h> |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 20 | |
| 21 | #include "../common/cadmus.h" |
| 22 | #include "../common/eeprom.h" |
Matthew McClintock | cbfc7ce | 2006-06-28 10:46:13 -0500 | [diff] [blame] | 23 | #include "../common/via.h" |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 24 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 25 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 26 | extern void ddr_enable_ecc(unsigned int dram_size); |
| 27 | #endif |
| 28 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 29 | void local_bus_init(void); |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 30 | |
Wolfgang Denk | 2d5df63 | 2005-07-21 16:14:36 +0200 | [diff] [blame] | 31 | /* |
| 32 | * I/O Port configuration table |
| 33 | * |
| 34 | * if conf is 1, then that port pin will be configured at boot time |
| 35 | * according to the five values podr/pdir/ppar/psor/pdat for that entry |
| 36 | */ |
| 37 | |
| 38 | const iop_conf_t iop_conf_tab[4][32] = { |
| 39 | |
| 40 | /* Port A configuration */ |
| 41 | { /* conf ppar psor pdir podr pdat */ |
| 42 | /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ |
| 43 | /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ |
| 44 | /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ |
| 45 | /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ |
| 46 | /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ |
| 47 | /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ |
| 48 | /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ |
| 49 | /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ |
| 50 | /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ |
| 51 | /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ |
| 52 | /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ |
| 53 | /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ |
| 54 | /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ |
| 55 | /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ |
| 56 | /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ |
| 57 | /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ |
| 58 | /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ |
| 59 | /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ |
| 60 | /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ |
| 61 | /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ |
| 62 | /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ |
| 63 | /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ |
| 64 | /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ |
| 65 | /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ |
| 66 | /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ |
| 67 | /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ |
| 68 | /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ |
| 69 | /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ |
| 70 | /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ |
| 71 | /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ |
| 72 | /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ |
| 73 | /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ |
| 74 | }, |
| 75 | |
| 76 | /* Port B configuration */ |
| 77 | { /* conf ppar psor pdir podr pdat */ |
| 78 | /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ |
| 79 | /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ |
| 80 | /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ |
| 81 | /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ |
| 82 | /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ |
| 83 | /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ |
| 84 | /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ |
| 85 | /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ |
| 86 | /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ |
| 87 | /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ |
| 88 | /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ |
| 89 | /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ |
| 90 | /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ |
| 91 | /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ |
| 92 | /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ |
| 93 | /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ |
| 94 | /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ |
| 95 | /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ |
| 96 | /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ |
| 97 | /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ |
| 98 | /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
| 99 | /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
| 100 | /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
| 101 | /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
| 102 | /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
| 103 | /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
| 104 | /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
| 105 | /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
| 106 | /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| 107 | /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| 108 | /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| 109 | /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
| 110 | }, |
| 111 | |
| 112 | /* Port C */ |
| 113 | { /* conf ppar psor pdir podr pdat */ |
| 114 | /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ |
| 115 | /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ |
| 116 | /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ |
| 117 | /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ |
| 118 | /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ |
| 119 | /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ |
| 120 | /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ |
| 121 | /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ |
| 122 | /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ |
| 123 | /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ |
| 124 | /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ |
| 125 | /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ |
| 126 | /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ |
| 127 | /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ |
| 128 | /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ |
| 129 | /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ |
| 130 | /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ |
| 131 | /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ |
| 132 | /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ |
| 133 | /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ |
| 134 | /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ |
| 135 | /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ |
| 136 | /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ |
| 137 | /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ |
| 138 | /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ |
| 139 | /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ |
| 140 | /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ |
| 141 | /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ |
| 142 | /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ |
| 143 | /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ |
| 144 | /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ |
| 145 | /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ |
| 146 | }, |
| 147 | |
| 148 | /* Port D */ |
| 149 | { /* conf ppar psor pdir podr pdat */ |
| 150 | /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ |
| 151 | /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ |
| 152 | /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ |
| 153 | /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ |
| 154 | /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ |
| 155 | /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ |
| 156 | /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ |
| 157 | /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ |
| 158 | /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ |
| 159 | /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ |
| 160 | /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ |
| 161 | /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ |
| 162 | /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ |
| 163 | /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ |
| 164 | /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ |
| 165 | /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ |
| 166 | /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
| 167 | /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ |
| 168 | /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
| 169 | /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ |
| 170 | /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ |
| 171 | /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ |
| 172 | /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ |
| 173 | /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ |
| 174 | /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ |
| 175 | /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ |
| 176 | /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ |
| 177 | /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ |
| 178 | /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| 179 | /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| 180 | /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
| 181 | /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
| 182 | } |
| 183 | }; |
| 184 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 185 | int checkboard (void) |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 186 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 187 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
chenhui zhao | 568336e | 2011-09-15 14:52:34 +0800 | [diff] [blame] | 188 | char buf[32]; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 189 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 190 | /* PCI slot in USER bits CSR[6:7] by convention. */ |
| 191 | uint pci_slot = get_pci_slot (); |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 192 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 193 | uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ |
| 194 | uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ |
| 195 | uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ |
| 196 | uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 197 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 198 | uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 199 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 200 | uint cpu_board_rev = get_cpu_board_revision (); |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 201 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 202 | printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", |
| 203 | get_board_version (), pci_slot); |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 204 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 205 | printf ("CPU Board Revision %d.%d (0x%04x)\n", |
| 206 | MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), |
| 207 | MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 208 | |
Peter Tyser | 8ca78f2 | 2010-10-29 17:59:24 -0500 | [diff] [blame] | 209 | printf("PCI1: %d bit, %s MHz, %s\n", |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 210 | (pci1_32) ? 32 : 64, |
chenhui zhao | 568336e | 2011-09-15 14:52:34 +0800 | [diff] [blame] | 211 | strmhz(buf, pci1_speed), |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 212 | pci1_clk_sel ? "sync" : "async"); |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 213 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 214 | if (pci_dual) { |
Peter Tyser | 8ca78f2 | 2010-10-29 17:59:24 -0500 | [diff] [blame] | 215 | printf("PCI2: 32 bit, 66 MHz, %s\n", |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 216 | pci2_clk_sel ? "sync" : "async"); |
| 217 | } else { |
Peter Tyser | 8ca78f2 | 2010-10-29 17:59:24 -0500 | [diff] [blame] | 218 | printf("PCI2: disabled\n"); |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 219 | } |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 220 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 221 | /* |
| 222 | * Initialize local bus. |
| 223 | */ |
| 224 | local_bus_init (); |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 225 | |
wdenk | 5c952cf | 2004-10-10 21:27:30 +0000 | [diff] [blame] | 226 | return 0; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 227 | } |
| 228 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 229 | /* |
| 230 | * Initialize Local Bus |
| 231 | */ |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 232 | void |
| 233 | local_bus_init(void) |
| 234 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 235 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
Becky Bruce | f51cdaf | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 236 | volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 237 | |
| 238 | uint clkdiv; |
| 239 | uint lbc_hz; |
| 240 | sys_info_t sysinfo; |
| 241 | uint temp_lbcdll; |
| 242 | |
| 243 | /* |
| 244 | * Errata LBC11. |
| 245 | * Fix Local Bus clock glitch when DLL is enabled. |
| 246 | * |
Wolfgang Denk | 8ed44d9 | 2008-10-19 02:35:50 +0200 | [diff] [blame] | 247 | * If localbus freq is < 66MHz, DLL bypass mode must be used. |
| 248 | * If localbus freq is > 133MHz, DLL can be safely enabled. |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 249 | * Between 66 and 133, the DLL is enabled with an override workaround. |
| 250 | */ |
| 251 | |
| 252 | get_sys_info(&sysinfo); |
Trent Piepho | a5d212a | 2008-12-03 15:16:34 -0800 | [diff] [blame] | 253 | clkdiv = lbc->lcrr & LCRR_CLKDIV; |
Prabhakar Kushwaha | 997399f | 2013-08-16 14:52:26 +0530 | [diff] [blame] | 254 | lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 255 | |
| 256 | if (lbc_hz < 66) { |
Paul Gortmaker | a2af6a7 | 2012-08-13 13:48:57 +0000 | [diff] [blame] | 257 | lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */ |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 258 | |
| 259 | } else if (lbc_hz >= 133) { |
Paul Gortmaker | a2af6a7 | 2012-08-13 13:48:57 +0000 | [diff] [blame] | 260 | lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 261 | |
| 262 | } else { |
Paul Gortmaker | a2af6a7 | 2012-08-13 13:48:57 +0000 | [diff] [blame] | 263 | lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */ |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 264 | udelay(200); |
| 265 | |
| 266 | /* |
| 267 | * Sample LBC DLL ctrl reg, upshift it to set the |
| 268 | * override bits. |
| 269 | */ |
| 270 | temp_lbcdll = gur->lbcdllcr; |
| 271 | gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); |
| 272 | asm("sync;isync;msync"); |
| 273 | } |
| 274 | } |
| 275 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 276 | /* |
| 277 | * Initialize SDRAM memory on the Local Bus. |
| 278 | */ |
Becky Bruce | 70961ba | 2010-12-17 17:17:57 -0600 | [diff] [blame] | 279 | void lbc_sdram_init(void) |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 280 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 281 | #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 282 | |
| 283 | uint idx; |
Becky Bruce | f51cdaf | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 284 | volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 285 | uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 286 | uint cpu_board_rev; |
| 287 | uint lsdmr_common; |
| 288 | |
Becky Bruce | 7ea3871 | 2010-12-17 17:17:59 -0600 | [diff] [blame] | 289 | puts("LBC SDRAM: "); |
| 290 | print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, |
| 291 | "\n "); |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 292 | |
| 293 | /* |
| 294 | * Setup SDRAM Base and Option Registers |
| 295 | */ |
Becky Bruce | f51cdaf | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 296 | set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); |
| 297 | set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 298 | lbc->lbcr = CONFIG_SYS_LBC_LBCR; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 299 | asm("msync"); |
| 300 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 301 | lbc->lsrt = CONFIG_SYS_LBC_LSRT; |
| 302 | lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 303 | asm("msync"); |
| 304 | |
| 305 | /* |
| 306 | * Determine which address lines to use baed on CPU board rev. |
| 307 | */ |
| 308 | cpu_board_rev = get_cpu_board_revision(); |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 309 | lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 310 | if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { |
Kumar Gala | b0fe93ed | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 311 | lsdmr_common |= LSDMR_BSMA1617; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 312 | } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { |
Kumar Gala | b0fe93ed | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 313 | lsdmr_common |= LSDMR_BSMA1516; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 314 | } else { |
| 315 | /* |
| 316 | * Assume something unable to identify itself is |
| 317 | * really old, and likely has lines 16/17 mapped. |
| 318 | */ |
Kumar Gala | b0fe93ed | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 319 | lsdmr_common |= LSDMR_BSMA1617; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 320 | } |
| 321 | |
| 322 | /* |
| 323 | * Issue PRECHARGE ALL command. |
| 324 | */ |
Kumar Gala | b0fe93ed | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 325 | lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 326 | asm("sync;msync"); |
| 327 | *sdram_addr = 0xff; |
| 328 | ppcDcbf((unsigned long) sdram_addr); |
| 329 | udelay(100); |
| 330 | |
| 331 | /* |
| 332 | * Issue 8 AUTO REFRESH commands. |
| 333 | */ |
| 334 | for (idx = 0; idx < 8; idx++) { |
Kumar Gala | b0fe93ed | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 335 | lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 336 | asm("sync;msync"); |
| 337 | *sdram_addr = 0xff; |
| 338 | ppcDcbf((unsigned long) sdram_addr); |
| 339 | udelay(100); |
| 340 | } |
| 341 | |
| 342 | /* |
| 343 | * Issue 8 MODE-set command. |
| 344 | */ |
Kumar Gala | b0fe93ed | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 345 | lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 346 | asm("sync;msync"); |
| 347 | *sdram_addr = 0xff; |
| 348 | ppcDcbf((unsigned long) sdram_addr); |
| 349 | udelay(100); |
| 350 | |
| 351 | /* |
| 352 | * Issue NORMAL OP command. |
| 353 | */ |
Kumar Gala | b0fe93ed | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 354 | lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 355 | asm("sync;msync"); |
| 356 | *sdram_addr = 0xff; |
| 357 | ppcDcbf((unsigned long) sdram_addr); |
| 358 | udelay(200); /* Overkill. Must wait > 200 bus cycles */ |
| 359 | |
| 360 | #endif /* enable SDRAM init */ |
| 361 | } |
| 362 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 363 | #if defined(CONFIG_PCI) |
Matthew McClintock | cbfc7ce | 2006-06-28 10:46:13 -0500 | [diff] [blame] | 364 | /* For some reason the Tundra PCI bridge shows up on itself as a |
| 365 | * different device. Work around that by refusing to configure it. |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 366 | */ |
Matthew McClintock | cbfc7ce | 2006-06-28 10:46:13 -0500 | [diff] [blame] | 367 | void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 368 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 369 | static struct pci_config_table pci_mpc85xxcds_config_table[] = { |
Matthew McClintock | cbfc7ce | 2006-06-28 10:46:13 -0500 | [diff] [blame] | 370 | {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, |
Randy Vinson | 7f3f2bd | 2007-02-27 19:42:22 -0700 | [diff] [blame] | 371 | {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, |
| 372 | {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, |
Andy Fleming | ffa621a | 2007-02-24 01:08:13 -0600 | [diff] [blame] | 373 | mpc85xx_config_via_usbide, {0,0,0}}, |
Randy Vinson | 7f3f2bd | 2007-02-27 19:42:22 -0700 | [diff] [blame] | 374 | {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, |
| 375 | mpc85xx_config_via_usb, {0,0,0}}, |
| 376 | {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, |
| 377 | mpc85xx_config_via_usb2, {0,0,0}}, |
| 378 | {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, |
Andy Fleming | ffa621a | 2007-02-24 01:08:13 -0600 | [diff] [blame] | 379 | mpc85xx_config_via_power, {0,0,0}}, |
Randy Vinson | 7f3f2bd | 2007-02-27 19:42:22 -0700 | [diff] [blame] | 380 | {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, |
| 381 | mpc85xx_config_via_ac97, {0,0,0}}, |
Andy Fleming | ffa621a | 2007-02-24 01:08:13 -0600 | [diff] [blame] | 382 | {}, |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 383 | }; |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 384 | |
Matthew McClintock | cbfc7ce | 2006-06-28 10:46:13 -0500 | [diff] [blame] | 385 | static struct pci_controller hose[] = { |
| 386 | { config_table: pci_mpc85xxcds_config_table,}, |
| 387 | #ifdef CONFIG_MPC85XX_PCI2 |
| 388 | {}, |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 389 | #endif |
| 390 | }; |
| 391 | |
| 392 | #endif /* CONFIG_PCI */ |
| 393 | |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 394 | void |
| 395 | pci_init_board(void) |
| 396 | { |
| 397 | #ifdef CONFIG_PCI |
Matthew McClintock | 7376eb8 | 2006-10-11 15:13:01 -0500 | [diff] [blame] | 398 | pci_mpc85xx_init(hose); |
wdenk | 03f5c55 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 399 | #endif |
| 400 | } |
Kumar Gala | b90d254 | 2007-11-29 00:11:44 -0600 | [diff] [blame] | 401 | |
| 402 | #if defined(CONFIG_OF_BOARD_SETUP) |
| 403 | void |
| 404 | ft_pci_setup(void *blob, bd_t *bd) |
| 405 | { |
| 406 | int node, tmp[2]; |
| 407 | const char *path; |
| 408 | |
| 409 | node = fdt_path_offset(blob, "/aliases"); |
| 410 | tmp[0] = 0; |
| 411 | if (node >= 0) { |
| 412 | #ifdef CONFIG_PCI1 |
| 413 | path = fdt_getprop(blob, node, "pci0", NULL); |
| 414 | if (path) { |
| 415 | tmp[1] = hose[0].last_busno - hose[0].first_busno; |
| 416 | do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); |
| 417 | } |
| 418 | #endif |
| 419 | #ifdef CONFIG_MPC85XX_PCI2 |
| 420 | path = fdt_getprop(blob, node, "pci1", NULL); |
| 421 | if (path) { |
| 422 | tmp[1] = hose[1].last_busno - hose[1].first_busno; |
| 423 | do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); |
| 424 | } |
| 425 | #endif |
| 426 | } |
| 427 | } |
| 428 | #endif |