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wdenk945af8d2003-07-16 21:53:01 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2003-2005
wdenk945af8d2003-07-16 21:53:01 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
wdenkcbd8a352004-02-24 02:00:03 +000032#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
Detlev Zundelfd428c02010-03-12 10:01:12 +010033#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
wdenk945af8d2003-07-16 21:53:01 +000034#define CONFIG_ICECUBE 1 /* ... on IceCube board */
35
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenk945af8d2003-07-16 21:53:01 +000037
38#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39#define BOOTFLAG_WARM 0x02 /* Software reboot */
40
Becky Bruce31d82672008-05-08 19:02:12 -050041#define CONFIG_HIGH_BATS 1 /* High BATs supported */
42
wdenk945af8d2003-07-16 21:53:01 +000043/*
44 * Serial console configuration
45 */
46#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
47#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk945af8d2003-07-16 21:53:01 +000049
wdenk96e48cf2003-08-05 18:22:44 +000050
wdenk96e48cf2003-08-05 18:22:44 +000051/*
52 * PCI Mapping:
53 * 0x40000000 - 0x4fffffff - PCI Memory
54 * 0x50000000 - 0x50ffffff - PCI IO Space
55 */
Rafal Jaworowskib66a9382006-03-29 13:17:09 +020056#define CONFIG_PCI
57
58#if defined(CONFIG_PCI)
wdenk96e48cf2003-08-05 18:22:44 +000059#define CONFIG_PCI_PNP 1
60#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -050061#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
wdenk96e48cf2003-08-05 18:22:44 +000062
63#define CONFIG_PCI_MEM_BUS 0x40000000
64#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
65#define CONFIG_PCI_MEM_SIZE 0x10000000
66
67#define CONFIG_PCI_IO_BUS 0x50000000
68#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
69#define CONFIG_PCI_IO_SIZE 0x01000000
Rafal Jaworowskib66a9382006-03-29 13:17:09 +020070#endif
wdenk96e48cf2003-08-05 18:22:44 +000071
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_XLB_PIPELINING 1
wdenke1599e82004-10-10 23:27:33 +000073
wdenk96e48cf2003-08-05 18:22:44 +000074#define CONFIG_NET_MULTI 1
Marian Balakowicz63ff0042005-10-28 22:30:33 +020075#define CONFIG_MII 1
wdenk96e48cf2003-08-05 18:22:44 +000076#define CONFIG_EEPRO100 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkf54ebdf2003-09-17 15:10:32 +000078#define CONFIG_NS8382X 1
wdenk96e48cf2003-08-05 18:22:44 +000079
wdenk132ba5f2004-02-27 08:20:54 +000080/* Partitions */
81#define CONFIG_MAC_PARTITION
82#define CONFIG_DOS_PARTITION
wdenk64f70be2004-09-28 20:34:50 +000083#define CONFIG_ISO_PARTITION
wdenk132ba5f2004-02-27 08:20:54 +000084
wdenk80885a92004-02-26 23:46:20 +000085/* USB */
Markus Klotzbuecherae3b7702006-11-27 11:46:46 +010086#define CONFIG_USB_OHCI_NEW
wdenk80885a92004-02-26 23:46:20 +000087#define CONFIG_USB_STORAGE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_OHCI_BE_CONTROLLER
89#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
90#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
91#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
92#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
93#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Markus Klotzbuecherae3b7702006-11-27 11:46:46 +010094
wdenk414eec32005-04-02 22:37:54 +000095#define CONFIG_TIMESTAMP /* Print image info with timestamp */
96
wdenk945af8d2003-07-16 21:53:01 +000097
Jon Loeliger348f2582007-07-08 13:46:18 -050098/*
Jon Loeliger11799432007-07-10 09:02:57 -050099 * BOOTP options
100 */
101#define CONFIG_BOOTP_BOOTFILESIZE
102#define CONFIG_BOOTP_BOOTPATH
103#define CONFIG_BOOTP_GATEWAY
104#define CONFIG_BOOTP_HOSTNAME
105
106
107/*
Jon Loeliger348f2582007-07-08 13:46:18 -0500108 * Command line configuration.
109 */
110#include <config_cmd_default.h>
111
112#define CONFIG_CMD_EEPROM
113#define CONFIG_CMD_FAT
114#define CONFIG_CMD_I2C
115#define CONFIG_CMD_IDE
116#define CONFIG_CMD_NFS
117#define CONFIG_CMD_SNTP
Jon Loeliger11799432007-07-10 09:02:57 -0500118#define CONFIG_CMD_USB
119
120#if defined(CONFIG_PCI)
121#define CONFIG_CMD_PCI
122#endif
Jon Loeliger348f2582007-07-08 13:46:18 -0500123
wdenk945af8d2003-07-16 21:53:01 +0000124
wdenk5cf9da42003-11-07 13:42:26 +0000125#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126# define CONFIG_SYS_LOWBOOT 1
127# define CONFIG_SYS_LOWBOOT16 1
wdenk5cf9da42003-11-07 13:42:26 +0000128#endif
129#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100130#if defined(CONFIG_LITE5200B)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100132#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133# define CONFIG_SYS_LOWBOOT 1
134# define CONFIG_SYS_LOWBOOT08 1
wdenk5cf9da42003-11-07 13:42:26 +0000135#endif
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100136#endif
wdenk5cf9da42003-11-07 13:42:26 +0000137
wdenk945af8d2003-07-16 21:53:01 +0000138/*
139 * Autobooting
140 */
141#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk5cf9da42003-11-07 13:42:26 +0000142
143#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100144 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk5cf9da42003-11-07 13:42:26 +0000145 "echo"
146
147#undef CONFIG_BOOTARGS
148
149#define CONFIG_EXTRA_ENV_SETTINGS \
150 "netdev=eth0\0" \
151 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100152 "nfsroot=${serverip}:${rootpath}\0" \
wdenk5cf9da42003-11-07 13:42:26 +0000153 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100154 "addip=setenv bootargs ${bootargs} " \
155 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
156 ":${hostname}:${netdev}:off panic=1\0" \
wdenk5cf9da42003-11-07 13:42:26 +0000157 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100158 "bootm ${kernel_addr}\0" \
wdenk5cf9da42003-11-07 13:42:26 +0000159 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100160 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
161 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk5cf9da42003-11-07 13:42:26 +0000162 "rootpath=/opt/eldk/ppc_82xx\0" \
163 "bootfile=/tftpboot/MPC5200/uImage\0" \
164 ""
165
166#define CONFIG_BOOTCOMMAND "run flash_self"
wdenk945af8d2003-07-16 21:53:01 +0000167
wdenkacf98e72003-09-16 11:39:10 +0000168/*
169 * IPB Bus clocking configuration.
170 */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100171#if defined(CONFIG_LITE5200B)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100173#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenkacf98e72003-09-16 11:39:10 +0000175#endif
Stefan Roesee59581c2006-11-28 17:55:49 +0100176
177/* pass open firmware flat tree */
Grant Likelycf2817a2007-09-06 09:46:23 -0600178#define CONFIG_OF_LIBFDT 1
Stefan Roesee59581c2006-11-28 17:55:49 +0100179#define CONFIG_OF_BOARD_SETUP 1
180
Stefan Roesee59581c2006-11-28 17:55:49 +0100181#define OF_CPU "PowerPC,5200@0"
182#define OF_SOC "soc5200@f0000000"
Domen Puncer39f23cd2007-04-20 11:13:16 +0200183#define OF_TBCLK (bd->bi_busfreq / 4)
Stefan Roesee59581c2006-11-28 17:55:49 +0100184#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
185
wdenk945af8d2003-07-16 21:53:01 +0000186/*
187 * I2C configuration
188 */
wdenk531716e2003-09-13 19:01:12 +0000189#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
dzuab209d52003-09-30 14:08:43 +0000191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
193#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk531716e2003-09-13 19:01:12 +0000194
195/*
196 * EEPROM configuration
197 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
199#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
200#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
201#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
wdenk945af8d2003-07-16 21:53:01 +0000202
203/*
204 * Flash configuration
205 */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100206#if defined(CONFIG_LITE5200B)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_FLASH_BASE 0xFE000000
208#define CONFIG_SYS_FLASH_SIZE 0x01000000
209#if !defined(CONFIG_SYS_LOWBOOT)
210#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
211#else /* CONFIG_SYS_LOWBOOT */
212#if defined(CONFIG_SYS_LOWBOOT08)
213# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100214#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#if defined(CONFIG_SYS_LOWBOOT16)
216#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000)
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100217#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#endif /* CONFIG_SYS_LOWBOOT */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100219#else /* !CONFIG_LITE5200B (IceCube)*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_FLASH_BASE 0xFF000000
221#define CONFIG_SYS_FLASH_SIZE 0x01000000
222#if !defined(CONFIG_SYS_LOWBOOT)
223#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
224#else /* CONFIG_SYS_LOWBOOT */
225#if defined(CONFIG_SYS_LOWBOOT08)
226#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
wdenk7152b1d2003-09-05 23:19:14 +0000227#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#if defined(CONFIG_SYS_LOWBOOT16)
229#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
wdenk5cf9da42003-11-07 13:42:26 +0000230#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#endif /* CONFIG_SYS_LOWBOOT */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100232#endif /* CONFIG_LITE5200B */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
wdenk7152b1d2003-09-05 23:19:14 +0000234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
wdenk945af8d2003-07-16 21:53:01 +0000236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
238#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenk945af8d2003-07-16 21:53:01 +0000239
wdenk96e48cf2003-08-05 18:22:44 +0000240#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
wdenk945af8d2003-07-16 21:53:01 +0000241
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100242#if defined(CONFIG_LITE5200B)
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200243#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_FLASH_CFI
245#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100246#endif
247
wdenk945af8d2003-07-16 21:53:01 +0000248
249/*
250 * Environment settings
251 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200252#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200253#define CONFIG_ENV_SIZE 0x10000
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100254#if defined(CONFIG_LITE5200B)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200255#define CONFIG_ENV_SECT_SIZE 0x20000
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100256#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200257#define CONFIG_ENV_SECT_SIZE 0x10000
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100258#endif
wdenk96e48cf2003-08-05 18:22:44 +0000259#define CONFIG_ENV_OVERWRITE 1
wdenk945af8d2003-07-16 21:53:01 +0000260
261/*
262 * Memory map
263 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_MBAR 0xF0000000
265#define CONFIG_SYS_SDRAM_BASE 0x00000000
266#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
wdenk945af8d2003-07-16 21:53:01 +0000267
268/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
270#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
wdenk945af8d2003-07-16 21:53:01 +0000271
272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
274#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
275#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk945af8d2003-07-16 21:53:01 +0000276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
278#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
279# define CONFIG_SYS_RAMBOOT 1
wdenk945af8d2003-07-16 21:53:01 +0000280#endif
281
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
283#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
284#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk945af8d2003-07-16 21:53:01 +0000285
286/*
287 * Ethernet configuration
288 */
wdenkcbd8a352004-02-24 02:00:03 +0000289#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800290#define CONFIG_MPC5xxx_FEC_MII100
wdenk04a85b32004-04-15 18:22:41 +0000291/*
Ben Warren86321fc2009-02-05 23:58:25 -0800292 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
wdenk7e780362004-04-08 22:31:29 +0000293 */
Ben Warren86321fc2009-02-05 23:58:25 -0800294/* #define CONFIG_MPC5xxx_FEC_MII10 */
wdenkd4ca31c2004-01-02 14:00:00 +0000295#define CONFIG_PHY_ADDR 0x00
wdenk945af8d2003-07-16 21:53:01 +0000296
297/*
298 * GPIO configuration
299 */
wdenkb2001f22003-12-20 22:45:10 +0000300#ifdef CONFIG_MPC5200_DDR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004
wdenkb2001f22003-12-20 22:45:10 +0000302#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
wdenkb2001f22003-12-20 22:45:10 +0000304#endif
wdenk945af8d2003-07-16 21:53:01 +0000305
306/*
307 * Miscellaneous configurable options
308 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_LONGHELP /* undef to save memory */
310#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500311#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk945af8d2003-07-16 21:53:01 +0000313#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk945af8d2003-07-16 21:53:01 +0000315#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
317#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
318#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk945af8d2003-07-16 21:53:01 +0000319
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
321#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenk945af8d2003-07-16 21:53:01 +0000322
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk945af8d2003-07-16 21:53:01 +0000324
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk945af8d2003-07-16 21:53:01 +0000326
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeliger348f2582007-07-08 13:46:18 -0500328#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeliger348f2582007-07-08 13:46:18 -0500330#endif
331
wdenk945af8d2003-07-16 21:53:01 +0000332/*
333 * Various low-level settings
334 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
336#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenk945af8d2003-07-16 21:53:01 +0000337
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100338#if defined(CONFIG_LITE5200B)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
340#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
341#define CONFIG_SYS_CS1_CFG 0x00047800
342#define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
343#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
344#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START
345#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
346#define CONFIG_SYS_BOOTCS_CFG 0x00047800
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100347#else /* IceCube aka Lite5200 */
wdenkb2001f22003-12-20 22:45:10 +0000348#ifdef CONFIG_MPC5200_DDR
349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
351#define CONFIG_SYS_BOOTCS_SIZE 0x00800000
352#define CONFIG_SYS_BOOTCS_CFG 0x00047801
353#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
354#define CONFIG_SYS_CS1_SIZE 0x00800000
355#define CONFIG_SYS_CS1_CFG 0x00047800
wdenkb2001f22003-12-20 22:45:10 +0000356
357#else /* !CONFIG_MPC5200_DDR */
358
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
360#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
361#define CONFIG_SYS_BOOTCS_CFG 0x00047801
362#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
363#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
wdenk945af8d2003-07-16 21:53:01 +0000364
wdenkb2001f22003-12-20 22:45:10 +0000365#endif /* CONFIG_MPC5200_DDR */
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100366#endif /*CONFIG_LITE5200B */
wdenkb2001f22003-12-20 22:45:10 +0000367
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_CS_BURST 0x00000000
369#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
wdenk945af8d2003-07-16 21:53:01 +0000370
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_RESET_ADDRESS 0xff000000
wdenk945af8d2003-07-16 21:53:01 +0000372
wdenk132ba5f2004-02-27 08:20:54 +0000373/*-----------------------------------------------------------------------
wdenkc3f9d492004-03-14 00:59:59 +0000374 * USB stuff
375 *-----------------------------------------------------------------------
376 */
wdenk4d13cba2004-03-14 14:09:05 +0000377#define CONFIG_USB_CLOCK 0x0001BBBB
378#define CONFIG_USB_CONFIG 0x00001000
wdenkc3f9d492004-03-14 00:59:59 +0000379
380/*-----------------------------------------------------------------------
wdenk132ba5f2004-02-27 08:20:54 +0000381 * IDE/ATA stuff Supports IDE harddisk
382 *-----------------------------------------------------------------------
383 */
384
385#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
386
387#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
388#undef CONFIG_IDE_LED /* LED for ide not supported */
389
390#define CONFIG_IDE_RESET /* reset for ide supported */
391#define CONFIG_IDE_PREINIT
392
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
394#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
wdenk132ba5f2004-02-27 08:20:54 +0000395
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk132ba5f2004-02-27 08:20:54 +0000397
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
wdenk132ba5f2004-02-27 08:20:54 +0000399
400/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
wdenk132ba5f2004-02-27 08:20:54 +0000402
403/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
wdenk132ba5f2004-02-27 08:20:54 +0000405
406/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
wdenk132ba5f2004-02-27 08:20:54 +0000408
409/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_ATA_STRIDE 4
wdenk132ba5f2004-02-27 08:20:54 +0000411
wdenk64f70be2004-09-28 20:34:50 +0000412#define CONFIG_ATAPI 1
413
wdenk945af8d2003-07-16 21:53:01 +0000414#endif /* __CONFIG_H */