blob: 3e57c0b92fe6ed0a59a969176343d06440d21312 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/***********************************************************
32 * High Level Configuration Options
33 * (easy to change)
34 ***********************************************************/
35#define CONFIG_405GP 1 /* This is a PPC405 CPU */
36#define CONFIG_4xx 1 /* ...member of PPC4xx family */
37#define CONFIG_PIP405 1 /* ...on a PIP405 board */
38/***********************************************************
39 * Clock
40 ***********************************************************/
41#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
42
Jon Loeligeracf02692007-07-08 14:49:44 -050043
44/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050045 * BOOTP options
46 */
47#define CONFIG_BOOTP_BOOTFILESIZE
48#define CONFIG_BOOTP_BOOTPATH
49#define CONFIG_BOOTP_GATEWAY
50#define CONFIG_BOOTP_HOSTNAME
51
52
53/*
Jon Loeligeracf02692007-07-08 14:49:44 -050054 * Command line configuration.
55 */
56#include <config_cmd_default.h>
57
58#define CONFIG_CMD_IDE
59#define CONFIG_CMD_DHCP
60#define CONFIG_CMD_PCI
61#define CONFIG_CMD_CACHE
62#define CONFIG_CMD_IRQ
63#define CONFIG_CMD_EEPROM
64#define CONFIG_CMD_I2C
65#define CONFIG_CMD_REGINFO
66#define CONFIG_CMD_FDC
67#define CONFIG_CMD_SCSI
68#define CONFIG_CMD_FAT
69#define CONFIG_CMD_DATE
70#define CONFIG_CMD_ELF
71#define CONFIG_CMD_USB
72#define CONFIG_CMD_MII
73#define CONFIG_CMD_SDRAM
Jon Loeligeracf02692007-07-08 14:49:44 -050074#define CONFIG_CMD_PING
75#define CONFIG_CMD_SAVES
76#define CONFIG_CMD_BSP
77
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_HUSH_PARSER
79#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkc6097192002-11-03 00:24:07 +000080/**************************************************************
81 * I2C Stuff:
82 * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
83 * 0x53.
84 * Caution: on the same bus is the SPD (Serial Presens Detect
85 * EEPROM of the SDRAM
86 * The Atmel EEPROM uses 16Bit addressing.
87 ***************************************************************/
88#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +020089#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
91#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkc6097192002-11-03 00:24:07 +000092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
94#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +020095#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020096#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
97#define CONFIG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
wdenkc6097192002-11-03 00:24:07 +000098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
100#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
wdenkc6097192002-11-03 00:24:07 +0000101 /* 64 byte page write mode using*/
102 /* last 6 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +0000104
105
106/***************************************************************
107 * Definitions for Serial Presence Detect EEPROM address
108 * (to get SDRAM settings)
109 ***************************************************************/
110#define SPD_EEPROM_ADDRESS 0x50
111
wdenkc837dcb2004-01-20 23:12:12 +0000112#define CONFIG_BOARD_EARLY_INIT_F
wdenkc6097192002-11-03 00:24:07 +0000113/**************************************************************
114 * Environment definitions
115 **************************************************************/
116#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
117
118
119#define CONFIG_BOOTDELAY 5
120/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
Wolfgang Denk2afbe4e2005-08-13 02:04:37 +0200121/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200122#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
wdenkc6097192002-11-03 00:24:07 +0000123
124
wdenk3e386912003-04-05 00:53:31 +0000125#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
wdenkc6097192002-11-03 00:24:07 +0000126#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
127
128#define CONFIG_IPADDR 10.0.0.100
129#define CONFIG_SERVERIP 10.0.0.1
130#define CONFIG_PREBOOT
131/***************************************************************
132 * defines if the console is stored in the environment
133 ***************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
wdenkc6097192002-11-03 00:24:07 +0000135/***************************************************************
136 * defines if an overwrite_console function exists
137 *************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
139#define CONFIG_SYS_CONSOLE_INFO_QUIET
wdenkc6097192002-11-03 00:24:07 +0000140/***************************************************************
141 * defines if the overwrite_console should be stored in the
142 * environment
143 **************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
wdenkc6097192002-11-03 00:24:07 +0000145
146/**************************************************************
147 * loads config
148 *************************************************************/
149#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +0000151
wdenk7205e402003-09-10 22:30:53 +0000152#define CONFIG_MISC_INIT_R
wdenkc6097192002-11-03 00:24:07 +0000153/***********************************************************
154 * Miscellaneous configurable options
155 **********************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_LONGHELP /* undef to save memory */
157#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligeracf02692007-07-08 14:49:44 -0500158#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000160#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000162#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
164#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
165#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
168#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
171#define CONFIG_SYS_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000172
173/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_BAUDRATE_TABLE \
wdenkc6097192002-11-03 00:24:07 +0000175 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
176 57600, 115200, 230400, 460800, 921600 }
177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
179#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkc6097192002-11-03 00:24:07 +0000180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000182
183/*-----------------------------------------------------------------------
184 * PCI stuff
185 *-----------------------------------------------------------------------
186 */
187#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
188#define PCI_HOST_FORCE 1 /* configure as pci host */
189#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
190
191#define CONFIG_PCI /* include pci support */
192#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
193#define CONFIG_PCI_PNP /* pci plug-and-play */
194 /* resource configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
196#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
197#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
198#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
199#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
200#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
201#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
202#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000203
204/*-----------------------------------------------------------------------
205 * Start addresses for the final memory configuration
206 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000208 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_SDRAM_BASE 0x00000000
210#define CONFIG_SYS_FLASH_BASE 0xFFF80000
211#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
212#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
213#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000214
215/*
216 * For booting Linux, the board info and command line data
217 * have to be in the first 8 MB of memory, since this is
218 * the maximum mapped by the Linux kernel during initialization.
219 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000221/*-----------------------------------------------------------------------
222 * FLASH organization
223 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
225#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
228#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000229
wdenkc6097192002-11-03 00:24:07 +0000230/*
231 * Init Memory Controller:
232 */
wdenk7205e402003-09-10 22:30:53 +0000233#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
234#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
235/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
236#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
wdenkc6097192002-11-03 00:24:07 +0000237
wdenkc837dcb2004-01-20 23:12:12 +0000238#define CONFIG_BOARD_EARLY_INIT_F
wdenkc6097192002-11-03 00:24:07 +0000239
240/* Configuration Port location */
241#define CONFIG_PORT_ADDR 0xF4000000
242#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
243
244
wdenkc6097192002-11-03 00:24:07 +0000245/*-----------------------------------------------------------------------
246 * Definitions for initial stack pointer and data area (in On Chip SRAM)
247 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_TEMP_STACK_OCM 1
249#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
250#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
251#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
252#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of On Chip SRAM */
253#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
254#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
255#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000256
257/*
258 * Internal Definitions
259 *
260 * Boot Flags
261 */
262#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
263#define BOOTFLAG_WARM 0x02 /* Software reboot */
264
265
266/***********************************************************************
267 * External peripheral base address
268 ***********************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
wdenkc6097192002-11-03 00:24:07 +0000270
271/***********************************************************************
272 * Last Stage Init
273 ***********************************************************************/
274#define CONFIG_LAST_STAGE_INIT
275/************************************************************
276 * Ethernet Stuff
277 ***********************************************************/
Ben Warren96e21f82008-10-27 23:50:15 -0700278#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +0000279#define CONFIG_MII 1 /* MII PHY management */
280#define CONFIG_PHY_ADDR 1 /* PHY address */
Ben Warren18cc7af2009-04-28 16:50:53 -0700281#define CONFIG_NET_MULTI
wdenkc6097192002-11-03 00:24:07 +0000282/************************************************************
283 * RTC
284 ***********************************************************/
285#define CONFIG_RTC_MC146818
286#undef CONFIG_WATCHDOG /* watchdog disabled */
287
288/************************************************************
289 * IDE/ATA stuff
290 ************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
292#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
295#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
296#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
297#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
298#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
299#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
wdenkc6097192002-11-03 00:24:07 +0000300
301#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
302#undef CONFIG_IDE_LED /* no led for ide supported */
303#define CONFIG_IDE_RESET /* reset for ide supported... */
304#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
wdenk7205e402003-09-10 22:30:53 +0000305#define CONFIG_SUPPORT_VFAT
wdenkc6097192002-11-03 00:24:07 +0000306
307/************************************************************
308 * ATAPI support (experimental)
309 ************************************************************/
310#define CONFIG_ATAPI /* enable ATAPI Support */
311
312/************************************************************
313 * SCSI support (experimental) only SYM53C8xx supported
314 ************************************************************/
315#define CONFIG_SCSI_SYM53C8XX
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
317#define CONFIG_SYS_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
318#define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
319#define CONFIG_SYS_SCSI_SPIN_UP_TIME 2
wdenkc6097192002-11-03 00:24:07 +0000320
321/************************************************************
322 * Disk-On-Chip configuration
323 ************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
325#define CONFIG_SYS_DOC_SHORT_TIMEOUT
326#define CONFIG_SYS_DOC_SUPPORT_2000
327#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
wdenkc6097192002-11-03 00:24:07 +0000328
329/************************************************************
330 * DISK Partition support
331 ************************************************************/
332#define CONFIG_DOS_PARTITION
333#define CONFIG_MAC_PARTITION
334#define CONFIG_ISO_PARTITION /* Experimental */
335
336/************************************************************
337 * Keyboard support
338 ************************************************************/
339#define CONFIG_ISA_KEYBOARD
340
341/************************************************************
342 * Video support
343 ************************************************************/
344#define CONFIG_VIDEO /*To enable video controller support */
345#define CONFIG_VIDEO_CT69000
346#define CONFIG_CFB_CONSOLE
347#define CONFIG_VIDEO_LOGO
348#define CONFIG_CONSOLE_EXTRA_INFO
349#define CONFIG_VGA_AS_SINGLE_DEVICE
350#define CONFIG_VIDEO_SW_CURSOR
351#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
352
353/************************************************************
354 * USB support
355 ************************************************************/
356#define CONFIG_USB_UHCI
357#define CONFIG_USB_KEYBOARD
358#define CONFIG_USB_STORAGE
359
360/* Enable needed helper functions */
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200361#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
wdenkc6097192002-11-03 00:24:07 +0000362
363/************************************************************
364 * Debug support
365 ************************************************************/
Jon Loeligeracf02692007-07-08 14:49:44 -0500366#if defined(CONFIG_CMD_KGDB)
wdenkc6097192002-11-03 00:24:07 +0000367#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
368#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
369#endif
370
371/************************************************************
wdenka2663ea2003-12-07 18:32:37 +0000372 * support BZIP2 compression
373 ************************************************************/
374#define CONFIG_BZIP2 1
375
376/************************************************************
wdenkc6097192002-11-03 00:24:07 +0000377 * Ident
378 ************************************************************/
379#define VERSION_TAG "released"
wdenkf3e0de62003-06-04 15:05:30 +0000380#define CONFIG_ISO_STRING "MEV-10066-001"
381#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
wdenkc6097192002-11-03 00:24:07 +0000382
383
384#endif /* __CONFIG_H */