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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 2e87980580d0bf4781ad0d63efd456aa1a73d03f / . / arch / arm / mach-davinci / Kconfig
blob: 30752839a3152999e7fbcaa21736010b7353c836 [file] [log] [blame]
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]1if ARCH_DAVINCI
2
3choice
4 prompt "DaVinci board select"
Joe Hershbergera26cd042015-05-12 14:46:23 -0500[diff] [blame]5 optional
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]6
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]7config TARGET_IPAM390
8 bool "IPAM390 board"
Adam Ford6aa4ad82018-01-11 08:20:27 -0600[diff] [blame]9 select MACH_DAVINCI_DA850_EVM
10 select SOC_DA850
Masahiro Yamada02627352014-10-20 17:45:56 +0900[diff] [blame]11 select SUPPORT_SPL
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]12
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]13config TARGET_DA850EVM
14 bool "DA850 EVM board"
Adam Ford6aa4ad82018-01-11 08:20:27 -0600[diff] [blame]15 select MACH_DAVINCI_DA850_EVM
16 select SOC_DA850
Masahiro Yamada02627352014-10-20 17:45:56 +0900[diff] [blame]17 select SUPPORT_SPL
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]18
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]19config TARGET_EA20
20 bool "EA20 board"
Adam Ford6aa4ad82018-01-11 08:20:27 -0600[diff] [blame]21 select MACH_DAVINCI_DA850_EVM
22 select SOC_DA850
Tom Rinie5ec4812017-01-22 19:43:11 -0500[diff] [blame]23 select BOARD_LATE_INIT
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]24
Simon Glass67619462015-08-30 19:18:59 -0600[diff] [blame]25config TARGET_OMAPL138_LCDK
26 bool "OMAPL138 LCDK"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame^]27 select SOC_DA8XX
Simon Glass67619462015-08-30 19:18:59 -0600[diff] [blame]28 select SUPPORT_SPL
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]29
30config TARGET_CALIMAIN
31 bool "Calimain board"
Adam Ford6aa4ad82018-01-11 08:20:27 -0600[diff] [blame]32 select SOC_DA850
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]33
David Lechner2ac07f72016-02-26 00:46:07 -0600[diff] [blame]34config TARGET_LEGOEV3
35 bool "LEGO MINDSTORMS EV3"
Adam Ford6aa4ad82018-01-11 08:20:27 -0600[diff] [blame]36 select MACH_DAVINCI_DA850_EVM
37 select SOC_DA850
David Lechner2ac07f72016-02-26 00:46:07 -0600[diff] [blame]38
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]39endchoice
40
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]41config SYS_SOC
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]42 default "davinci"
43
Adam Ford6aa4ad82018-01-11 08:20:27 -0600[diff] [blame]44config DA850_LOWLEVEL
45 bool "Enable Lowlevel DA850 initialization"
46 depends on SOC_DA850
47
Fabien Parentf519b362016-11-29 14:23:36 +0100[diff] [blame]48config SYS_DA850_PLL_INIT
49 bool
50
Fabien Parentb31bf372016-11-29 14:23:37 +0100[diff] [blame]51config SYS_DA850_DDR_INIT
52 bool
53
Adam Ford6aa4ad82018-01-11 08:20:27 -0600[diff] [blame]54config SOC_DA850
55 bool
56 select SOC_DA8XX
Adam Ford6aa4ad82018-01-11 08:20:27 -0600[diff] [blame]57
58config SOC_DA8XX
59 bool
60 select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
61
62config MACH_DAVINCI_DA850_EVM
63 bool
64
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]65if SYS_DA850_PLL_INIT
66comment "DA850 PLL Initialization Parameters"
67
68config SYS_DV_CLKMODE
69 int "PLLCTL Clock Mode"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame^]70 default 0
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]71 help
72 Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator
73
74config SYS_DA850_PLL0_POSTDIV
75 int "PLLC0 PLL Post-Divider"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame^]76 default 1
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]77 help
78 Value written to PLLC0 PLL Post-Divider Control Register
79
80config SYS_DA850_PLL0_PLLDIV1
81 hex "PLLC0 Divider 1"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame^]82 default 0x8000
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]83 help
84 Value written to PLLC0 Divider 1 register
85
86config SYS_DA850_PLL0_PLLDIV2
87 hex "PLLC0 Divider 2"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame^]88 default 0x8001
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]89 help
90 Value written to PLLC0 Divider 2 register
91
92config SYS_DA850_PLL0_PLLDIV3
93 hex "PLLC0 Divider 3"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame^]94 default 0x8002
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]95 help
96 Value written to PLLC0 Divider 3 register
97
98config SYS_DA850_PLL0_PLLDIV4
99 hex "PLLC0 Divider 4"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame^]100 default 0x8003
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]101 help
102 Value written to PLLC0 Divider 4 register
103
104config SYS_DA850_PLL0_PLLDIV5
105 hex "PLLC0 Divider 5"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame^]106 default 0x8002
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]107 help
108 Value written to PLLC0 Divider 5 register
109
110config SYS_DA850_PLL0_PLLDIV6
111 hex "PLLC0 Divider 6"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame^]112 default 0x8000
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]113 help
114 Value written to PLLC0 Divider 6 register
115
116config SYS_DA850_PLL0_PLLDIV7
117 hex "PLLC0 Divider 7"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame^]118 default 0x8005
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]119 help
120 Value written to PLLC0 Divider 7 register
121
122config SYS_DA850_PLL1_POSTDIV
123 hex "PLLC1 PLL Post-Divider"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame^]124 default 1
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]125 help
126 Value written to PLLC1 PLL Post-Divider Control Register
127
128config SYS_DA850_PLL1_PLLDIV1
129 hex "PLLC1 Divider 2"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame^]130 default 0x8000
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]131 help
132 Value written to PLLC1 Divider 1 register
133
134config SYS_DA850_PLL1_PLLDIV2
135 hex "PLLC1 Divider 2"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame^]136 default 0x8001
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]137 help
138 Value written to PLLC1 Divider 2 register
139
140config SYS_DA850_PLL1_PLLDIV3
141 hex "PLLC1 Divider 3"
Tom Rini2e879802018-01-31 15:34:49 -0500[diff] [blame^]142 default 0x8002
Adam Ford76e22222018-01-23 04:04:28 -0600[diff] [blame]143 help
144 Value written to PLLC1 Divider 3 register
145
146endif
147
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]148source "board/Barix/ipam390/Kconfig"
149source "board/davinci/da8xxevm/Kconfig"
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]150source "board/davinci/ea20/Kconfig"
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]151source "board/omicron/calimain/Kconfig"
David Lechner2ac07f72016-02-26 00:46:07 -0600[diff] [blame]152source "board/lego/ev3/Kconfig"
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]153
Philipp Tomsichb5299932017-08-03 23:23:55 +0200[diff] [blame]154config SPL_LDSCRIPT
155 default "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" if TARGET_IPAM390
156 default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
157
Masahiro Yamada3491ba62014-08-31 07:11:01 +0900[diff] [blame]158endif