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wdenkcd0a9de2004-02-23 20:48:38 +00001/*
2 * (C) Copyright 2004
3 * Tolunay Orkun, Nextio Inc., torkun@nextio.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
37#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */
wdenk4d13cba2004-03-14 14:09:05 +000039#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
wdenkcd0a9de2004-02-23 20:48:38 +000040#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
41#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
42
43/*
44 * OS Bootstrap configuration
45 *
46 */
47
48#if 0
49#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
50#else
51#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */
52#endif
53
54#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */
55
56#if 1
57#undef CONFIG_BOOTARGS
58#define CONFIG_BOOTCOMMAND \
59 "setenv bootargs console=ttyS0,38400 debug " \
60 "root=/dev/ram rw ramdisk_size=4096 " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010061 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenkcd0a9de2004-02-23 20:48:38 +000062 "bootm fe000000 fe100000"
63#endif
64
65#if 0
66#undef CONFIG_BOOTARGS
67#define CONFIG_BOOTCOMMAND \
68 "bootp; " \
69 "setenv bootargs console=ttyS0,38400 debug " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010070 "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenkcd0a9de2004-02-23 20:48:38 +000072 "bootm"
73#endif
74
75/*
Jon Loeliger2fd90ce2007-07-09 21:48:26 -050076 * BOOTP options
wdenkcd0a9de2004-02-23 20:48:38 +000077 */
Jon Loeliger2fd90ce2007-07-09 21:48:26 -050078#define CONFIG_BOOTP_SUBNETMASK
79#define CONFIG_BOOTP_GATEWAY
80#define CONFIG_BOOTP_HOSTNAME
81#define CONFIG_BOOTP_BOOTPATH
82#define CONFIG_BOOTP_BOOTFILESIZE
83#define CONFIG_BOOTP_DNS2
wdenkcd0a9de2004-02-23 20:48:38 +000084
Jon Loeliger37e4f242007-07-04 22:31:56 -050085
86/*
87 * Command line configuration.
88 */
89#include <config_cmd_default.h>
90
91#define CONFIG_CMD_ASKENV
92#define CONFIG_CMD_BEDBUG
93#define CONFIG_CMD_ELF
94#define CONFIG_CMD_IRQ
95#define CONFIG_CMD_I2C
96#define CONFIG_CMD_PCI
97#define CONFIG_CMD_DATE
98#define CONFIG_CMD_MII
99#define CONFIG_CMD_PING
100#define CONFIG_CMD_DHCP
101
wdenkcd0a9de2004-02-23 20:48:38 +0000102
103/*
104 * Serial download configuration
105 *
106 */
107#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
108#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
109
110/*
111 * KGDB Configuration
112 *
113 */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500114#if defined(CONFIG_CMD_KGDB)
wdenkcd0a9de2004-02-23 20:48:38 +0000115#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
116#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
117#endif
118
119/*
120 * Miscellaneous configurable options
121 *
122 */
123#undef CFG_HUSH_PARSER /* use "hush" command parser */
124#ifdef CFG_HUSH_PARSER
125#define CFG_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */
126#endif
127
128#define CFG_LONGHELP /* undef to save memory */
129#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500130#if defined(CONFIG_CMD_KGDB)
wdenkcd0a9de2004-02-23 20:48:38 +0000131#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
132#else
133#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
134#endif
135#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
136#define CFG_MAXARGS 16 /* max number of command args */
137#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
138
139#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
140#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
141
142#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
143#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
144#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */
145#define CFG_LOAD_ADDR 0x100000 /* default load address */
146
147/*
148 * For booting Linux, the board info and command line data
149 * have to be in the first 8 MB of memory, since this is
150 * the maximum mapped by the Linux kernel during initialization.
151 */
152#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
153
154/*
155 * watchdog configuration
156 *
157 */
158#undef CONFIG_WATCHDOG /* watchdog disabled */
159
160/*
161 * UART configuration
162 *
163 */
164#define CFG_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */
165#undef CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
166#undef CFG_BASE_BAUD
167#define CONFIG_BAUDRATE 38400 /* Default baud rate */
168#define CFG_BAUDRATE_TABLE \
169 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
170
171/*
172 * I2C configuration
173 *
174 */
175#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
176#define CFG_I2C_SPEED 100000 /* I2C speed */
177#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
178
179/*
180 * MII PHY configuration
181 *
182 */
183#define CONFIG_MII 1 /* MII PHY management */
184#define CONFIG_PHY_ADDR 0 /* PHY address */
185#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
186 /* 32usec min. for LXT971A */
187#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
188
189/*
190 * RTC configuration
191 *
192 * Note that DS1307 RTC is limited to 100Khz I2C bus.
193 *
194 */
195#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */
196
197/*
198 * PCI stuff
199 *
200 */
201#define CONFIG_PCI /* include pci support */
202#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
203#define PCI_HOST_FORCE 1 /* configure as pci host */
204#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
205
206#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
207#define CONFIG_PCI_PNP /* do pci plug-and-play */
208 /* resource configuration */
209#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
210#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
211
212#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
213#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
214#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
215#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
216#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
217#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
218#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
219#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
220
221/*
222 * IDE stuff
223 *
224 */
225#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
226#undef CONFIG_IDE_LED /* no led for ide supported */
227#undef CONFIG_IDE_RESET /* no reset for ide supported */
228
229/*
230 * Environment configuration
231 *
232 */
233#define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
234#undef CFG_ENV_IS_IN_NVRAM
235#undef CFG_ENV_IS_IN_EEPROM
236
237/*
238 * General Memory organization
239 *
240 * Start addresses for the final memory configuration
241 * (Set up by the startup code)
242 * Please note that CFG_SDRAM_BASE _must_ start at 0
243 */
244#define CFG_SDRAM_BASE 0x00000000
245#define CFG_FLASH_BASE 0xFE000000
246#define CFG_FLASH_SIZE 0x02000000
247#define CFG_MONITOR_BASE TEXT_BASE
248#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
249#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
250
251#if CFG_MONITOR_BASE < CFG_FLASH_BASE
252#define CFG_RAMSTART
253#endif
254
255#if defined(CFG_ENV_IS_IN_FLASH)
256#define CFG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
257#define CFG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
258#define CFG_ENV_SIZE 0x00001000 /* Size of Environment */
259#define CFG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
260#endif
261
262/*
263 * FLASH Device configuration
264 *
265 */
266#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
267#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
268#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
269#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
270#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
271#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
272#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
273#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
274
275/*
276 * On Chip Memory location/size
277 *
278 */
279#define CFG_OCM_DATA_ADDR 0xF8000000
280#define CFG_OCM_DATA_SIZE 0x1000
281
282/*
283 * Global info and initial stack
284 *
285 */
286#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */
287#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
288#define CFG_GBL_DATA_SIZE 128 /* byte size reserved for initial data */
289#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
290#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
291
292/*
293 * Cache configuration
294 *
295 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200296#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
wdenkcd0a9de2004-02-23 20:48:38 +0000297 /* have only 8kB, 16kB is save here */
298#define CFG_CACHELINE_SIZE 32
299
300/*
301 * Miscellaneous board specific definitions
302 *
303 */
304#define CFG_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */
wdenkeeb1b772004-03-23 22:53:55 +0000305#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */
wdenkcd0a9de2004-02-23 20:48:38 +0000306
307/*
308 * Internal Definitions
309 *
310 * Boot Flags
311 *
312 */
313#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
314#define BOOTFLAG_WARM 0x02 /* Software reboot */
315
316#endif /* __CONFIG_H */