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Tom Warren3f82b1d2011-01-27 10:58:05 +00001/*
Tom Warren7aaa5a62015-03-04 16:36:00 -07002 * (C) Copyright 2010-2015
Tom Warren3f82b1d2011-01-27 10:58:05 +00003 * NVIDIA Corporation <www.nvidia.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Tom Warren3f82b1d2011-01-27 10:58:05 +00006 */
7
8#include <common.h>
Thomas Chou18746262015-11-19 21:48:11 +08009#include <dm.h>
10#include <ns16550.h>
Simon Glass537e9672015-05-13 07:02:29 -060011#include <spl.h>
Tom Warren3f82b1d2011-01-27 10:58:05 +000012#include <asm/io.h>
Simon Glassbb6997f2011-11-28 15:04:39 +000013#include <asm/arch/clock.h>
14#include <asm/arch/funcmux.h>
Marcel Ziswiler8c33ba72014-10-10 23:32:32 +020015#include <asm/arch/mc.h>
Tom Warren150c2492012-09-19 15:50:56 -070016#include <asm/arch/tegra.h>
Stephen Warren73c38932015-01-19 16:25:52 -070017#include <asm/arch-tegra/ap.h>
Lucas Stach516f00b2012-09-29 10:02:08 +000018#include <asm/arch-tegra/board.h>
Tom Warren150c2492012-09-19 15:50:56 -070019#include <asm/arch-tegra/pmc.h>
20#include <asm/arch-tegra/sys_proto.h>
21#include <asm/arch-tegra/warmboot.h>
Tom Warren3f82b1d2011-01-27 10:58:05 +000022
Tom Warren659a0752015-07-08 08:05:35 -070023void save_boot_params_ret(void);
24
Tom Warren3f82b1d2011-01-27 10:58:05 +000025DECLARE_GLOBAL_DATA_PTR;
26
Simon Glassbb6997f2011-11-28 15:04:39 +000027enum {
28 /* UARTs which we can enable */
29 UARTA = 1 << 0,
30 UARTB = 1 << 1,
Tom Warrene23bb6a2013-01-28 13:32:10 +000031 UARTC = 1 << 2,
Simon Glassbb6997f2011-11-28 15:04:39 +000032 UARTD = 1 << 3,
Tom Warrene23bb6a2013-01-28 13:32:10 +000033 UARTE = 1 << 4,
34 UART_COUNT = 5,
Simon Glassbb6997f2011-11-28 15:04:39 +000035};
36
Simon Glass537e9672015-05-13 07:02:29 -060037static bool from_spl __attribute__ ((section(".data")));
38
39#ifndef CONFIG_SPL_BUILD
40void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
41{
42 from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
43 save_boot_params_ret();
44}
45#endif
46
47bool spl_was_boot_source(void)
48{
49 return from_spl;
50}
51
Stephen Warren73c38932015-01-19 16:25:52 -070052#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
53#if !defined(CONFIG_TEGRA124)
54#error tegra_cpu_is_non_secure has only been validated on Tegra124
55#endif
56bool tegra_cpu_is_non_secure(void)
57{
58 /*
59 * This register reads 0xffffffff in non-secure mode. This register
60 * only implements bits 31:20, so the lower bits will always read 0 in
61 * secure mode. Thus, the lower bits are an indicator for secure vs.
62 * non-secure mode.
63 */
64 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
65 uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
66 return (mc_s_cfg0 & 1) == 1;
67}
68#endif
69
Stephen Warrenaeb3fcb2014-07-02 14:12:30 -060070/* Read the RAM size directly from the memory controller */
Stephen Warrena5fc3d02015-08-07 16:12:44 -060071static phys_size_t query_sdram_size(void)
Stephen Warrenaeb3fcb2014-07-02 14:12:30 -060072{
73 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
Stephen Warrena5fc3d02015-08-07 16:12:44 -060074 u32 emem_cfg;
75 phys_size_t size_bytes;
Stephen Warrenaeb3fcb2014-07-02 14:12:30 -060076
Stephen Warren3a2cab52014-12-23 10:34:50 -070077 emem_cfg = readl(&mc->mc_emem_cfg);
Marcel Ziswiler8c33ba72014-10-10 23:32:32 +020078#if defined(CONFIG_TEGRA20)
Stephen Warren3a2cab52014-12-23 10:34:50 -070079 debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
80 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
Marcel Ziswiler8c33ba72014-10-10 23:32:32 +020081#else
Stephen Warren3a2cab52014-12-23 10:34:50 -070082 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
Stephen Warrena5fc3d02015-08-07 16:12:44 -060083#ifndef CONFIG_PHYS_64BIT
Stephen Warren56519c42014-12-23 10:34:51 -070084 /*
85 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
86 * and will wrap. Clip the reported size to the maximum that a 32-bit
87 * variable can represent (rounded to a page).
88 */
89 if (emem_cfg >= 4096) {
90 size_bytes = U32_MAX & ~(0x1000 - 1);
Stephen Warrena5fc3d02015-08-07 16:12:44 -060091 } else
92#endif
93 {
Stephen Warren56519c42014-12-23 10:34:51 -070094 /* RAM size EMC is programmed to. */
Stephen Warrena5fc3d02015-08-07 16:12:44 -060095 size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
96#ifndef CONFIG_ARM64
Stephen Warren56519c42014-12-23 10:34:51 -070097 /*
98 * If all RAM fits within 32-bits, it can be accessed without
99 * LPAE, so go test the RAM size. Otherwise, we can't access
100 * all the RAM, and get_ram_size() would get confused, so
101 * avoid using it. There's no reason we should need this
102 * validation step anyway.
103 */
104 if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
105 size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
106 size_bytes);
Stephen Warrena5fc3d02015-08-07 16:12:44 -0600107#endif
Stephen Warren56519c42014-12-23 10:34:51 -0700108 }
Stephen Warrenaeb3fcb2014-07-02 14:12:30 -0600109#endif
Tom Warren3f82b1d2011-01-27 10:58:05 +0000110
Marcel Ziswiler8c33ba72014-10-10 23:32:32 +0200111#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
112 /* External memory limited to 2047 MB due to IROM/HI-VEC */
Stephen Warren3a2cab52014-12-23 10:34:50 -0700113 if (size_bytes == SZ_2G)
114 size_bytes -= SZ_1M;
Marcel Ziswiler8c33ba72014-10-10 23:32:32 +0200115#endif
116
Stephen Warren3a2cab52014-12-23 10:34:50 -0700117 return size_bytes;
Marcel Ziswiler8c33ba72014-10-10 23:32:32 +0200118}
119
Tom Warren3f82b1d2011-01-27 10:58:05 +0000120int dram_init(void)
121{
Tom Warren3f82b1d2011-01-27 10:58:05 +0000122 /* We do not initialise DRAM here. We just query the size */
Simon Glass7f8c0702011-11-05 03:56:57 +0000123 gd->ram_size = query_sdram_size();
Tom Warren3f82b1d2011-01-27 10:58:05 +0000124 return 0;
125}
126
Stephen Warrenb9607e72012-05-14 13:13:45 +0000127static int uart_configs[] = {
Tom Warrenb2871032012-12-11 13:34:15 +0000128#if defined(CONFIG_TEGRA20)
129 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
Stephen Warrenb9607e72012-05-14 13:13:45 +0000130 FUNCMUX_UART1_UAA_UAB,
Tom Warrenb2871032012-12-11 13:34:15 +0000131 #elif defined(CONFIG_TEGRA_UARTA_GPU)
Stephen Warrene21649b2012-05-16 05:59:59 +0000132 FUNCMUX_UART1_GPU,
Tom Warrenb2871032012-12-11 13:34:15 +0000133 #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
Lucas Stacha2cfe632012-05-16 08:21:02 +0000134 FUNCMUX_UART1_SDIO1,
Tom Warrenb2871032012-12-11 13:34:15 +0000135 #else
Stephen Warrenb9607e72012-05-14 13:13:45 +0000136 FUNCMUX_UART1_IRRX_IRTX,
Stephen Warren4727a132013-01-22 06:20:08 +0000137#endif
138 FUNCMUX_UART2_UAD,
Stephen Warrenb9607e72012-05-14 13:13:45 +0000139 -1,
140 FUNCMUX_UART4_GMC,
141 -1,
Tom Warrene23bb6a2013-01-28 13:32:10 +0000142#elif defined(CONFIG_TEGRA30)
Tom Warrenb2871032012-12-11 13:34:15 +0000143 FUNCMUX_UART1_ULPI, /* UARTA */
144 -1,
145 -1,
146 -1,
147 -1,
Tom Warren2f5dac92014-01-24 12:46:16 -0700148#elif defined(CONFIG_TEGRA114)
Tom Warrene23bb6a2013-01-28 13:32:10 +0000149 -1,
150 -1,
151 -1,
152 FUNCMUX_UART4_GMI, /* UARTD */
153 -1,
Tom Warren7aaa5a62015-03-04 16:36:00 -0700154#elif defined(CONFIG_TEGRA124)
Tom Warren2f5dac92014-01-24 12:46:16 -0700155 FUNCMUX_UART1_KBC, /* UARTA */
156 -1,
157 -1,
158 FUNCMUX_UART4_GPIO, /* UARTD */
159 -1,
Tom Warren7aaa5a62015-03-04 16:36:00 -0700160#else /* Tegra210 */
161 FUNCMUX_UART1_UART1, /* UARTA */
162 -1,
163 -1,
164 FUNCMUX_UART4_UART4, /* UARTD */
165 -1,
Tom Warrenb2871032012-12-11 13:34:15 +0000166#endif
Stephen Warrenb9607e72012-05-14 13:13:45 +0000167};
168
Simon Glassbb6997f2011-11-28 15:04:39 +0000169/**
170 * Set up the specified uarts
171 *
172 * @param uarts_ids Mask containing UARTs to init (UARTx)
173 */
174static void setup_uarts(int uart_ids)
175{
176 static enum periph_id id_for_uart[] = {
177 PERIPH_ID_UART1,
178 PERIPH_ID_UART2,
179 PERIPH_ID_UART3,
180 PERIPH_ID_UART4,
Tom Warrene23bb6a2013-01-28 13:32:10 +0000181 PERIPH_ID_UART5,
Simon Glassbb6997f2011-11-28 15:04:39 +0000182 };
183 size_t i;
184
185 for (i = 0; i < UART_COUNT; i++) {
186 if (uart_ids & (1 << i)) {
187 enum periph_id id = id_for_uart[i];
188
Stephen Warrenb9607e72012-05-14 13:13:45 +0000189 funcmux_select(id, uart_configs[i]);
Simon Glassbb6997f2011-11-28 15:04:39 +0000190 clock_ll_start_uart(id);
191 }
192 }
193}
194
195void board_init_uart_f(void)
196{
197 int uart_ids = 0; /* bit mask of which UART ids to enable */
198
Tom Warren29f3e3f2012-09-04 17:00:24 -0700199#ifdef CONFIG_TEGRA_ENABLE_UARTA
Simon Glassbb6997f2011-11-28 15:04:39 +0000200 uart_ids |= UARTA;
201#endif
Tom Warren29f3e3f2012-09-04 17:00:24 -0700202#ifdef CONFIG_TEGRA_ENABLE_UARTB
Simon Glassbb6997f2011-11-28 15:04:39 +0000203 uart_ids |= UARTB;
204#endif
Tom Warrene23bb6a2013-01-28 13:32:10 +0000205#ifdef CONFIG_TEGRA_ENABLE_UARTC
206 uart_ids |= UARTC;
207#endif
Tom Warren29f3e3f2012-09-04 17:00:24 -0700208#ifdef CONFIG_TEGRA_ENABLE_UARTD
Simon Glassbb6997f2011-11-28 15:04:39 +0000209 uart_ids |= UARTD;
210#endif
Tom Warrene23bb6a2013-01-28 13:32:10 +0000211#ifdef CONFIG_TEGRA_ENABLE_UARTE
212 uart_ids |= UARTE;
213#endif
Simon Glassbb6997f2011-11-28 15:04:39 +0000214 setup_uarts(uart_ids);
215}
Simon Glassbd29cb02012-01-09 13:22:15 +0000216
Simon Glass878a3ed2015-12-04 08:58:39 -0700217#if !CONFIG_IS_ENABLED(OF_CONTROL)
Thomas Chou18746262015-11-19 21:48:11 +0800218static struct ns16550_platdata ns16550_com1_pdata = {
219 .base = CONFIG_SYS_NS16550_COM1,
220 .reg_shift = 2,
221 .clock = CONFIG_SYS_NS16550_CLK,
222};
223
224U_BOOT_DEVICE(ns16550_com1) = {
225 "ns16550_serial", &ns16550_com1_pdata
226};
227#endif
228
Thierry Reding32b32342015-07-27 11:45:25 -0600229#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
Simon Glassbd29cb02012-01-09 13:22:15 +0000230void enable_caches(void)
231{
232 /* Enable D-cache. I-cache is already enabled in start.S */
233 dcache_enable();
234}
235#endif