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wdenk12f34242003-09-02 22:48:03 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
4 *
wdenkfbe4b5c2003-10-06 21:55:32 +00005 * (C) Copyright 2003
6 * DAVE Srl
wdenk12f34242003-09-02 22:48:03 +00007 *
wdenkfbe4b5c2003-10-06 21:55:32 +00008 * http://www.dave-tech.it
9 * http://www.wawnet.biz
10 * mailto:info@wawnet.biz
11 *
12 * Credits: Stefan Roese, Wolfgang Denk
wdenk12f34242003-09-02 22:48:03 +000013 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30/*
31 * board/config.h - configuration options, board specific
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
wdenk42d1f032003-10-15 23:53:47 +000037#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
wdenkfbe4b5c2003-10-06 21:55:32 +000038#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
39#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
wdenkc837dcb2004-01-20 23:12:12 +000040#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
41#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
wdenkfbe4b5c2003-10-06 21:55:32 +000042#endif
43
wdenke55ca7e2004-07-01 21:40:08 +000044
45/* Only one of the following two symbols must be defined (default is 25 MHz)
46 * CONFIG_PPCHAMELEON_CLK_25
47 * CONFIG_PPCHAMELEON_CLK_33
48 */
wdenk281e00a2004-08-01 22:48:16 +000049#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
Wolfgang Denk0f18cb62005-07-31 00:30:09 +020050#define CONFIG_PPCHAMELEON_CLK_25
wdenk281e00a2004-08-01 22:48:16 +000051#endif
wdenke55ca7e2004-07-01 21:40:08 +000052
53#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
54#error "* Two external frequencies (SysClk) are defined! *"
55#endif
56
57#undef CONFIG_PPCHAMELEON_SMI712
58
wdenk12f34242003-09-02 22:48:03 +000059/*
60 * Debug stuff
61 */
wdenkc837dcb2004-01-20 23:12:12 +000062#undef __DEBUG_START_FROM_SRAM__
wdenk12f34242003-09-02 22:48:03 +000063#define __DISABLE_MACHINE_EXCEPTION__
64
65#ifdef __DEBUG_START_FROM_SRAM__
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
wdenk12f34242003-09-02 22:48:03 +000067#endif
68
69/*
70 * High Level Configuration Options
71 * (easy to change)
72 */
73
74#define CONFIG_405EP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000075#define CONFIG_4xx 1 /* ...member of PPC4xx family */
76#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
wdenk12f34242003-09-02 22:48:03 +000077
wdenkc837dcb2004-01-20 23:12:12 +000078#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
79#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
wdenk12f34242003-09-02 22:48:03 +000080
wdenke55ca7e2004-07-01 21:40:08 +000081
82#ifdef CONFIG_PPCHAMELEON_CLK_25
wdenk281e00a2004-08-01 22:48:16 +000083# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
wdenke55ca7e2004-07-01 21:40:08 +000084#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
wdenk281e00a2004-08-01 22:48:16 +000085# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
wdenke55ca7e2004-07-01 21:40:08 +000086#else
wdenk281e00a2004-08-01 22:48:16 +000087# error "* External frequency (SysClk) not defined! *"
wdenke55ca7e2004-07-01 21:40:08 +000088#endif
wdenk12f34242003-09-02 22:48:03 +000089
wdenk12f34242003-09-02 22:48:03 +000090#define CONFIG_BAUDRATE 115200
wdenk4d816772003-09-03 14:03:26 +000091#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk12f34242003-09-02 22:48:03 +000092
wdenk12f34242003-09-02 22:48:03 +000093#undef CONFIG_BOOTARGS
wdenk12f34242003-09-02 22:48:03 +000094
wdenk200f8c72003-09-13 19:13:29 +000095/* Ethernet stuff */
96#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
97#define CONFIG_ETHADDR 00:50:c2:1e:af:fe
wdenke2ffd592004-12-31 09:32:47 +000098#define CONFIG_HAS_ETH1
wdenkc837dcb2004-01-20 23:12:12 +000099#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
wdenk12f34242003-09-02 22:48:03 +0000100
101#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk12f34242003-09-02 22:48:03 +0000103
wdenk12f34242003-09-02 22:48:03 +0000104#undef CONFIG_EXT_PHY
wdenkcea655a2004-06-06 23:53:59 +0000105#define CONFIG_NET_MULTI 1
wdenk4d816772003-09-03 14:03:26 +0000106
Ben Warren96e21f82008-10-27 23:50:15 -0700107#define CONFIG_PPC4xx_EMAC
wdenk12f34242003-09-02 22:48:03 +0000108#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +0000109#ifndef CONFIG_EXT_PHY
stroesebf418862005-06-30 13:06:07 +0000110#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
111#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
wdenk12f34242003-09-02 22:48:03 +0000112#else
wdenkc837dcb2004-01-20 23:12:12 +0000113#define CONFIG_PHY_ADDR 2 /* PHY address */
wdenk12f34242003-09-02 22:48:03 +0000114#endif
wdenkc837dcb2004-01-20 23:12:12 +0000115#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
wdenk12f34242003-09-02 22:48:03 +0000116
Jon Loeligeracf02692007-07-08 14:49:44 -0500117
118/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500119 * BOOTP options
120 */
121#define CONFIG_BOOTP_BOOTFILESIZE
122#define CONFIG_BOOTP_BOOTPATH
123#define CONFIG_BOOTP_GATEWAY
124#define CONFIG_BOOTP_HOSTNAME
125
126
127/*
Jon Loeligeracf02692007-07-08 14:49:44 -0500128 * Command line configuration.
129 */
130#include <config_cmd_default.h>
131
132#define CONFIG_CMD_DATE
133#define CONFIG_CMD_DHCP
134#define CONFIG_CMD_ELF
135#define CONFIG_CMD_EEPROM
136#define CONFIG_CMD_I2C
137#define CONFIG_CMD_IRQ
138#define CONFIG_CMD_JFFS2
139#define CONFIG_CMD_MII
140#define CONFIG_CMD_NAND
141#define CONFIG_CMD_NFS
142#define CONFIG_CMD_PCI
143#define CONFIG_CMD_SNTP
144
wdenk12f34242003-09-02 22:48:03 +0000145
146#define CONFIG_MAC_PARTITION
147#define CONFIG_DOS_PARTITION
148
wdenkc837dcb2004-01-20 23:12:12 +0000149#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk12f34242003-09-02 22:48:03 +0000150
wdenke6325152005-03-17 16:43:10 +0000151#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_I2C_RTC_ADDR 0x68
153#define CONFIG_SYS_M41T11_BASE_YEAR 1900
wdenk12f34242003-09-02 22:48:03 +0000154
Stefan Roese62534be2006-03-17 10:28:24 +0100155/*
156 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
157 */
wdenkc837dcb2004-01-20 23:12:12 +0000158#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenk12f34242003-09-02 22:48:03 +0000159
Stefan Roese62534be2006-03-17 10:28:24 +0100160/* SDRAM timings used in datasheet */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_SDRAM_CL 2
162#define CONFIG_SYS_SDRAM_tRP 20
163#define CONFIG_SYS_SDRAM_tRC 65
164#define CONFIG_SYS_SDRAM_tRCD 20
165#undef CONFIG_SYS_SDRAM_tRFC
Stefan Roese62534be2006-03-17 10:28:24 +0100166
wdenk12f34242003-09-02 22:48:03 +0000167/*
168 * Miscellaneous configurable options
169 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_LONGHELP /* undef to save memory */
171#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk12f34242003-09-02 22:48:03 +0000172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
174#ifdef CONFIG_SYS_HUSH_PARSER
175#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk12f34242003-09-02 22:48:03 +0000176#endif
177
Jon Loeligeracf02692007-07-08 14:49:44 -0500178#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk12f34242003-09-02 22:48:03 +0000180#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk12f34242003-09-02 22:48:03 +0000182#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
184#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
185#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk12f34242003-09-02 22:48:03 +0000186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
wdenk12f34242003-09-02 22:48:03 +0000188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenk12f34242003-09-02 22:48:03 +0000190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
192#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk12f34242003-09-02 22:48:03 +0000193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_BASE_BAUD 691200
wdenk12f34242003-09-02 22:48:03 +0000196
197/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk42d1f032003-10-15 23:53:47 +0000199 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
200 57600, 115200, 230400, 460800, 921600 }
wdenk12f34242003-09-02 22:48:03 +0000201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
203#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenk12f34242003-09-02 22:48:03 +0000204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk12f34242003-09-02 22:48:03 +0000206
207#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
208
209/*-----------------------------------------------------------------------
210 * NAND-FLASH stuff
211 *-----------------------------------------------------------------------
212 */
Wolfgang Denk170c1972009-07-18 15:32:10 +0200213
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100214/*
215 * nand device 1 on dave (PPChameleonEVB) needs more time,
216 * so we just introduce additional wait in nand_wait(),
217 * effectively for both devices.
218 */
219#define PPCHAMELON_NAND_TIMER_HACK
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_NAND0_BASE 0xFF400000
222#define CONFIG_SYS_NAND1_BASE 0xFF000000
223#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE }
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100224#define NAND_BIG_DELAY_US 25
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
wdenk12f34242003-09-02 22:48:03 +0000226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
228#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
229#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
230#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
wdenk12f34242003-09-02 22:48:03 +0000231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
233#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
234#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
235#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
wdenk12f34242003-09-02 22:48:03 +0000236
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100237#define MACRO_NAND_DISABLE_CE(nandptr) do \
238{ \
239 switch((unsigned long)nandptr) \
240 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241 case CONFIG_SYS_NAND0_BASE: \
242 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100243 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244 case CONFIG_SYS_NAND1_BASE: \
245 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100246 break; \
247 } \
248} while(0)
249
250#define MACRO_NAND_ENABLE_CE(nandptr) do \
251{ \
252 switch((unsigned long)nandptr) \
253 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254 case CONFIG_SYS_NAND0_BASE: \
255 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100256 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257 case CONFIG_SYS_NAND1_BASE: \
258 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100259 break; \
260 } \
261} while(0)
262
263#define MACRO_NAND_CTL_CLRALE(nandptr) do \
264{ \
265 switch((unsigned long)nandptr) \
266 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267 case CONFIG_SYS_NAND0_BASE: \
268 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100269 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270 case CONFIG_SYS_NAND1_BASE: \
271 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100272 break; \
273 } \
274} while(0)
275
276#define MACRO_NAND_CTL_SETALE(nandptr) do \
277{ \
278 switch((unsigned long)nandptr) \
279 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280 case CONFIG_SYS_NAND0_BASE: \
281 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100282 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283 case CONFIG_SYS_NAND1_BASE: \
284 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100285 break; \
286 } \
287} while(0)
288
289#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
290{ \
291 switch((unsigned long)nandptr) \
292 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293 case CONFIG_SYS_NAND0_BASE: \
294 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100295 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296 case CONFIG_SYS_NAND1_BASE: \
297 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100298 break; \
299 } \
300} while(0)
301
302#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
303 switch((unsigned long)nandptr) { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304 case CONFIG_SYS_NAND0_BASE: \
305 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100306 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307 case CONFIG_SYS_NAND1_BASE: \
308 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100309 break; \
310 } \
311} while(0)
wdenk12f34242003-09-02 22:48:03 +0000312
wdenk12f34242003-09-02 22:48:03 +0000313/*-----------------------------------------------------------------------
314 * PCI stuff
315 *-----------------------------------------------------------------------
316 */
wdenkc837dcb2004-01-20 23:12:12 +0000317#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
318#define PCI_HOST_FORCE 1 /* configure as pci host */
319#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenk12f34242003-09-02 22:48:03 +0000320
wdenkc837dcb2004-01-20 23:12:12 +0000321#define CONFIG_PCI /* include pci support */
322#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
323#undef CONFIG_PCI_PNP /* do pci plug-and-play */
324 /* resource configuration */
wdenk12f34242003-09-02 22:48:03 +0000325
wdenkc837dcb2004-01-20 23:12:12 +0000326#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenk12f34242003-09-02 22:48:03 +0000327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
329#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
330#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
wdenke55ca7e2004-07-01 21:40:08 +0000331
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
333#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
334#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
335#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
336#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
337#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenk12f34242003-09-02 22:48:03 +0000338
339/*-----------------------------------------------------------------------
340 * Start addresses for the final memory configuration
341 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk12f34242003-09-02 22:48:03 +0000343 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_SDRAM_BASE 0x00000000
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200345
346/* Reserve 256 kB for Monitor */
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100347/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
349#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
350#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100351*/
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200352
353/* Reserve 320 kB for Monitor */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_FLASH_BASE 0xFFFB0000
355#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
356#define CONFIG_SYS_MONITOR_LEN (320 * 1024)
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200357
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
wdenk12f34242003-09-02 22:48:03 +0000359
360/*
361 * For booting Linux, the board info and command line data
362 * have to be in the first 8 MB of memory, since this is
363 * the maximum mapped by the Linux kernel during initialization.
364 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk12f34242003-09-02 22:48:03 +0000366/*-----------------------------------------------------------------------
367 * FLASH organization
368 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
370#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk12f34242003-09-02 22:48:03 +0000371
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
373#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
wdenk12f34242003-09-02 22:48:03 +0000374
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
376#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
377#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenk12f34242003-09-02 22:48:03 +0000378/*
379 * The following defines are added for buggy IOP480 byte interface.
380 * All other boards should use the standard values (CPCI405 etc.)
381 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
383#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
384#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenk12f34242003-09-02 22:48:03 +0000385
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenk12f34242003-09-02 22:48:03 +0000387
wdenk12f34242003-09-02 22:48:03 +0000388/*-----------------------------------------------------------------------
389 * Environment Variable setup
390 */
wdenke55ca7e2004-07-01 21:40:08 +0000391#ifdef ENVIRONMENT_IN_EEPROM
392
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200393#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200394#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
395#define CONFIG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
wdenke55ca7e2004-07-01 21:40:08 +0000396
397#else /* DEFAULT: environment in flash, using redundand flash sectors */
398
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200399#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200400#define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
401#define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
402#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
403#define CONFIG_ENV_SIZE_REDUND 0x2000
wdenk12f34242003-09-02 22:48:03 +0000404
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200406
wdenke55ca7e2004-07-01 21:40:08 +0000407#endif /* ENVIRONMENT_IN_EEPROM */
408
409
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
411#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
wdenk12f34242003-09-02 22:48:03 +0000412
413/*-----------------------------------------------------------------------
414 * I2C EEPROM (CAT24WC16) for environment
415 */
416#define CONFIG_HARD_I2C /* I2c with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
418#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk12f34242003-09-02 22:48:03 +0000419
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
421#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +0000422/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
424#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenk12f34242003-09-02 22:48:03 +0000425 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000426 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenk12f34242003-09-02 22:48:03 +0000428
wdenk12f34242003-09-02 22:48:03 +0000429/*
430 * Init Memory Controller:
431 *
432 * BR0/1 and OR0/1 (FLASH)
433 */
434
435#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
436
437/*-----------------------------------------------------------------------
438 * External Bus Controller (EBC) Setup
439 */
440
wdenkc837dcb2004-01-20 23:12:12 +0000441/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_EBC_PB0AP 0x92015480
443#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenk12f34242003-09-02 22:48:03 +0000444
wdenkc837dcb2004-01-20 23:12:12 +0000445/* Memory Bank 1 (External SRAM) initialization */
wdenk12f34242003-09-02 22:48:03 +0000446/* Since this must replace NOR Flash, we use the same settings for CS0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_EBC_PB1AP 0x92015480
448#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
wdenk12f34242003-09-02 22:48:03 +0000449
wdenkc837dcb2004-01-20 23:12:12 +0000450/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_EBC_PB2AP 0x92015480
452#define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
wdenk12f34242003-09-02 22:48:03 +0000453
wdenkc837dcb2004-01-20 23:12:12 +0000454/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_EBC_PB3AP 0x92015480
456#define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
wdenk12f34242003-09-02 22:48:03 +0000457
wdenke55ca7e2004-07-01 21:40:08 +0000458#ifdef CONFIG_PPCHAMELEON_SMI712
459/*
460 * Video console (graphic: SMI LynxEM)
461 */
462#define CONFIG_VIDEO
463#define CONFIG_CFB_CONSOLE
464#define CONFIG_VIDEO_SMI_LYNXEM
465#define CONFIG_VIDEO_LOGO
466/*#define CONFIG_VIDEO_BMP_LOGO*/
467#define CONFIG_CONSOLE_EXTRA_INFO
468#define CONFIG_VGA_AS_SINGLE_DEVICE
469/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_ISA_IO 0xE8000000
Marcel Ziswiler7817cb22007-12-30 03:30:46 +0100471/* see also drivers/video/videomodes.c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
wdenk12f34242003-09-02 22:48:03 +0000473#endif
474
475/*-----------------------------------------------------------------------
476 * FPGA stuff
477 */
478/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_FPGA_MODE 0x00
480#define CONFIG_SYS_FPGA_STATUS 0x02
481#define CONFIG_SYS_FPGA_TS 0x04
482#define CONFIG_SYS_FPGA_TS_LOW 0x06
483#define CONFIG_SYS_FPGA_TS_CAP0 0x10
484#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
485#define CONFIG_SYS_FPGA_TS_CAP1 0x14
486#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
487#define CONFIG_SYS_FPGA_TS_CAP2 0x18
488#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
489#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
490#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
wdenk12f34242003-09-02 22:48:03 +0000491
492/* FPGA Mode Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
494#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
495#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
496#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
wdenk12f34242003-09-02 22:48:03 +0000497
498/* FPGA Status Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
500#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
501#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
502#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
503#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
wdenk12f34242003-09-02 22:48:03 +0000504
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200505#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
506#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
wdenk12f34242003-09-02 22:48:03 +0000507
508/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200509#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
510#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
511#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
512#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
513#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
wdenk12f34242003-09-02 22:48:03 +0000514
515/*-----------------------------------------------------------------------
516 * Definitions for initial stack pointer and data area (in data cache)
517 */
wdenk12f34242003-09-02 22:48:03 +0000518/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200519#define CONFIG_SYS_TEMP_STACK_OCM 1
wdenk12f34242003-09-02 22:48:03 +0000520
521/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200522#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
523#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
524#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
525#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
wdenk12f34242003-09-02 22:48:03 +0000526
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
528#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
529#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk12f34242003-09-02 22:48:03 +0000530
531/*-----------------------------------------------------------------------
532 * Definitions for GPIO setup (PPC405EP specific)
533 *
wdenkc837dcb2004-01-20 23:12:12 +0000534 * GPIO0[0] - External Bus Controller BLAST output
535 * GPIO0[1-9] - Instruction trace outputs -> GPIO
wdenk12f34242003-09-02 22:48:03 +0000536 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
537 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
538 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
539 * GPIO0[24-27] - UART0 control signal inputs/outputs
540 * GPIO0[28-29] - UART1 data signal input/output
wdenkc837dcb2004-01-20 23:12:12 +0000541 * GPIO0[30] - EMAC0 input
542 * GPIO0[31] - EMAC1 reject packet as output
wdenk12f34242003-09-02 22:48:03 +0000543 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544#define CONFIG_SYS_GPIO0_OSRH 0x40000550
545#define CONFIG_SYS_GPIO0_OSRL 0x00000110
546#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
547/*#define CONFIG_SYS_GPIO0_ISR1L 0x15555445*/
548#define CONFIG_SYS_GPIO0_ISR1L 0x15555444
549#define CONFIG_SYS_GPIO0_TSRH 0x00000000
550#define CONFIG_SYS_GPIO0_TSRL 0x00000000
551#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
wdenk12f34242003-09-02 22:48:03 +0000552
553/*
554 * Internal Definitions
555 *
556 * Boot Flags
557 */
558#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
559#define BOOTFLAG_WARM 0x02 /* Software reboot */
560
wdenk180d3f72004-01-04 16:28:35 +0000561
wdenk12f34242003-09-02 22:48:03 +0000562#define CONFIG_NO_SERIAL_EEPROM
wdenk1d6f9722004-09-09 17:44:35 +0000563
wdenk200f8c72003-09-13 19:13:29 +0000564/*--------------------------------------------------------------------*/
wdenk1d6f9722004-09-09 17:44:35 +0000565
wdenk12f34242003-09-02 22:48:03 +0000566#ifdef CONFIG_NO_SERIAL_EEPROM
567
wdenk12f34242003-09-02 22:48:03 +0000568/*
wdenk200f8c72003-09-13 19:13:29 +0000569!-----------------------------------------------------------------------
wdenk12f34242003-09-02 22:48:03 +0000570! Defines for entry options.
571! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
wdenkc837dcb2004-01-20 23:12:12 +0000572! are plugged in the board will be utilized as non-ECC DIMMs.
wdenk200f8c72003-09-13 19:13:29 +0000573!-----------------------------------------------------------------------
wdenk12f34242003-09-02 22:48:03 +0000574*/
wdenk10767cc2004-05-13 13:23:58 +0000575#undef AUTO_MEMORY_CONFIG
576#define DIMM_READ_ADDR 0xAB
577#define DIMM_WRITE_ADDR 0xAA
wdenk12f34242003-09-02 22:48:03 +0000578
wdenk10767cc2004-05-13 13:23:58 +0000579#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
580#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
581#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
582#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */
583#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
584#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
585#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
586#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
587#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
588#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
wdenk12f34242003-09-02 22:48:03 +0000589
590/* Defines for CPC0_PLLMR1 Register fields */
wdenk10767cc2004-05-13 13:23:58 +0000591#define PLL_ACTIVE 0x80000000
592#define CPC0_PLLMR1_SSCS 0x80000000
593#define PLL_RESET 0x40000000
594#define CPC0_PLLMR1_PLLR 0x40000000
wdenk12f34242003-09-02 22:48:03 +0000595 /* Feedback multiplier */
wdenk10767cc2004-05-13 13:23:58 +0000596#define PLL_FBKDIV 0x00F00000
597#define CPC0_PLLMR1_FBDV 0x00F00000
598#define PLL_FBKDIV_16 0x00000000
599#define PLL_FBKDIV_1 0x00100000
600#define PLL_FBKDIV_2 0x00200000
601#define PLL_FBKDIV_3 0x00300000
602#define PLL_FBKDIV_4 0x00400000
603#define PLL_FBKDIV_5 0x00500000
604#define PLL_FBKDIV_6 0x00600000
605#define PLL_FBKDIV_7 0x00700000
606#define PLL_FBKDIV_8 0x00800000
607#define PLL_FBKDIV_9 0x00900000
608#define PLL_FBKDIV_10 0x00A00000
609#define PLL_FBKDIV_11 0x00B00000
610#define PLL_FBKDIV_12 0x00C00000
611#define PLL_FBKDIV_13 0x00D00000
612#define PLL_FBKDIV_14 0x00E00000
613#define PLL_FBKDIV_15 0x00F00000
wdenk12f34242003-09-02 22:48:03 +0000614 /* Forward A divisor */
wdenk10767cc2004-05-13 13:23:58 +0000615#define PLL_FWDDIVA 0x00070000
616#define CPC0_PLLMR1_FWDVA 0x00070000
617#define PLL_FWDDIVA_8 0x00000000
618#define PLL_FWDDIVA_7 0x00010000
619#define PLL_FWDDIVA_6 0x00020000
620#define PLL_FWDDIVA_5 0x00030000
621#define PLL_FWDDIVA_4 0x00040000
622#define PLL_FWDDIVA_3 0x00050000
623#define PLL_FWDDIVA_2 0x00060000
624#define PLL_FWDDIVA_1 0x00070000
wdenk12f34242003-09-02 22:48:03 +0000625 /* Forward B divisor */
wdenk10767cc2004-05-13 13:23:58 +0000626#define PLL_FWDDIVB 0x00007000
627#define CPC0_PLLMR1_FWDVB 0x00007000
628#define PLL_FWDDIVB_8 0x00000000
629#define PLL_FWDDIVB_7 0x00001000
630#define PLL_FWDDIVB_6 0x00002000
631#define PLL_FWDDIVB_5 0x00003000
632#define PLL_FWDDIVB_4 0x00004000
633#define PLL_FWDDIVB_3 0x00005000
634#define PLL_FWDDIVB_2 0x00006000
635#define PLL_FWDDIVB_1 0x00007000
wdenk12f34242003-09-02 22:48:03 +0000636 /* PLL tune bits */
wdenk10767cc2004-05-13 13:23:58 +0000637#define PLL_TUNE_MASK 0x000003FF
638#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
639#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
640#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
641#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
642#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
643#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
644#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
wdenk12f34242003-09-02 22:48:03 +0000645
646/* Defines for CPC0_PLLMR0 Register fields */
647 /* CPU divisor */
wdenk10767cc2004-05-13 13:23:58 +0000648#define PLL_CPUDIV 0x00300000
649#define CPC0_PLLMR0_CCDV 0x00300000
650#define PLL_CPUDIV_1 0x00000000
651#define PLL_CPUDIV_2 0x00100000
652#define PLL_CPUDIV_3 0x00200000
653#define PLL_CPUDIV_4 0x00300000
wdenk12f34242003-09-02 22:48:03 +0000654 /* PLB divisor */
wdenk10767cc2004-05-13 13:23:58 +0000655#define PLL_PLBDIV 0x00030000
656#define CPC0_PLLMR0_CBDV 0x00030000
657#define PLL_PLBDIV_1 0x00000000
658#define PLL_PLBDIV_2 0x00010000
659#define PLL_PLBDIV_3 0x00020000
660#define PLL_PLBDIV_4 0x00030000
wdenk12f34242003-09-02 22:48:03 +0000661 /* OPB divisor */
wdenk10767cc2004-05-13 13:23:58 +0000662#define PLL_OPBDIV 0x00003000
663#define CPC0_PLLMR0_OPDV 0x00003000
664#define PLL_OPBDIV_1 0x00000000
665#define PLL_OPBDIV_2 0x00001000
666#define PLL_OPBDIV_3 0x00002000
667#define PLL_OPBDIV_4 0x00003000
wdenk12f34242003-09-02 22:48:03 +0000668 /* EBC divisor */
wdenk10767cc2004-05-13 13:23:58 +0000669#define PLL_EXTBUSDIV 0x00000300
670#define CPC0_PLLMR0_EPDV 0x00000300
671#define PLL_EXTBUSDIV_2 0x00000000
672#define PLL_EXTBUSDIV_3 0x00000100
673#define PLL_EXTBUSDIV_4 0x00000200
674#define PLL_EXTBUSDIV_5 0x00000300
wdenk12f34242003-09-02 22:48:03 +0000675 /* MAL divisor */
wdenk10767cc2004-05-13 13:23:58 +0000676#define PLL_MALDIV 0x00000030
677#define CPC0_PLLMR0_MPDV 0x00000030
678#define PLL_MALDIV_1 0x00000000
679#define PLL_MALDIV_2 0x00000010
680#define PLL_MALDIV_3 0x00000020
681#define PLL_MALDIV_4 0x00000030
wdenk12f34242003-09-02 22:48:03 +0000682 /* PCI divisor */
wdenk10767cc2004-05-13 13:23:58 +0000683#define PLL_PCIDIV 0x00000003
684#define CPC0_PLLMR0_PPFD 0x00000003
685#define PLL_PCIDIV_1 0x00000000
686#define PLL_PCIDIV_2 0x00000001
687#define PLL_PCIDIV_3 0x00000002
688#define PLL_PCIDIV_4 0x00000003
wdenk12f34242003-09-02 22:48:03 +0000689
wdenke55ca7e2004-07-01 21:40:08 +0000690#ifdef CONFIG_PPCHAMELEON_CLK_25
691/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
692#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
693 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
694 PLL_MALDIV_1 | PLL_PCIDIV_4)
695#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
696 PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
697 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
698
699#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
700 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
701 PLL_MALDIV_1 | PLL_PCIDIV_4)
702#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
703 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
704 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
705
706#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
707 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
708 PLL_MALDIV_1 | PLL_PCIDIV_4)
709#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
710 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
711 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
712
713#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
714 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
715 PLL_MALDIV_1 | PLL_PCIDIV_2)
716#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
717 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
718 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
719
720#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
721
wdenk180d3f72004-01-04 16:28:35 +0000722/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
wdenke55ca7e2004-07-01 21:40:08 +0000723#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
wdenk10767cc2004-05-13 13:23:58 +0000724 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
725 PLL_MALDIV_1 | PLL_PCIDIV_4)
wdenke55ca7e2004-07-01 21:40:08 +0000726#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
wdenk10767cc2004-05-13 13:23:58 +0000727 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
728 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
wdenke55ca7e2004-07-01 21:40:08 +0000729
730#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk10767cc2004-05-13 13:23:58 +0000731 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
732 PLL_MALDIV_1 | PLL_PCIDIV_4)
wdenke55ca7e2004-07-01 21:40:08 +0000733#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
wdenk10767cc2004-05-13 13:23:58 +0000734 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
735 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
wdenke55ca7e2004-07-01 21:40:08 +0000736
737#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk10767cc2004-05-13 13:23:58 +0000738 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
739 PLL_MALDIV_1 | PLL_PCIDIV_4)
wdenke55ca7e2004-07-01 21:40:08 +0000740#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
wdenk10767cc2004-05-13 13:23:58 +0000741 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
742 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
wdenke55ca7e2004-07-01 21:40:08 +0000743
744#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
wdenk10767cc2004-05-13 13:23:58 +0000745 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
746 PLL_MALDIV_1 | PLL_PCIDIV_2)
wdenke55ca7e2004-07-01 21:40:08 +0000747#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
wdenk10767cc2004-05-13 13:23:58 +0000748 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
749 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
wdenk180d3f72004-01-04 16:28:35 +0000750
wdenke55ca7e2004-07-01 21:40:08 +0000751#else
752#error "* External frequency (SysClk) not defined! *"
753#endif
754
wdenk180d3f72004-01-04 16:28:35 +0000755#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
756/* Model HI */
wdenk1d6f9722004-09-09 17:44:35 +0000757#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
758#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200759#define CONFIG_SYS_OPB_FREQ 55555555
wdenk180d3f72004-01-04 16:28:35 +0000760/* Model ME */
761#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
wdenk1d6f9722004-09-09 17:44:35 +0000762#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
763#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200764#define CONFIG_SYS_OPB_FREQ 66666666
wdenk180d3f72004-01-04 16:28:35 +0000765#else
766/* Model BA (default) */
wdenk1d6f9722004-09-09 17:44:35 +0000767#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
768#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200769#define CONFIG_SYS_OPB_FREQ 66666666
wdenke55ca7e2004-07-01 21:40:08 +0000770#endif
wdenk12f34242003-09-02 22:48:03 +0000771
wdenk1d6f9722004-09-09 17:44:35 +0000772#endif /* CONFIG_NO_SERIAL_EEPROM */
wdenk180d3f72004-01-04 16:28:35 +0000773
wdenk1d6f9722004-09-09 17:44:35 +0000774#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
wdenk998eaae2004-04-18 19:43:36 +0000775#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
776
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200777/*
778 * JFFS2 partitions
779 */
780
781/* No command line, one static partition */
Stefan Roese68d7d652009-03-19 13:30:36 +0100782#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200783#define CONFIG_JFFS2_DEV "nand0"
784#define CONFIG_JFFS2_PART_SIZE 0x00400000
785#define CONFIG_JFFS2_PART_OFFSET 0x00000000
786
787/* mtdparts command line support */
788/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100789#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200790#define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
791*/
792
793/* 256 kB U-boot image */
794/*
795#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
796 "1792k(user),256k(u-boot);" \
797 "ppchameleonevb-nand:-(nand)"
798*/
799
800/* 320 kB U-boot image */
801/*
802#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
803 "1728k(user),320k(u-boot);" \
804 "ppchameleonevb-nand:-(nand)"
805*/
806
wdenk12f34242003-09-02 22:48:03 +0000807#endif /* __CONFIG_H */