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wdenk5b1d7132002-11-03 00:07:02 +00001/*
2 * (C) Copyright 2001-2002
3 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk5b1d7132002-11-03 00:07:02 +00006 */
7
8/************************************************************************/
9/* ** HEADER FILES */
10/************************************************************************/
11
wdenk8564acf2003-07-14 22:13:32 +000012/* #define DEBUG */
13
wdenk5b1d7132002-11-03 00:07:02 +000014#include <config.h>
15#include <common.h>
wdenkc3f4d172004-06-25 23:35:58 +000016#include <command.h>
wdenk7aa78612003-05-03 15:50:43 +000017#include <watchdog.h>
wdenk5b1d7132002-11-03 00:07:02 +000018#include <stdarg.h>
19#include <lcdvideo.h>
20#include <linux/types.h>
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +020021#include <stdio_dev.h>
wdenk4532cb62003-04-27 22:52:51 +000022#if defined(CONFIG_POST)
23#include <post.h>
24#endif
wdenk682011f2003-06-03 23:54:09 +000025#include <lcd.h>
wdenk5b1d7132002-11-03 00:07:02 +000026
27#ifdef CONFIG_LCD
28
29/************************************************************************/
30/* ** CONFIG STUFF -- should be moved to board config file */
31/************************************************************************/
wdenk88804d12005-07-04 00:03:16 +000032#ifndef CONFIG_LCD_INFO
33#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */
34#endif
wdenk608c9142003-01-13 23:54:46 +000035
wdenk5b1d7132002-11-03 00:07:02 +000036/*----------------------------------------------------------------------*/
37#ifdef CONFIG_KYOCERA_KCS057QV1AJ
38/*
39 * Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
40 */
41#define LCD_BPP LCD_COLOR4
42
wdenk8655b6f2004-10-09 23:25:58 +000043vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +000045 LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0
46 /* wbl, vpw, lcdac, wbf */
47};
48#endif /* CONFIG_KYOCERA_KCS057QV1AJ */
49/*----------------------------------------------------------------------*/
50
51/*----------------------------------------------------------------------*/
wdenk682011f2003-06-03 23:54:09 +000052#ifdef CONFIG_HITACHI_SP19X001_Z1A
53/*
54 * Hitachi SP19X001-. Active, color, single scan.
55 */
wdenk8655b6f2004-10-09 23:25:58 +000056vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057 640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
wdenk682011f2003-06-03 23:54:09 +000058 LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
59 /* wbl, vpw, lcdac, wbf */
60};
61#endif /* CONFIG_HITACHI_SP19X001_Z1A */
62/*----------------------------------------------------------------------*/
63
64/*----------------------------------------------------------------------*/
wdenkfd3103b2003-11-25 16:55:19 +000065#ifdef CONFIG_NEC_NL6448AC33
wdenk5b1d7132002-11-03 00:07:02 +000066/*
wdenkfd3103b2003-11-25 16:55:19 +000067 * NEC NL6448AC33-18. Active, color, single scan.
wdenk5b1d7132002-11-03 00:07:02 +000068 */
wdenk8655b6f2004-10-09 23:25:58 +000069vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +000071 3, 0, 0, 1, 1, 144, 2, 0, 33
72 /* wbl, vpw, lcdac, wbf */
73};
wdenkfd3103b2003-11-25 16:55:19 +000074#endif /* CONFIG_NEC_NL6448AC33 */
wdenk5b1d7132002-11-03 00:07:02 +000075/*----------------------------------------------------------------------*/
76
wdenkfd3103b2003-11-25 16:55:19 +000077#ifdef CONFIG_NEC_NL6448BC20
wdenk5b1d7132002-11-03 00:07:02 +000078/*
wdenkfd3103b2003-11-25 16:55:19 +000079 * NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan.
wdenk5b1d7132002-11-03 00:07:02 +000080 */
wdenk8655b6f2004-10-09 23:25:58 +000081vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +000083 3, 0, 0, 1, 1, 144, 2, 0, 33
84 /* wbl, vpw, lcdac, wbf */
85};
wdenkfd3103b2003-11-25 16:55:19 +000086#endif /* CONFIG_NEC_NL6448BC20 */
87/*----------------------------------------------------------------------*/
88
89#ifdef CONFIG_NEC_NL6448BC33_54
90/*
91 * NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
92 */
wdenk8655b6f2004-10-09 23:25:58 +000093vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094 640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
wdenkfd3103b2003-11-25 16:55:19 +000095 3, 0, 0, 1, 1, 144, 2, 0, 33
96 /* wbl, vpw, lcdac, wbf */
97};
98#endif /* CONFIG_NEC_NL6448BC33_54 */
wdenk5b1d7132002-11-03 00:07:02 +000099/*----------------------------------------------------------------------*/
100
101#ifdef CONFIG_SHARP_LQ104V7DS01
102/*
103 * SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
104 */
wdenk8655b6f2004-10-09 23:25:58 +0000105vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
wdenk5b1d7132002-11-03 00:07:02 +0000107 3, 0, 0, 1, 1, 25, 1, 0, 33
108 /* wbl, vpw, lcdac, wbf */
109};
110#endif /* CONFIG_SHARP_LQ104V7DS01 */
111/*----------------------------------------------------------------------*/
112
113#ifdef CONFIG_SHARP_16x9
114/*
115 * Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am
116 * not sure what it is.......
117 */
wdenk8655b6f2004-10-09 23:25:58 +0000118vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +0000120 3, 0, 0, 1, 1, 15, 4, 0, 3
121};
122#endif /* CONFIG_SHARP_16x9 */
123/*----------------------------------------------------------------------*/
124
125#ifdef CONFIG_SHARP_LQ057Q3DC02
126/*
127 * Sharp LQ057Q3DC02 display. Active, color, single scan.
128 */
wdenk8655b6f2004-10-09 23:25:58 +0000129#undef LCD_DF
wdenk4a6fd342003-04-12 23:38:12 +0000130#define LCD_DF 12
131
wdenk8655b6f2004-10-09 23:25:58 +0000132vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +0000134 3, 0, 0, 1, 1, 15, 4, 0, 3
135 /* wbl, vpw, lcdac, wbf */
136};
wdenk88804d12005-07-04 00:03:16 +0000137#define CONFIG_LCD_INFO_BELOW_LOGO
wdenk5b1d7132002-11-03 00:07:02 +0000138#endif /* CONFIG_SHARP_LQ057Q3DC02 */
139/*----------------------------------------------------------------------*/
140
141#ifdef CONFIG_SHARP_LQ64D341
142/*
143 * Sharp LQ64D341 display, 640x480. Active, color, single scan.
144 */
wdenk8655b6f2004-10-09 23:25:58 +0000145vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +0000147 3, 0, 0, 1, 1, 128, 16, 0, 32
148 /* wbl, vpw, lcdac, wbf */
149};
150#endif /* CONFIG_SHARP_LQ64D341 */
wdenk608c9142003-01-13 23:54:46 +0000151
dzu29127b62003-09-25 22:30:12 +0000152#ifdef CONFIG_SHARP_LQ065T9DR51U
153/*
154 * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
155 */
wdenk8655b6f2004-10-09 23:25:58 +0000156vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157 400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
dzu29127b62003-09-25 22:30:12 +0000158 3, 0, 0, 1, 1, 248, 4, 0, 35
159 /* wbl, vpw, lcdac, wbf */
160};
wdenk88804d12005-07-04 00:03:16 +0000161#define CONFIG_LCD_INFO_BELOW_LOGO
dzu29127b62003-09-25 22:30:12 +0000162#endif /* CONFIG_SHARP_LQ065T9DR51U */
163
wdenk608c9142003-01-13 23:54:46 +0000164#ifdef CONFIG_SHARP_LQ084V1DG21
165/*
166 * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
167 */
wdenk8655b6f2004-10-09 23:25:58 +0000168vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169 640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
wdenk608c9142003-01-13 23:54:46 +0000170 3, 0, 0, 1, 1, 160, 3, 0, 48
171 /* wbl, vpw, lcdac, wbf */
172};
173#endif /* CONFIG_SHARP_LQ084V1DG21 */
174
wdenk5b1d7132002-11-03 00:07:02 +0000175/*----------------------------------------------------------------------*/
176
177#ifdef CONFIG_HLD1045
178/*
179 * HLD1045 display, 640x480. Active, color, single scan.
180 */
wdenk8655b6f2004-10-09 23:25:58 +0000181vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +0000183 3, 0, 0, 1, 1, 160, 3, 0, 48
184 /* wbl, vpw, lcdac, wbf */
185};
186#endif /* CONFIG_HLD1045 */
187/*----------------------------------------------------------------------*/
188
189#ifdef CONFIG_PRIMEVIEW_V16C6448AC
190/*
191 * Prime View V16C6448AC
192 */
wdenk8655b6f2004-10-09 23:25:58 +0000193vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194 640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +0000195 3, 0, 0, 1, 1, 144, 2, 0, 35
196 /* wbl, vpw, lcdac, wbf */
197};
198#endif /* CONFIG_PRIMEVIEW_V16C6448AC */
199
200/*----------------------------------------------------------------------*/
201
202#ifdef CONFIG_OPTREX_BW
203/*
204 * Optrex CBL50840-2 NF-FW 99 22 M5
205 * or
206 * Hitachi LMG6912RPFC-00T
207 * or
208 * Hitachi SP14Q002
209 *
210 * 320x240. Black & white.
211 */
212#define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */
213 /* 1 - 4 grey levels, 2 bpp */
214 /* 2 - 16 grey levels, 4 bpp */
wdenk8655b6f2004-10-09 23:25:58 +0000215vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
wdenk5b1d7132002-11-03 00:07:02 +0000217 OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
218};
219#endif /* CONFIG_OPTREX_BW */
220
wdenk5b1d7132002-11-03 00:07:02 +0000221/************************************************************************/
222/* ----------------- chipset specific functions ----------------------- */
223/************************************************************************/
224
wdenk8655b6f2004-10-09 23:25:58 +0000225/*
226 * Calculate fb size for VIDEOLFB_ATAG.
227 */
228ulong calc_fbsize (void)
229{
230 ulong size;
231 int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
232
233 size = line_length * panel_info.vl_row;
234
235 return size;
236}
237
238void lcd_ctrl_init (void *lcdbase)
wdenk5b1d7132002-11-03 00:07:02 +0000239{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk5b1d7132002-11-03 00:07:02 +0000241 volatile lcd823_t *lcdp = &immr->im_lcd;
242
243 uint lccrtmp;
wdenk682011f2003-06-03 23:54:09 +0000244 uint lchcr_hpc_tmp;
wdenk5b1d7132002-11-03 00:07:02 +0000245
246 /* Initialize the LCD control register according to the LCD
247 * parameters defined. We do everything here but enable
248 * the controller.
249 */
250
251 lccrtmp = LCDBIT (LCCR_BNUM_BIT,
252 (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));
253
254 lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) |
255 LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) |
256 LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) |
257 LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) |
258 LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) |
259 LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) |
260 LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) |
261 LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) |
262 LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) |
263 LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft);
264
265#if 0
266 lccrtmp |= ((SIU_LEVEL5 / 2) << 12);
267 lccrtmp |= LCCR_EIEN;
268#endif
269
270 lcdp->lcd_lccr = lccrtmp;
271 lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */
272
273 /* Initialize LCD controller bus priorities.
274 */
275 immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */
276
277 /* set SHFT/CLOCK division factor 4
278 * This needs to be set based upon display type and processor
279 * speed. The TFT displays run about 20 to 30 MHz.
280 * I was running 64 MHz processor speed.
281 * The value for this divider must be chosen so the result is
282 * an integer of the processor speed (i.e., divide by 3 with
283 * 64 MHz would be bad).
284 */
285 immr->im_clkrst.car_sccr &= ~0x1F;
286 immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */
287
wdenk5b1d7132002-11-03 00:07:02 +0000288 /* Enable LCD on port D.
289 */
290 immr->im_ioport.iop_pdpar |= 0x1FFF;
291 immr->im_ioport.iop_pddir |= 0x1FFF;
292
293 /* Enable LCD_A/B/C on port B.
294 */
295 immr->im_cpm.cp_pbpar |= 0x00005001;
296 immr->im_cpm.cp_pbdir |= 0x00005001;
wdenk5b1d7132002-11-03 00:07:02 +0000297
298 /* Load the physical address of the linear frame buffer
299 * into the LCD controller.
300 * BIG NOTE: This has to be modified to load A and B depending
301 * upon the split mode of the LCD.
302 */
Jeroen Hofstee00a0ca52013-01-22 10:44:12 +0000303 lcdp->lcd_lcfaa = (ulong)lcdbase;
304 lcdp->lcd_lcfba = (ulong)lcdbase;
wdenk5b1d7132002-11-03 00:07:02 +0000305
306 /* MORE HACKS...This must be updated according to 823 manual
307 * for different panels.
wdenk682011f2003-06-03 23:54:09 +0000308 * Udi Finkelstein - done - see below:
309 * Note: You better not try unsupported combinations such as
310 * 4-bit wide passive dual scan LCD at 4/8 Bit color.
wdenk5b1d7132002-11-03 00:07:02 +0000311 */
wdenk682011f2003-06-03 23:54:09 +0000312 lchcr_hpc_tmp =
wdenk8bde7f72003-06-27 21:31:46 +0000313 (panel_info.vl_col *
wdenk682011f2003-06-03 23:54:09 +0000314 (panel_info.vl_tft ? 8 :
315 (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
316 /* use << to mult by: single scan = 1, dual scan = 2 */
317 panel_info.vl_splt) *
318 (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */
319
wdenk5b1d7132002-11-03 00:07:02 +0000320 lcdp->lcd_lchcr = LCHCR_BO |
321 LCDBIT (LCHCR_AT_BIT, 4) |
wdenk682011f2003-06-03 23:54:09 +0000322 LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) |
wdenk5b1d7132002-11-03 00:07:02 +0000323 panel_info.vl_wbl;
wdenk5b1d7132002-11-03 00:07:02 +0000324
325 lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) |
326 LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) |
327 LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) |
328 panel_info.vl_wbf;
329
330}
331
332/*----------------------------------------------------------------------*/
333
wdenk5b1d7132002-11-03 00:07:02 +0000334#if LCD_BPP == LCD_COLOR8
wdenk8655b6f2004-10-09 23:25:58 +0000335void
wdenk5b1d7132002-11-03 00:07:02 +0000336lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
337{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk5b1d7132002-11-03 00:07:02 +0000339 volatile cpm8xx_t *cp = &(immr->im_cpm);
340 unsigned short colreg, *cmap_ptr;
341
342 cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
343
344 colreg = ((red & 0x0F) << 8) |
345 ((green & 0x0F) << 4) |
346 (blue & 0x0F) ;
Nikita Kiryanovdc6b5b32014-12-08 17:14:35 +0200347
wdenk5b1d7132002-11-03 00:07:02 +0000348 *cmap_ptr = colreg;
349
350 debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
351 regno, &(cp->lcd_cmap[regno * 2]),
352 red, green, blue,
wdenk8bde7f72003-06-27 21:31:46 +0000353 cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
wdenk5b1d7132002-11-03 00:07:02 +0000354}
355#endif /* LCD_COLOR8 */
356
357/*----------------------------------------------------------------------*/
358
Nikita Kiryanov38b55082015-02-03 13:32:21 +0200359ushort *configuration_get_cmap(void)
360{
361 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
362 cpm8xx_t *cp = &(immr->im_cpm);
363 return (ushort *)&(cp->lcd_cmap[255 * sizeof(ushort)]);
364}
365
Nikita Kiryanov27fad012015-02-03 13:32:23 +0200366#if defined(CONFIG_MPC823)
367void fb_put_byte(uchar **fb, uchar **from)
368{
369 *(*fb)++ = (255 - *(*from)++);
370}
371#endif
372
Nikita Kiryanov0ee261f2015-02-03 13:32:25 +0200373#ifdef CONFIG_LCD_LOGO
374#include <bmp_logo.h>
375void lcd_logo_set_cmap(void)
376{
377 int i;
378 ushort *cmap;
379 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
380 cpm8xx_t *cp = &(immr->im_cpm);
381 cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET * sizeof(ushort)]);
382
383 for (i = 0; i < BMP_LOGO_COLORS; ++i)
384 *cmap++ = bmp_logo_palette[i];
385}
386#endif
387
wdenk8655b6f2004-10-09 23:25:58 +0000388void lcd_enable (void)
wdenk5b1d7132002-11-03 00:07:02 +0000389{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk5b1d7132002-11-03 00:07:02 +0000391 volatile lcd823_t *lcdp = &immr->im_lcd;
392
393 /* Enable the LCD panel */
394 immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */
395 lcdp->lcd_lccr |= LCCR_PON;
wdenk5b1d7132002-11-03 00:07:02 +0000396}
397
wdenk5b1d7132002-11-03 00:07:02 +0000398/************************************************************************/
wdenk5b1d7132002-11-03 00:07:02 +0000399
400#endif /* CONFIG_LCD */