blob: 8329f4a352f04d2d44e2a3ce3f8872941ad72c68 [file] [log] [blame]
Kever Yangc43acfd2018-12-20 11:33:42 +08001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Kever Yang39648e62017-06-23 16:11:07 +08002/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
Kever Yang39648e62017-06-23 16:11:07 +08004 */
Kever Yang39648e62017-06-23 16:11:07 +08005#include <common.h>
Kever Yang85a38742019-08-02 10:39:59 +03006#include <clk.h>
7#include <debug_uart.h>
Kever Yang39648e62017-06-23 16:11:07 +08008#include <dm.h>
Kever Yang85a38742019-08-02 10:39:59 +03009#include <dt-structs.h>
Kever Yang39648e62017-06-23 16:11:07 +080010#include <ram.h>
Kever Yang85a38742019-08-02 10:39:59 +030011#include <regmap.h>
Kever Yang39648e62017-06-23 16:11:07 +080012#include <syscon.h>
Kever Yang85a38742019-08-02 10:39:59 +030013#include <asm/io.h>
Kever Yang15f09a12019-03-28 11:01:23 +080014#include <asm/arch-rockchip/clock.h>
Kever Yang85a38742019-08-02 10:39:59 +030015#include <asm/arch-rockchip/cru_rk3328.h>
Kever Yang15f09a12019-03-28 11:01:23 +080016#include <asm/arch-rockchip/grf_rk3328.h>
Kever Yang5d19ddf2019-11-15 11:04:33 +080017#include <asm/arch-rockchip/sdram.h>
Kever Yang85a38742019-08-02 10:39:59 +030018#include <asm/arch-rockchip/sdram_rk3328.h>
19#include <asm/arch-rockchip/uart.h>
Kever Yang39648e62017-06-23 16:11:07 +080020
Kever Yang39648e62017-06-23 16:11:07 +080021struct dram_info {
Kever Yang85a38742019-08-02 10:39:59 +030022#ifdef CONFIG_TPL_BUILD
YouMin Chenca93e322019-11-15 11:04:44 +080023 struct ddr_pctl_regs *pctl;
24 struct ddr_phy_regs *phy;
Kever Yang85a38742019-08-02 10:39:59 +030025 struct clk ddr_clk;
26 struct rk3328_cru *cru;
YouMin Chenca93e322019-11-15 11:04:44 +080027 struct msch_regs *msch;
Kever Yang85a38742019-08-02 10:39:59 +030028 struct rk3328_ddr_grf_regs *ddr_grf;
29#endif
Kever Yang39648e62017-06-23 16:11:07 +080030 struct ram_info info;
31 struct rk3328_grf_regs *grf;
32};
33
Kever Yang85a38742019-08-02 10:39:59 +030034#ifdef CONFIG_TPL_BUILD
35
36struct rk3328_sdram_channel sdram_ch;
37
38struct rockchip_dmc_plat {
39#if CONFIG_IS_ENABLED(OF_PLATDATA)
40 struct dtd_rockchip_rk3328_dmc dtplat;
41#else
42 struct rk3328_sdram_params sdram_params;
43#endif
44 struct regmap *map;
45};
46
47#if CONFIG_IS_ENABLED(OF_PLATDATA)
48static int conv_of_platdata(struct udevice *dev)
49{
50 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
51 struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
52 int ret;
53
54 ret = regmap_init_mem_platdata(dev, dtplat->reg,
55 ARRAY_SIZE(dtplat->reg) / 2,
56 &plat->map);
57 if (ret)
58 return ret;
59
60 return 0;
61}
62#endif
63
64static void rkclk_ddr_reset(struct dram_info *dram,
65 u32 ctl_srstn, u32 ctl_psrstn,
66 u32 phy_srstn, u32 phy_psrstn)
67{
68 writel(ddrctrl_srstn_req(ctl_srstn) | ddrctrl_psrstn_req(ctl_psrstn) |
69 ddrphy_srstn_req(phy_srstn) | ddrphy_psrstn_req(phy_psrstn),
70 &dram->cru->softrst_con[5]);
71 writel(ddrctrl_asrstn_req(ctl_srstn), &dram->cru->softrst_con[9]);
72}
73
YouMin Chenca93e322019-11-15 11:04:44 +080074static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz)
Kever Yang85a38742019-08-02 10:39:59 +030075{
76 unsigned int refdiv, postdiv1, postdiv2, fbdiv;
77 int delay = 1000;
YouMin Chenca93e322019-11-15 11:04:44 +080078 u32 mhz = hz / MHZ;
Kever Yang85a38742019-08-02 10:39:59 +030079
80 refdiv = 1;
81 if (mhz <= 300) {
82 postdiv1 = 4;
83 postdiv2 = 2;
84 } else if (mhz <= 400) {
85 postdiv1 = 6;
86 postdiv2 = 1;
87 } else if (mhz <= 600) {
88 postdiv1 = 4;
89 postdiv2 = 1;
90 } else if (mhz <= 800) {
91 postdiv1 = 3;
92 postdiv2 = 1;
93 } else if (mhz <= 1600) {
94 postdiv1 = 2;
95 postdiv2 = 1;
96 } else {
97 postdiv1 = 1;
98 postdiv2 = 1;
99 }
100 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24;
101
102 writel(((0x1 << 4) << 16) | (0 << 4), &dram->cru->mode_con);
103 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]);
104 writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv),
105 &dram->cru->dpll_con[1]);
106
107 while (delay > 0) {
108 udelay(1);
109 if (LOCK(readl(&dram->cru->dpll_con[1])))
110 break;
111 delay--;
112 }
113
114 writel(((0x1 << 4) << 16) | (1 << 4), &dram->cru->mode_con);
115}
116
117static void rkclk_configure_ddr(struct dram_info *dram,
118 struct rk3328_sdram_params *sdram_params)
119{
120 void __iomem *phy_base = dram->phy;
121
122 /* choose DPLL for ddr clk source */
123 clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7);
124
125 /* for inno ddr phy need 2*freq */
YouMin Chenca93e322019-11-15 11:04:44 +0800126 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ * 2);
Kever Yang85a38742019-08-02 10:39:59 +0300127}
128
129/* return ddrconfig value
130 * (-1), find ddrconfig fail
131 * other, the ddrconfig value
132 * only support cs0_row >= cs1_row
133 */
YouMin Chenca93e322019-11-15 11:04:44 +0800134static u32 calculate_ddrconfig(struct rk3328_sdram_params *sdram_params)
Kever Yang85a38742019-08-02 10:39:59 +0300135{
YouMin Chenca93e322019-11-15 11:04:44 +0800136 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
Kever Yang85a38742019-08-02 10:39:59 +0300137 u32 cs, bw, die_bw, col, row, bank;
YouMin Chenca93e322019-11-15 11:04:44 +0800138 u32 cs1_row;
Kever Yang85a38742019-08-02 10:39:59 +0300139 u32 i, tmp;
140 u32 ddrconf = -1;
141
YouMin Chenca93e322019-11-15 11:04:44 +0800142 cs = cap_info->rank;
143 bw = cap_info->bw;
144 die_bw = cap_info->dbw;
145 col = cap_info->col;
146 row = cap_info->cs0_row;
147 cs1_row = cap_info->cs1_row;
148 bank = cap_info->bk;
Kever Yang85a38742019-08-02 10:39:59 +0300149
YouMin Chenca93e322019-11-15 11:04:44 +0800150 if (sdram_params->base.dramtype == DDR4) {
151 /* when DDR_TEST, CS always at MSB position for easy test */
152 if (cs == 2 && row == cs1_row) {
153 /* include 2cs cap both 2^n or both (2^n - 2^(n-2)) */
154 tmp = ((row - 13) << 3) | (1 << 2) | (bw & 0x2) |
155 die_bw;
156 for (i = 17; i < 21; i++) {
157 if (((tmp & 0x7) ==
158 (ddr4_cfg_2_rbc[i - 10] & 0x7)) &&
159 ((tmp & 0x3c) <=
160 (ddr4_cfg_2_rbc[i - 10] & 0x3c))) {
161 ddrconf = i;
162 goto out;
163 }
164 }
165 }
166
Kever Yang85a38742019-08-02 10:39:59 +0300167 tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw;
168 for (i = 10; i < 17; i++) {
169 if (((tmp & 0x7) == (ddr4_cfg_2_rbc[i - 10] & 0x7)) &&
170 ((tmp & 0x3c) <= (ddr4_cfg_2_rbc[i - 10] & 0x3c)) &&
171 ((tmp & 0x40) <= (ddr4_cfg_2_rbc[i - 10] & 0x40))) {
172 ddrconf = i;
173 goto out;
174 }
175 }
176 } else {
177 if (bank == 2) {
178 ddrconf = 8;
179 goto out;
180 }
181
YouMin Chenca93e322019-11-15 11:04:44 +0800182 /* when DDR_TEST, CS always at MSB position for easy test */
183 if (cs == 2 && row == cs1_row) {
184 /* include 2cs cap both 2^n or both (2^n - 2^(n-2)) */
185 for (i = 5; i < 8; i++) {
186 if ((bw + col - 11) == (ddr_cfg_2_rbc[i] &
187 0x3)) {
188 ddrconf = i;
189 goto out;
190 }
191 }
192 }
193
Kever Yang85a38742019-08-02 10:39:59 +0300194 tmp = ((row - 13) << 4) | (1 << 2) | ((bw + col - 11) << 0);
195 for (i = 0; i < 5; i++)
196 if (((tmp & 0xf) == (ddr_cfg_2_rbc[i] & 0xf)) &&
197 ((tmp & 0x30) <= (ddr_cfg_2_rbc[i] & 0x30))) {
198 ddrconf = i;
199 goto out;
200 }
201 }
202
203out:
204 if (ddrconf > 20)
YouMin Chenca93e322019-11-15 11:04:44 +0800205 printf("calculate ddrconfig error\n");
Kever Yang85a38742019-08-02 10:39:59 +0300206
207 return ddrconf;
208}
209
Kever Yang85a38742019-08-02 10:39:59 +0300210/*******
211 * calculate controller dram address map, and setting to register.
212 * argument sdram_ch.ddrconf must be right value before
213 * call this function.
214 *******/
215static void set_ctl_address_map(struct dram_info *dram,
216 struct rk3328_sdram_params *sdram_params)
217{
YouMin Chenca93e322019-11-15 11:04:44 +0800218 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
Kever Yang85a38742019-08-02 10:39:59 +0300219 void __iomem *pctl_base = dram->pctl;
220
YouMin Chenca93e322019-11-15 11:04:44 +0800221 sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0),
222 &addrmap[cap_info->ddrconfig][0], 9 * 4);
223 if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4)
Kever Yang85a38742019-08-02 10:39:59 +0300224 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31);
YouMin Chenca93e322019-11-15 11:04:44 +0800225 if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1)
Kever Yang85a38742019-08-02 10:39:59 +0300226 setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8);
227
YouMin Chenca93e322019-11-15 11:04:44 +0800228 if (cap_info->rank == 1)
Kever Yang85a38742019-08-02 10:39:59 +0300229 clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f);
230}
231
Kever Yang85a38742019-08-02 10:39:59 +0300232static int data_training(struct dram_info *dram, u32 cs, u32 dramtype)
233{
Kever Yang85a38742019-08-02 10:39:59 +0300234 void __iomem *pctl_base = dram->pctl;
YouMin Chenca93e322019-11-15 11:04:44 +0800235 u32 dis_auto_zq = 0;
236 u32 pwrctl;
237 u32 ret;
Kever Yang85a38742019-08-02 10:39:59 +0300238
YouMin Chenca93e322019-11-15 11:04:44 +0800239 /* disable auto low-power */
240 pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL);
241 writel(0, pctl_base + DDR_PCTL2_PWRCTL);
Kever Yang85a38742019-08-02 10:39:59 +0300242
YouMin Chenca93e322019-11-15 11:04:44 +0800243 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl);
Kever Yang85a38742019-08-02 10:39:59 +0300244
YouMin Chenca93e322019-11-15 11:04:44 +0800245 ret = phy_data_training(dram->phy, cs, dramtype);
Kever Yang85a38742019-08-02 10:39:59 +0300246
YouMin Chenca93e322019-11-15 11:04:44 +0800247 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq);
248
249 /* restore auto low-power */
250 writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL);
251
Kever Yang85a38742019-08-02 10:39:59 +0300252 return ret;
253}
254
Kever Yang85a38742019-08-02 10:39:59 +0300255static void rx_deskew_switch_adjust(struct dram_info *dram)
256{
257 u32 i, deskew_val;
258 u32 gate_val = 0;
259 void __iomem *phy_base = dram->phy;
260
261 for (i = 0; i < 4; i++)
YouMin Chenca93e322019-11-15 11:04:44 +0800262 gate_val = MAX(readl(PHY_REG(phy_base, 0xfb + i)), gate_val);
Kever Yang85a38742019-08-02 10:39:59 +0300263
264 deskew_val = (gate_val >> 3) + 1;
265 deskew_val = (deskew_val > 0x1f) ? 0x1f : deskew_val;
266 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2);
267 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4,
268 (deskew_val & 0x1c) << 2);
269}
270
Kever Yang85a38742019-08-02 10:39:59 +0300271static void tx_deskew_switch_adjust(struct dram_info *dram)
272{
273 void __iomem *phy_base = dram->phy;
274
275 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1);
276}
277
278static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig)
279{
280 writel(ddrconfig, &dram->msch->ddrconf);
281}
282
YouMin Chenca93e322019-11-15 11:04:44 +0800283static void sdram_msch_config(struct msch_regs *msch,
284 struct sdram_msch_timings *noc_timings)
285{
286 writel(noc_timings->ddrtiming.d32, &msch->ddrtiming);
287
288 writel(noc_timings->ddrmode.d32, &msch->ddrmode);
289 writel(noc_timings->readlatency, &msch->readlatency);
290
291 writel(noc_timings->activate.d32, &msch->activate);
292 writel(noc_timings->devtodev.d32, &msch->devtodev);
293 writel(noc_timings->ddr4timing.d32, &msch->ddr4_timing);
294 writel(noc_timings->agingx0, &msch->aging0);
295 writel(noc_timings->agingx0, &msch->aging1);
296 writel(noc_timings->agingx0, &msch->aging2);
297 writel(noc_timings->agingx0, &msch->aging3);
298 writel(noc_timings->agingx0, &msch->aging4);
299 writel(noc_timings->agingx0, &msch->aging5);
300}
301
Kever Yang85a38742019-08-02 10:39:59 +0300302static void dram_all_config(struct dram_info *dram,
303 struct rk3328_sdram_params *sdram_params)
304{
YouMin Chenca93e322019-11-15 11:04:44 +0800305 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
306 u32 sys_reg2 = 0;
307 u32 sys_reg3 = 0;
Kever Yang85a38742019-08-02 10:39:59 +0300308
YouMin Chenca93e322019-11-15 11:04:44 +0800309 set_ddrconfig(dram, cap_info->ddrconfig);
310 sdram_org_config(cap_info, &sdram_params->base, &sys_reg2,
311 &sys_reg3, 0);
312 writel(sys_reg2, &dram->grf->os_reg[2]);
313 writel(sys_reg3, &dram->grf->os_reg[3]);
Kever Yang85a38742019-08-02 10:39:59 +0300314
YouMin Chenca93e322019-11-15 11:04:44 +0800315 sdram_msch_config(dram->msch, &sdram_ch.noc_timings);
Kever Yang85a38742019-08-02 10:39:59 +0300316}
317
318static void enable_low_power(struct dram_info *dram,
319 struct rk3328_sdram_params *sdram_params)
320{
321 void __iomem *pctl_base = dram->pctl;
322
323 /* enable upctl2 axi clock auto gating */
324 writel(0x00800000, &dram->ddr_grf->ddr_grf_con[0]);
325 writel(0x20012001, &dram->ddr_grf->ddr_grf_con[2]);
326 /* enable upctl2 core clock auto gating */
327 writel(0x001e001a, &dram->ddr_grf->ddr_grf_con[2]);
328 /* enable sr, pd */
329 if (PD_IDLE == 0)
330 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
331 else
332 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
333 if (SR_IDLE == 0)
334 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
335 else
336 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
337 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3));
338}
339
340static int sdram_init(struct dram_info *dram,
341 struct rk3328_sdram_params *sdram_params, u32 pre_init)
342{
YouMin Chenca93e322019-11-15 11:04:44 +0800343 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
Kever Yang85a38742019-08-02 10:39:59 +0300344 void __iomem *pctl_base = dram->pctl;
345
346 rkclk_ddr_reset(dram, 1, 1, 1, 1);
347 udelay(10);
348 /*
349 * dereset ddr phy psrstn to config pll,
350 * if using phy pll psrstn must be dereset
351 * before config pll
352 */
353 rkclk_ddr_reset(dram, 1, 1, 1, 0);
354 rkclk_configure_ddr(dram, sdram_params);
YouMin Chenca93e322019-11-15 11:04:44 +0800355
Kever Yang85a38742019-08-02 10:39:59 +0300356 /* release phy srst to provide clk to ctrl */
357 rkclk_ddr_reset(dram, 1, 1, 0, 0);
358 udelay(10);
YouMin Chenca93e322019-11-15 11:04:44 +0800359 phy_soft_reset(dram->phy);
Kever Yang85a38742019-08-02 10:39:59 +0300360 /* release ctrl presetn, and config ctl registers */
361 rkclk_ddr_reset(dram, 1, 0, 0, 0);
YouMin Chenca93e322019-11-15 11:04:44 +0800362 pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE);
363 cap_info->ddrconfig = calculate_ddrconfig(sdram_params);
Kever Yang85a38742019-08-02 10:39:59 +0300364 set_ctl_address_map(dram, sdram_params);
YouMin Chenca93e322019-11-15 11:04:44 +0800365 phy_cfg(dram->phy, &sdram_params->phy_regs, &sdram_params->skew,
366 &sdram_params->base, cap_info->bw);
Kever Yang85a38742019-08-02 10:39:59 +0300367
368 /* enable dfi_init_start to init phy after ctl srstn deassert */
369 setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4));
370 rkclk_ddr_reset(dram, 0, 0, 0, 0);
371 /* wait for dfi_init_done and dram init complete */
372 while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0)
373 continue;
374
375 /* do ddr gate training */
YouMin Chenca93e322019-11-15 11:04:44 +0800376 if (data_training(dram, 0, sdram_params->base.dramtype) != 0) {
377 printf("data training error\n");
378 return -1;
379 }
Kever Yang85a38742019-08-02 10:39:59 +0300380
YouMin Chenca93e322019-11-15 11:04:44 +0800381 if (sdram_params->base.dramtype == DDR4)
382 pctl_write_vrefdq(dram->pctl, 0x3, 5670,
383 sdram_params->base.dramtype);
Kever Yang85a38742019-08-02 10:39:59 +0300384
Kever Yang31531f62020-01-07 15:15:20 +0800385 if (pre_init != 0) {
Kever Yang85a38742019-08-02 10:39:59 +0300386 rx_deskew_switch_adjust(dram);
387 tx_deskew_switch_adjust(dram);
388 }
389
390 dram_all_config(dram, sdram_params);
391 enable_low_power(dram, sdram_params);
392
393 return 0;
394}
395
396static u64 dram_detect_cap(struct dram_info *dram,
397 struct rk3328_sdram_params *sdram_params,
398 unsigned char channel)
399{
YouMin Chenca93e322019-11-15 11:04:44 +0800400 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
Kever Yang85a38742019-08-02 10:39:59 +0300401
402 /*
403 * for ddr3: ddrconf = 3
404 * for ddr4: ddrconf = 12
405 * for lpddr3: ddrconf = 3
406 * default bw = 1
407 */
408 u32 bk, bktmp;
409 u32 col, coltmp;
YouMin Chenca93e322019-11-15 11:04:44 +0800410 u32 rowtmp;
Kever Yang85a38742019-08-02 10:39:59 +0300411 u32 cs;
412 u32 bw = 1;
YouMin Chenca93e322019-11-15 11:04:44 +0800413 u32 dram_type = sdram_params->base.dramtype;
Kever Yang85a38742019-08-02 10:39:59 +0300414
415 if (dram_type != DDR4) {
416 /* detect col and bk for ddr3/lpddr3 */
417 coltmp = 12;
418 bktmp = 3;
419 rowtmp = 16;
420
YouMin Chenca93e322019-11-15 11:04:44 +0800421 if (sdram_detect_col(cap_info, coltmp) != 0)
Kever Yang85a38742019-08-02 10:39:59 +0300422 goto cap_err;
YouMin Chenca93e322019-11-15 11:04:44 +0800423 sdram_detect_bank(cap_info, coltmp, bktmp);
424 sdram_detect_dbw(cap_info, dram_type);
Kever Yang85a38742019-08-02 10:39:59 +0300425 } else {
426 /* detect bg for ddr4 */
427 coltmp = 10;
428 bktmp = 4;
429 rowtmp = 17;
430
431 col = 10;
432 bk = 2;
YouMin Chenca93e322019-11-15 11:04:44 +0800433 cap_info->col = col;
434 cap_info->bk = bk;
435 sdram_detect_bg(cap_info, coltmp);
Kever Yang85a38742019-08-02 10:39:59 +0300436 }
YouMin Chenca93e322019-11-15 11:04:44 +0800437
Kever Yang85a38742019-08-02 10:39:59 +0300438 /* detect row */
YouMin Chenca93e322019-11-15 11:04:44 +0800439 if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0)
Kever Yang85a38742019-08-02 10:39:59 +0300440 goto cap_err;
YouMin Chenca93e322019-11-15 11:04:44 +0800441
Kever Yang85a38742019-08-02 10:39:59 +0300442 /* detect row_3_4 */
YouMin Chenca93e322019-11-15 11:04:44 +0800443 sdram_detect_row_3_4(cap_info, coltmp, bktmp);
Kever Yang85a38742019-08-02 10:39:59 +0300444
YouMin Chenca93e322019-11-15 11:04:44 +0800445 /* bw and cs detect using data training */
Kever Yang85a38742019-08-02 10:39:59 +0300446 if (data_training(dram, 1, dram_type) == 0)
447 cs = 1;
448 else
449 cs = 0;
YouMin Chenca93e322019-11-15 11:04:44 +0800450 cap_info->rank = cs + 1;
Kever Yang85a38742019-08-02 10:39:59 +0300451
452 bw = 2;
YouMin Chenca93e322019-11-15 11:04:44 +0800453 cap_info->bw = bw;
Kever Yang85a38742019-08-02 10:39:59 +0300454
YouMin Chenca93e322019-11-15 11:04:44 +0800455 cap_info->cs0_high16bit_row = cap_info->cs0_row;
456 if (cs) {
457 cap_info->cs1_row = cap_info->cs0_row;
458 cap_info->cs1_high16bit_row = cap_info->cs0_row;
459 } else {
460 cap_info->cs1_row = 0;
461 cap_info->cs1_high16bit_row = 0;
462 }
Kever Yang85a38742019-08-02 10:39:59 +0300463
YouMin Chenca93e322019-11-15 11:04:44 +0800464 return 0;
Kever Yang85a38742019-08-02 10:39:59 +0300465cap_err:
YouMin Chenca93e322019-11-15 11:04:44 +0800466 return -1;
Kever Yang85a38742019-08-02 10:39:59 +0300467}
468
469static int sdram_init_detect(struct dram_info *dram,
470 struct rk3328_sdram_params *sdram_params)
471{
YouMin Chenca93e322019-11-15 11:04:44 +0800472 u32 sys_reg = 0;
473 u32 sys_reg3 = 0;
474 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
475
Kever Yang85a38742019-08-02 10:39:59 +0300476 debug("Starting SDRAM initialization...\n");
477
478 memcpy(&sdram_ch, &sdram_params->ch,
479 sizeof(struct rk3328_sdram_channel));
480
Kever Yang31531f62020-01-07 15:15:20 +0800481 sdram_init(dram, sdram_params, 0);
Kever Yang85a38742019-08-02 10:39:59 +0300482 dram_detect_cap(dram, sdram_params, 0);
483
484 /* modify bw, cs related timing */
YouMin Chenca93e322019-11-15 11:04:44 +0800485 pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info,
486 sdram_params->base.dramtype);
487
488 if (cap_info->bw == 2)
489 sdram_ch.noc_timings.ddrtiming.b.bwratio = 0;
490 else
491 sdram_ch.noc_timings.ddrtiming.b.bwratio = 1;
492
Kever Yang85a38742019-08-02 10:39:59 +0300493 /* reinit sdram by real dram cap */
Kever Yang31531f62020-01-07 15:15:20 +0800494 sdram_init(dram, sdram_params, 1);
Kever Yang85a38742019-08-02 10:39:59 +0300495
496 /* redetect cs1 row */
YouMin Chenca93e322019-11-15 11:04:44 +0800497 sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype);
498 if (cap_info->cs1_row) {
499 sys_reg = readl(&dram->grf->os_reg[2]);
500 sys_reg3 = readl(&dram->grf->os_reg[3]);
501 SYS_REG_ENC_CS1_ROW(cap_info->cs1_row,
502 sys_reg, sys_reg3, 0);
503 writel(sys_reg, &dram->grf->os_reg[2]);
504 writel(sys_reg3, &dram->grf->os_reg[3]);
505 }
506
507 sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base);
Kever Yang85a38742019-08-02 10:39:59 +0300508
509 return 0;
510}
511
512static int rk3328_dmc_init(struct udevice *dev)
513{
514 struct dram_info *priv = dev_get_priv(dev);
515 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
516 int ret;
517
518#if !CONFIG_IS_ENABLED(OF_PLATDATA)
519 struct rk3328_sdram_params *params = &plat->sdram_params;
520#else
521 struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
522 struct rk3328_sdram_params *params =
523 (void *)dtplat->rockchip_sdram_params;
524
525 ret = conv_of_platdata(dev);
526 if (ret)
527 return ret;
528#endif
529 priv->phy = regmap_get_range(plat->map, 0);
530 priv->pctl = regmap_get_range(plat->map, 1);
531 priv->grf = regmap_get_range(plat->map, 2);
532 priv->cru = regmap_get_range(plat->map, 3);
533 priv->msch = regmap_get_range(plat->map, 4);
534 priv->ddr_grf = regmap_get_range(plat->map, 5);
535
536 debug("%s phy %p pctrl %p grf %p cru %p msch %p ddr_grf %p\n",
537 __func__, priv->phy, priv->pctl, priv->grf, priv->cru,
538 priv->msch, priv->ddr_grf);
539 ret = sdram_init_detect(priv, params);
540 if (ret < 0) {
541 printf("%s DRAM init failed%d\n", __func__, ret);
542 return ret;
543 }
544
545 return 0;
546}
547
548static int rk3328_dmc_ofdata_to_platdata(struct udevice *dev)
549{
550#if !CONFIG_IS_ENABLED(OF_PLATDATA)
551 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
552 int ret;
553
554 ret = dev_read_u32_array(dev, "rockchip,sdram-params",
555 (u32 *)&plat->sdram_params,
556 sizeof(plat->sdram_params) / sizeof(u32));
557 if (ret) {
558 printf("%s: Cannot read rockchip,sdram-params %d\n",
559 __func__, ret);
560 return ret;
561 }
562 ret = regmap_init_mem(dev, &plat->map);
563 if (ret)
564 printf("%s: regmap failed %d\n", __func__, ret);
565#endif
566 return 0;
567}
568
569#endif
570
Kever Yang39648e62017-06-23 16:11:07 +0800571static int rk3328_dmc_probe(struct udevice *dev)
572{
Kever Yang85a38742019-08-02 10:39:59 +0300573#ifdef CONFIG_TPL_BUILD
574 if (rk3328_dmc_init(dev))
575 return 0;
576#else
Kever Yang39648e62017-06-23 16:11:07 +0800577 struct dram_info *priv = dev_get_priv(dev);
578
579 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
580 debug("%s: grf=%p\n", __func__, priv->grf);
581 priv->info.base = CONFIG_SYS_SDRAM_BASE;
582 priv->info.size = rockchip_sdram_size(
583 (phys_addr_t)&priv->grf->os_reg[2]);
Kever Yang85a38742019-08-02 10:39:59 +0300584#endif
Kever Yang39648e62017-06-23 16:11:07 +0800585 return 0;
586}
587
588static int rk3328_dmc_get_info(struct udevice *dev, struct ram_info *info)
589{
590 struct dram_info *priv = dev_get_priv(dev);
591
592 *info = priv->info;
593
594 return 0;
595}
596
597static struct ram_ops rk3328_dmc_ops = {
598 .get_info = rk3328_dmc_get_info,
599};
600
Kever Yang39648e62017-06-23 16:11:07 +0800601static const struct udevice_id rk3328_dmc_ids[] = {
602 { .compatible = "rockchip,rk3328-dmc" },
603 { }
604};
605
606U_BOOT_DRIVER(dmc_rk3328) = {
607 .name = "rockchip_rk3328_dmc",
608 .id = UCLASS_RAM,
609 .of_match = rk3328_dmc_ids,
610 .ops = &rk3328_dmc_ops,
Kever Yang85a38742019-08-02 10:39:59 +0300611#ifdef CONFIG_TPL_BUILD
612 .ofdata_to_platdata = rk3328_dmc_ofdata_to_platdata,
613#endif
Kever Yang39648e62017-06-23 16:11:07 +0800614 .probe = rk3328_dmc_probe,
615 .priv_auto_alloc_size = sizeof(struct dram_info),
Kever Yang85a38742019-08-02 10:39:59 +0300616#ifdef CONFIG_TPL_BUILD
617 .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
618#endif
Kever Yang39648e62017-06-23 16:11:07 +0800619};