| Mark Jonas | 3313e0e | 2008-03-10 11:37:10 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| 3 | * Mark Jonas <mark.jonas@de.bosch.com> |
| 4 | * |
| 5 | * (C) Copyright 2007 |
| 6 | * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> |
| 7 | * |
| 8 | * board/mpr2/lowlevel_init.S |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | .global lowlevel_init |
| 27 | |
| 28 | .text |
| 29 | .align 2 |
| 30 | |
| 31 | lowlevel_init: |
| 32 | |
| 33 | /* |
| 34 | * Set frequency multipliers and dividers in FRQCR. |
| 35 | */ |
| 36 | mov.l WTCSR_A,r1 |
| 37 | mov.l WTCSR_D,r0 |
| 38 | mov.w r0,@r1 |
| 39 | |
| 40 | mov.l WTCNT_A,r1 |
| 41 | mov.l WTCNT_D,r0 |
| 42 | mov.w r0,@r1 |
| 43 | |
| 44 | mov.l FRQCR_A,r1 |
| 45 | mov.l FRQCR_D,r0 |
| 46 | mov.w r0,@r1 |
| 47 | |
| 48 | /* |
| 49 | * Setup CS0 (Flash). |
| 50 | */ |
| 51 | mov.l CS0BCR_A, r1 |
| 52 | mov.l CS0BCR_D, r0 |
| 53 | mov.l r0, @r1 |
| 54 | |
| 55 | mov.l CS0WCR_A, r1 |
| 56 | mov.l CS0WCR_D, r0 |
| 57 | mov.l r0, @r1 |
| 58 | |
| 59 | /* |
| 60 | * Setup CS3 (SDRAM). |
| 61 | */ |
| 62 | mov.l CS3BCR_A, r1 |
| 63 | mov.l CS3BCR_D, r0 |
| 64 | mov.l r0, @r1 |
| 65 | |
| 66 | mov.l CS3WCR_A, r1 |
| 67 | mov.l CS3WCR_D, r0 |
| 68 | mov.l r0, @r1 |
| 69 | |
| 70 | mov.l SDCR_A, r1 |
| 71 | mov.l SDCR_D1, r0 |
| 72 | mov.l r0, @r1 |
| 73 | |
| 74 | mov.l RTCSR_A, r1 |
| 75 | mov.l RTCSR_D, r0 |
| 76 | mov.l r0, @r1 |
| 77 | |
| 78 | mov.l RTCNT_A, r1 |
| 79 | mov.l RTCNT_D, r0 |
| 80 | mov.l r0, @r1 |
| 81 | |
| 82 | mov.l RTCOR_A, r1 |
| 83 | mov.l RTCOR_D, r0 |
| 84 | mov.l r0, @r1 |
| 85 | |
| 86 | mov.l SDCR_A, r1 |
| 87 | mov.l SDCR_D2, r0 |
| 88 | mov.l r0, @r1 |
| 89 | |
| 90 | mov.l SDMR3_A, r1 |
| 91 | mov.l SDMR3_D, r0 |
| 92 | add r0, r1 |
| 93 | mov #0, r0 |
| 94 | mov.w r0, @r1 |
| 95 | |
| 96 | rts |
| 97 | nop |
| 98 | |
| 99 | .align 4 |
| 100 | |
| 101 | /* |
| 102 | * Configuration for MPR2 A.3 through A.7 |
| 103 | */ |
| 104 | |
| 105 | /* |
| 106 | * PLL Settings |
| 107 | */ |
| 108 | FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */ |
| 109 | WTCNT_D: .long 0x5A00 /* start counting at zero */ |
| 110 | WTCSR_D: .long 0xA507 /* divide by 4096 */ |
| 111 | |
| 112 | /* |
| 113 | * Spansion S29GL256N11 @ 48 MHz |
| 114 | */ |
| 115 | CS0BCR_D: .long 0x12490400 /* 1 idle cycle inserted, normal space, 16 bit */ |
| 116 | CS0WCR_D: .long 0x00000340 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ |
| 117 | |
| 118 | /* |
| 119 | * Samsung K4S511632B-UL75 @ 48 MHz |
| 120 | * Micron MT48LC32M16A2-75 @ 48 MHz |
| 121 | */ |
| 122 | CS3BCR_D: .long 0x10004400 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ |
| 123 | CS3WCR_D: .long 0x00000091 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ |
| 124 | SDCR_D1: .long 0x00000012 /* no refresh, 13 rows, 10 cols, NO bank active mode */ |
| 125 | SDCR_D2: .long 0x00000812 /* refresh */ |
| 126 | RTCSR_D: .long 0xA55A0008 /* 1/4, once */ |
| 127 | RTCNT_D: .long 0xA55A005D /* count 93 */ |
| 128 | RTCOR_D: .long 0xa55a005d /* count 93 */ |
| 129 | SDMR3_D: .long 0x440 /* mode register CL2, burst read and SINGLE WRITE */ |
| 130 | |
| 131 | /* |
| 132 | * Registers |
| 133 | */ |
| 134 | |
| 135 | FRQCR_A: .long 0xA415FF80 |
| 136 | WTCNT_A: .long 0xA415FF84 |
| 137 | WTCSR_A: .long 0xA415FF86 |
| 138 | |
| 139 | #define BSC_BASE 0xA4FD0000 |
| 140 | CS0BCR_A: .long BSC_BASE + 0x04 |
| 141 | CS3BCR_A: .long BSC_BASE + 0x0C |
| 142 | CS0WCR_A: .long BSC_BASE + 0x24 |
| 143 | CS3WCR_A: .long BSC_BASE + 0x2C |
| 144 | SDCR_A: .long BSC_BASE + 0x44 |
| 145 | RTCSR_A: .long BSC_BASE + 0x48 |
| 146 | RTCNT_A: .long BSC_BASE + 0x4C |
| 147 | RTCOR_A: .long BSC_BASE + 0x50 |
| 148 | SDMR3_A: .long BSC_BASE + 0x5000 |