blob: 6973538a8c97b3c0c1b3afba9de50224a189f231 [file] [log] [blame]
Andy Fleming67431052007-04-23 02:54:25 -05001/*
2 * Copyright 2004-2007 Freescale Semiconductor.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8568mds board configuration file
25 */
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/* High Level Configuration Options */
30#define CONFIG_BOOKE 1 /* BOOKE */
Andy Flemingda9d4612007-08-14 00:14:25 -050031#define CONFIG_E500 1 /* BOOKE e500 family */
Andy Fleming67431052007-04-23 02:54:25 -050032#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
33#define CONFIG_MPC8568 1 /* MPC8568 specific */
34#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
35
Haiying Wang1563f562007-11-14 15:52:06 -050036#define CONFIG_PCI 1 /* Enable PCI/PCIE */
37#define CONFIG_PCI1 1 /* PCI controller */
38#define CONFIG_PCIE1 1 /* PCIE controller */
39#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
Kumar Gala8ff3de62007-12-07 12:17:34 -060040#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050041#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020042#define CONFIG_TSEC_ENET /* tsec ethernet support */
Andy Flemingb96c83d2007-08-15 20:03:34 -050043#define CONFIG_QE /* Enable QE */
Andy Fleming67431052007-04-23 02:54:25 -050044#define CONFIG_ENV_OVERWRITE
Kumar Gala4d3521c2008-01-16 09:15:29 -060045#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Andy Fleming67431052007-04-23 02:54:25 -050046
Andy Fleming67431052007-04-23 02:54:25 -050047#ifndef __ASSEMBLY__
48extern unsigned long get_clock_freq(void);
49#endif /*Replace a call to get_clock_freq (after it is implemented)*/
50#define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
51
52/*
53 * These can be toggled for performance analysis, otherwise use default.
54 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020055#define CONFIG_L2_CACHE /* toggle L2 cache */
Haiying Wang7a1ac412007-08-23 15:20:54 -040056#define CONFIG_BTB /* toggle branch predition */
Andy Fleming67431052007-04-23 02:54:25 -050057
58/*
59 * Only possible on E500 Version 2 or newer cores.
60 */
61#define CONFIG_ENABLE_36BIT_PHYS 1
62
63
64#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
65
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
67#define CONFIG_SYS_MEMTEST_END 0x00400000
Andy Fleming67431052007-04-23 02:54:25 -050068
69/*
70 * Base addresses -- Note these are effective addresses where the
71 * actual resources get mapped (not physical addresses)
72 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
74#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
75#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
76#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Andy Fleming67431052007-04-23 02:54:25 -050077
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
79#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
Haiying Wang1563f562007-11-14 15:52:06 -050080
Jon Loeligere6f5b352008-03-18 13:51:05 -050081/* DDR Setup */
82#define CONFIG_FSL_DDR2
83#undef CONFIG_FSL_DDR_INTERACTIVE
84#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
85#define CONFIG_DDR_SPD
86#define CONFIG_DDR_DLL /* possible DLL fix needed */
Dave Liu9b0ad1b2008-10-28 17:53:38 +080087#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Jon Loeligere6f5b352008-03-18 13:51:05 -050088
89#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
90
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
92#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Andy Fleming67431052007-04-23 02:54:25 -050093
Jon Loeligere6f5b352008-03-18 13:51:05 -050094#define CONFIG_NUM_DDR_CONTROLLERS 1
95#define CONFIG_DIMM_SLOTS_PER_CTLR 1
96#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Andy Fleming67431052007-04-23 02:54:25 -050097
Jon Loeligere6f5b352008-03-18 13:51:05 -050098/* I2C addresses of SPD EEPROMs */
99#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
100
101/* Make sure required options are set */
Andy Fleming67431052007-04-23 02:54:25 -0500102#ifndef CONFIG_SPD_EEPROM
103#error ("CONFIG_SPD_EEPROM is required")
104#endif
105
106#undef CONFIG_CLOCKS_IN_MHZ
107
Andy Fleming67431052007-04-23 02:54:25 -0500108/*
109 * Local Bus Definitions
110 */
111
112/*
113 * FLASH on the Local Bus
114 * Two banks, 8M each, using the CFI driver.
115 * Boot from BR0/OR0 bank at 0xff00_0000
116 * Alternate BR1/OR1 bank at 0xff80_0000
117 *
118 * BR0, BR1:
119 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
120 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
121 * Port Size = 16 bits = BRx[19:20] = 10
122 * Use GPCM = BRx[24:26] = 000
123 * Valid = BRx[31] = 1
124 *
125 * 0 4 8 12 16 20 24 28
126 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
127 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
128 *
129 * OR0, OR1:
130 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
131 * Reserved ORx[17:18] = 11, confusion here?
132 * CSNT = ORx[20] = 1
133 * ACS = half cycle delay = ORx[21:22] = 11
134 * SCY = 6 = ORx[24:27] = 0110
135 * TRLX = use relaxed timing = ORx[29] = 1
136 * EAD = use external address latch delay = OR[31] = 1
137 *
138 * 0 4 8 12 16 20 24 28
139 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
140 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_BCSR_BASE 0xf8000000
Andy Fleming67431052007-04-23 02:54:25 -0500142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
Andy Fleming67431052007-04-23 02:54:25 -0500144
145/*Chip select 0 - Flash*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_BR0_PRELIM 0xfe001001
147#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
Andy Fleming67431052007-04-23 02:54:25 -0500148
149/*Chip slelect 1 - BCSR*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_BR1_PRELIM 0xf8000801
151#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
Andy Fleming67431052007-04-23 02:54:25 -0500152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153/*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */
154#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
155#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
156#undef CONFIG_SYS_FLASH_CHECKSUM
157#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
158#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Andy Fleming67431052007-04-23 02:54:25 -0500159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Andy Fleming67431052007-04-23 02:54:25 -0500161
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200162#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_FLASH_CFI
164#define CONFIG_SYS_FLASH_EMPTY_INFO
Andy Fleming67431052007-04-23 02:54:25 -0500165
166
167/*
168 * SDRAM on the LocalBus
169 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
171#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Andy Fleming67431052007-04-23 02:54:25 -0500172
173
174/*Chip select 2 - SDRAM*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_BR2_PRELIM 0xf0001861
176#define CONFIG_SYS_OR2_PRELIM 0xfc006901
Andy Fleming67431052007-04-23 02:54:25 -0500177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
179#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
180#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
181#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Andy Fleming67431052007-04-23 02:54:25 -0500182
183/*
Andy Fleming67431052007-04-23 02:54:25 -0500184 * Common settings for all Local Bus SDRAM commands.
185 * At run time, either BSMA1516 (for CPU 1.1)
186 * or BSMA1617 (for CPU 1.0) (old)
187 * is OR'ed in too.
188 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500189#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
190 | LSDMR_PRETOACT7 \
191 | LSDMR_ACTTORW7 \
192 | LSDMR_BL8 \
193 | LSDMR_WRC4 \
194 | LSDMR_CL3 \
195 | LSDMR_RFEN \
Andy Fleming67431052007-04-23 02:54:25 -0500196 )
197
198/*
199 * The bcsr registers are connected to CS3 on MDS.
200 * The new memory map places bcsr at 0xf8000000.
201 *
202 * For BR3, need:
203 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
204 * port-size = 8-bits = BR[19:20] = 01
205 * no parity checking = BR[21:22] = 00
206 * GPMC for MSEL = BR[24:26] = 000
207 * Valid = BR[31] = 1
208 *
209 * 0 4 8 12 16 20 24 28
210 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
211 *
212 * For OR3, need:
213 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
214 * disable buffer ctrl OR[19] = 0
215 * CSNT OR[20] = 1
216 * ACS OR[21:22] = 11
217 * XACS OR[23] = 1
218 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
219 * SETA OR[28] = 0
220 * TRLX OR[29] = 1
221 * EHTR OR[30] = 1
222 * EAD extra time OR[31] = 1
223 *
224 * 0 4 8 12 16 20 24 28
225 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_BCSR (0xf8000000)
Andy Fleming67431052007-04-23 02:54:25 -0500228
229/*Chip slelect 4 - PIB*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_BR4_PRELIM 0xf8008801
231#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
Andy Fleming67431052007-04-23 02:54:25 -0500232
233/*Chip select 5 - PIB*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_BR5_PRELIM 0xf8010801
235#define CONFIG_SYS_OR5_PRELIM 0xffff69f7
Andy Fleming67431052007-04-23 02:54:25 -0500236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_INIT_RAM_LOCK 1
238#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
239#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
Andy Fleming67431052007-04-23 02:54:25 -0500240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
242#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
243#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Andy Fleming67431052007-04-23 02:54:25 -0500244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
246#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Andy Fleming67431052007-04-23 02:54:25 -0500247
248/* Serial Port */
249#define CONFIG_CONS_INDEX 1
250#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_NS16550
252#define CONFIG_SYS_NS16550_SERIAL
253#define CONFIG_SYS_NS16550_REG_SIZE 1
254#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Andy Fleming67431052007-04-23 02:54:25 -0500255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_BAUDRATE_TABLE \
Andy Fleming67431052007-04-23 02:54:25 -0500257 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
260#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Andy Fleming67431052007-04-23 02:54:25 -0500261
262/* Use the HUSH parser*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_HUSH_PARSER
264#ifdef CONFIG_SYS_HUSH_PARSER
265#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Andy Fleming67431052007-04-23 02:54:25 -0500266#endif
267
268/* pass open firmware flat tree */
Kumar Galac4808612007-11-29 01:06:19 -0600269#define CONFIG_OF_LIBFDT 1
270#define CONFIG_OF_BOARD_SETUP 1
271#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Andy Fleming67431052007-04-23 02:54:25 -0500272
273/*
274 * I2C
275 */
276#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
277#define CONFIG_HARD_I2C /* I2C with hardware support*/
278#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Haiying Wangc59e4092007-06-19 14:18:34 -0400279#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
281#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
282#define CONFIG_SYS_I2C_SLAVE 0x7F
283#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
284#define CONFIG_SYS_I2C_OFFSET 0x3000
285#define CONFIG_SYS_I2C2_OFFSET 0x3100
Andy Fleming67431052007-04-23 02:54:25 -0500286
287/*
288 * General PCI
289 * Memory Addresses are mapped 1-1. I/O is mapped from 0
290 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600291#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600292#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600293#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600295#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600296#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
298#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
Andy Fleming67431052007-04-23 02:54:25 -0500299
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600300#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600301#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600302#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600304#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600305#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
307#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
Andy Fleming67431052007-04-23 02:54:25 -0500308
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600309#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600310#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000
Kumar Galaa6e04c32008-12-02 16:08:38 -0600311#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000
Andy Fleming67431052007-04-23 02:54:25 -0500312
Andy Flemingda9d4612007-08-14 00:14:25 -0500313#ifdef CONFIG_QE
314/*
315 * QE UEC ethernet configuration
316 */
317#define CONFIG_UEC_ETH
318#ifndef CONFIG_TSEC_ENET
Andy Flemingb96c83d2007-08-15 20:03:34 -0500319#define CONFIG_ETHPRIME "FSL UEC0"
Andy Flemingda9d4612007-08-14 00:14:25 -0500320#endif
321#define CONFIG_PHY_MODE_NEED_CHANGE
322#define CONFIG_eTSEC_MDIO_BUS
323
324#ifdef CONFIG_eTSEC_MDIO_BUS
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200325#define CONFIG_MIIM_ADDRESS 0xE0024520
Andy Flemingda9d4612007-08-14 00:14:25 -0500326#endif
327
328#define CONFIG_UEC_ETH1 /* GETH1 */
329
330#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
332#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
333#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
334#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
335#define CONFIG_SYS_UEC1_PHY_ADDR 7
Heiko Schocher582c55a2010-01-20 09:04:28 +0100336#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
337#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
Andy Flemingda9d4612007-08-14 00:14:25 -0500338#endif
339
340#define CONFIG_UEC_ETH2 /* GETH2 */
341
342#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
344#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
345#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
346#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
347#define CONFIG_SYS_UEC2_PHY_ADDR 1
Heiko Schocher582c55a2010-01-20 09:04:28 +0100348#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
349#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
Andy Flemingda9d4612007-08-14 00:14:25 -0500350#endif
351#endif /* CONFIG_QE */
352
Haiying Wangf30ad492007-11-19 10:02:13 -0500353#if defined(CONFIG_PCI)
354
355#define CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200356#define CONFIG_PCI_PNP /* do pci plug-and-play */
Haiying Wangf30ad492007-11-19 10:02:13 -0500357
Andy Fleming67431052007-04-23 02:54:25 -0500358#undef CONFIG_EEPRO100
359#undef CONFIG_TULIP
360
361#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Andy Fleming67431052007-04-23 02:54:25 -0500363
364#endif /* CONFIG_PCI */
365
Andy Fleming67431052007-04-23 02:54:25 -0500366#ifndef CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200367#define CONFIG_NET_MULTI 1
Andy Fleming67431052007-04-23 02:54:25 -0500368#endif
369
Andy Flemingda9d4612007-08-14 00:14:25 -0500370#if defined(CONFIG_TSEC_ENET)
371
Andy Fleming67431052007-04-23 02:54:25 -0500372#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500373#define CONFIG_TSEC1 1
374#define CONFIG_TSEC1_NAME "eTSEC0"
375#define CONFIG_TSEC2 1
376#define CONFIG_TSEC2_NAME "eTSEC1"
Andy Fleming67431052007-04-23 02:54:25 -0500377
378#define TSEC1_PHY_ADDR 2
379#define TSEC2_PHY_ADDR 3
380
381#define TSEC1_PHYIDX 0
382#define TSEC2_PHYIDX 0
383
Andy Fleming3a790132007-08-15 20:03:25 -0500384#define TSEC1_FLAGS TSEC_GIGABIT
385#define TSEC2_FLAGS TSEC_GIGABIT
386
Andy Flemingb96c83d2007-08-15 20:03:34 -0500387/* Options are: eTSEC[0-1] */
Andy Fleming67431052007-04-23 02:54:25 -0500388#define CONFIG_ETHPRIME "eTSEC0"
389
390#endif /* CONFIG_TSEC_ENET */
391
392/*
393 * Environment
394 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200395#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200397#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
398#define CONFIG_ENV_SIZE 0x2000
Andy Fleming67431052007-04-23 02:54:25 -0500399
400#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Andy Fleming67431052007-04-23 02:54:25 -0500402
Jon Loeliger2835e512007-06-13 13:22:08 -0500403
404/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500405 * BOOTP options
406 */
407#define CONFIG_BOOTP_BOOTFILESIZE
408#define CONFIG_BOOTP_BOOTPATH
409#define CONFIG_BOOTP_GATEWAY
410#define CONFIG_BOOTP_HOSTNAME
411
412
413/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500414 * Command line configuration.
415 */
416#include <config_cmd_default.h>
417
418#define CONFIG_CMD_PING
419#define CONFIG_CMD_I2C
420#define CONFIG_CMD_MII
Kumar Gala82ac8c92007-12-07 12:04:30 -0600421#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500422#define CONFIG_CMD_IRQ
423#define CONFIG_CMD_SETEXPR
Jon Loeliger2835e512007-06-13 13:22:08 -0500424
Andy Fleming67431052007-04-23 02:54:25 -0500425#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500426 #define CONFIG_CMD_PCI
Andy Fleming67431052007-04-23 02:54:25 -0500427#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500428
Andy Fleming67431052007-04-23 02:54:25 -0500429
430#undef CONFIG_WATCHDOG /* watchdog disabled */
431
432/*
433 * Miscellaneous configurable options
434 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kumar Gala22abb2d2007-11-29 10:34:28 -0600436#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
438#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500439#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Andy Fleming67431052007-04-23 02:54:25 -0500441#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Andy Fleming67431052007-04-23 02:54:25 -0500443#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
445#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
446#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
447#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Andy Fleming67431052007-04-23 02:54:25 -0500448
449/*
450 * For booting Linux, the board info and command line data
Kumar Gala89188a62009-07-15 08:54:50 -0500451 * have to be in the first 16 MB of memory, since this is
Andy Fleming67431052007-04-23 02:54:25 -0500452 * the maximum mapped by the Linux kernel during initialization.
453 */
Kumar Gala89188a62009-07-15 08:54:50 -0500454#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Andy Fleming67431052007-04-23 02:54:25 -0500455
Andy Fleming67431052007-04-23 02:54:25 -0500456/*
457 * Internal Definitions
458 *
459 * Boot Flags
460 */
461#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
462#define BOOTFLAG_WARM 0x02 /* Software reboot */
463
Jon Loeliger2835e512007-06-13 13:22:08 -0500464#if defined(CONFIG_CMD_KGDB)
Andy Fleming67431052007-04-23 02:54:25 -0500465#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
466#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
467#endif
468
469/*
470 * Environment Configuration
471 */
472
473/* The mac addresses for all ethernet interface */
Andy Flemingda9d4612007-08-14 00:14:25 -0500474#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
475#define CONFIG_HAS_ETH0
Andy Fleming67431052007-04-23 02:54:25 -0500476#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
477#define CONFIG_HAS_ETH1
478#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
479#define CONFIG_HAS_ETH2
480#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
Andy Flemingda9d4612007-08-14 00:14:25 -0500481#define CONFIG_HAS_ETH3
482#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
Andy Fleming67431052007-04-23 02:54:25 -0500483#endif
484
485#define CONFIG_IPADDR 192.168.1.253
486
487#define CONFIG_HOSTNAME unknown
488#define CONFIG_ROOTPATH /nfsroot
489#define CONFIG_BOOTFILE your.uImage
490
491#define CONFIG_SERVERIP 192.168.1.1
492#define CONFIG_GATEWAYIP 192.168.1.1
493#define CONFIG_NETMASK 255.255.255.0
494
495#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
496
497#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
498#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
499
500#define CONFIG_BAUDRATE 115200
501
502#define CONFIG_EXTRA_ENV_SETTINGS \
503 "netdev=eth0\0" \
504 "consoledev=ttyS0\0" \
505 "ramdiskaddr=600000\0" \
506 "ramdiskfile=your.ramdisk.u-boot\0" \
507 "fdtaddr=400000\0" \
508 "fdtfile=your.fdt.dtb\0" \
509 "nfsargs=setenv bootargs root=/dev/nfs rw " \
510 "nfsroot=$serverip:$rootpath " \
511 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
512 "console=$consoledev,$baudrate $othbootargs\0" \
513 "ramargs=setenv bootargs root=/dev/ram rw " \
514 "console=$consoledev,$baudrate $othbootargs\0" \
515
516
517#define CONFIG_NFSBOOTCOMMAND \
518 "run nfsargs;" \
519 "tftp $loadaddr $bootfile;" \
520 "tftp $fdtaddr $fdtfile;" \
521 "bootm $loadaddr - $fdtaddr"
522
523
524#define CONFIG_RAMBOOTCOMMAND \
525 "run ramargs;" \
526 "tftp $ramdiskaddr $ramdiskfile;" \
527 "tftp $loadaddr $bootfile;" \
528 "bootm $loadaddr $ramdiskaddr"
529
530#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
531
532#endif /* __CONFIG_H */