blob: 6256b3a778f5d19da0b9037d0a3e6dbcf001c70a [file] [log] [blame]
Peng Fan6f6058b2016-01-28 16:55:04 +08001/*
2 * Copyright (C) 2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
Peng Fan8cf22312018-01-10 13:20:32 +08008#include <asm/io.h>
Peng Fanecd7ab52018-01-10 13:20:33 +08009#include <asm/mach-imx/sys_proto.h>
Peng Fan6f6058b2016-01-28 16:55:04 +080010#include <command.h>
Peng Fanecd7ab52018-01-10 13:20:33 +080011#include <imx_sip.h>
Tom Rini20b9f2e2018-01-03 08:52:39 -050012#include <linux/compiler.h>
Peng Fan6f6058b2016-01-28 16:55:04 +080013
Peng Fan8cf22312018-01-10 13:20:32 +080014int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
Peng Fan6f6058b2016-01-28 16:55:04 +080015{
Peng Fan8cf22312018-01-10 13:20:32 +080016 ulong stack, pc;
17
18 if (!boot_private_data)
19 return -EINVAL;
20
21 stack = *(ulong *)boot_private_data;
22 pc = *(ulong *)(boot_private_data + 4);
23
24 /* Set the stack and pc to M4 bootROM */
25 writel(stack, M4_BOOTROM_BASE_ADDR);
26 writel(pc, M4_BOOTROM_BASE_ADDR + 4);
27
28 /* Enable M4 */
Peng Fanecd7ab52018-01-10 13:20:33 +080029#ifdef CONFIG_MX8M
30 call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
31#else
Peng Fan8cf22312018-01-10 13:20:32 +080032 clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
33 SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
Peng Fanecd7ab52018-01-10 13:20:33 +080034#endif
Peng Fan8cf22312018-01-10 13:20:32 +080035
36 return 0;
Peng Fan6f6058b2016-01-28 16:55:04 +080037}
38
Peng Fan8cf22312018-01-10 13:20:32 +080039int arch_auxiliary_core_check_up(u32 core_id)
Peng Fan6f6058b2016-01-28 16:55:04 +080040{
Peng Fanecd7ab52018-01-10 13:20:33 +080041#ifdef CONFIG_MX8M
42 return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
43#else
Peng Fan8cf22312018-01-10 13:20:32 +080044 unsigned int val;
45
46 val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
47
48 if (val & SRC_M4C_NON_SCLR_RST_MASK)
49 return 0; /* assert in reset */
50
51 return 1;
Peng Fanecd7ab52018-01-10 13:20:33 +080052#endif
Peng Fan6f6058b2016-01-28 16:55:04 +080053}
54
Peng Fan6f6058b2016-01-28 16:55:04 +080055/*
56 * To i.MX6SX and i.MX7D, the image supported by bootaux needs
57 * the reset vector at the head for the image, with SP and PC
58 * as the first two words.
59 *
60 * Per the cortex-M reference manual, the reset vector of M4 needs
61 * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
62 * of that vector. So to boot M4, the A core must build the M4's reset
63 * vector with getting the PC and SP from image and filling them to
64 * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
65 * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
66 * accessing the M4 TCMUL.
67 */
Tom Rini20b9f2e2018-01-03 08:52:39 -050068static int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Peng Fan6f6058b2016-01-28 16:55:04 +080069{
70 ulong addr;
71 int ret, up;
72
73 if (argc < 2)
74 return CMD_RET_USAGE;
75
76 up = arch_auxiliary_core_check_up(0);
77 if (up) {
78 printf("## Auxiliary core is already up\n");
79 return CMD_RET_SUCCESS;
80 }
81
82 addr = simple_strtoul(argv[1], NULL, 16);
83
84 printf("## Starting auxiliary core at 0x%08lX ...\n", addr);
85
86 ret = arch_auxiliary_core_up(0, addr);
87 if (ret)
88 return CMD_RET_FAILURE;
89
90 return CMD_RET_SUCCESS;
91}
92
93U_BOOT_CMD(
94 bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
95 "Start auxiliary core",
96 ""
97);