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Wolfgang Denkb20d0032005-08-05 12:19:30 +02001/*
2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * MicroSys PM856 board configuration file
27 *
28 * Please refer to doc/README.mpc85xx for more info.
29 *
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/* High Level Configuration Options */
38#define CONFIG_BOOKE 1 /* BOOKE */
39#define CONFIG_E500 1 /* BOOKE e500 family */
40#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
41#define CONFIG_MPC8560 1 /* MPC8560 specific */
Wolfgang Denk452e8e72005-08-08 00:47:14 +020042#define CONFIG_CPM2 1 /* Has a CPM2 */
Wolfgang Denkb20d0032005-08-05 12:19:30 +020043#define CONFIG_PM856 1 /* PM856 board specific */
44
45#define CONFIG_PCI
46#define CONFIG_TSEC_ENET /* tsec ethernet support */
47#define CONFIG_ENV_OVERWRITE
48#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/
49#define CONFIG_DDR_ECC /* only for ECC DDR module */
50#define CONFIG_DDR_DLL /* possible DLL fix needed */
51#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
Wolfgang Denk452e8e72005-08-08 00:47:14 +020052#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
Wolfgang Denkb20d0032005-08-05 12:19:30 +020053
54
55/*
56 * sysclk for MPC85xx
57 *
58 * Two valid values are:
59 * 33000000
60 * 66000000
61 *
62 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
63 * is likely the desired value here, so that is now the default.
64 * The board, however, can run at 66MHz. In any event, this value
65 * must match the settings of some switches. Details can be found
66 * in the README.mpc85xxads.
67 */
68
69#ifndef CONFIG_SYS_CLK_FREQ
70#define CONFIG_SYS_CLK_FREQ 66000000
71#endif
72
73
74/*
75 * These can be toggled for performance analysis, otherwise use default.
76 */
77#define CONFIG_L2_CACHE /* toggle L2 cache */
78#define CONFIG_BTB /* toggle branch predition */
79#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
80
81#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
82
83#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
84
85#undef CFG_DRAM_TEST /* memory test, takes time */
86#define CFG_MEMTEST_START 0x00200000 /* memtest region */
87#define CFG_MEMTEST_END 0x00400000
88
89
90/*
91 * Base addresses -- Note these are effective addresses where the
92 * actual resources get mapped (not physical addresses)
93 */
94#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
95#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
96#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
97
98
99/*
100 * DDR Setup
101 */
102#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
103#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
104
105#if defined(CONFIG_SPD_EEPROM)
106 /*
107 * Determine DDR configuration from I2C interface.
108 */
109 #define SPD_EEPROM_ADDRESS 0x58 /* DDR DIMM */
110
111#else
112 /*
113 * Manually set up DDR parameters
114 */
115 #define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */
116 #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */
117 #define CFG_DDR_CS0_CONFIG 0x80000102
118 #define CFG_DDR_TIMING_1 0x47444321
119 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
120 #define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */
121 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
122 #define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
123#endif
124
125
126/*
127 * SDRAM on the Local Bus
128 */
129#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
130#define CFG_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */
131
132#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
133#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
134
135#define CFG_OR0_PRELIM 0xfe006f67 /* 32MB Flash */
136#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
137#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
138#undef CFG_FLASH_CHECKSUM
139#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
140#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
141
142#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
143
144#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
145#define CFG_RAMBOOT
146#else
147#undef CFG_RAMBOOT
148#endif
149
150#define CFG_FLASH_CFI_DRIVER
151#define CFG_FLASH_CFI
152#define CFG_FLASH_EMPTY_INFO
153
154#undef CONFIG_CLOCKS_IN_MHZ
155
156
157/*
158 * Local Bus Definitions
159 */
160
161#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
162#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
163#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
164#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
165
166
167#define CONFIG_L1_INIT_RAM
168#define CFG_INIT_RAM_LOCK 1
169#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
170#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
171
172#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
173#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
174#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
175
176#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
177#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
178
179/* Serial Port */
180#define CONFIG_CONS_ON_SCC /* define if console on SCC */
181#undef CONFIG_CONS_NONE /* define if console on something else */
182#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
183
184#define CFG_BAUDRATE_TABLE \
185 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
186
187/* Use the HUSH parser */
188#define CFG_HUSH_PARSER
189#ifdef CFG_HUSH_PARSER
190#define CFG_PROMPT_HUSH_PS2 "> "
191#endif
192
193/* I2C */
194#define CONFIG_HARD_I2C /* I2C with hardware support*/
195#undef CONFIG_SOFT_I2C /* I2C bit-banged */
196#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
197#define CFG_I2C_SLAVE 0x7F
198#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
199
200/*
201 * EEPROM configuration
202 */
203#define CFG_I2C_EEPROM_ADDR 0x58
204#define CFG_I2C_EEPROM_ADDR_LEN 1
205#define CFG_EEPROM_PAGE_WRITE_BITS 4
206#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
207
208/*
209 * RTC configuration
210 */
211#define CONFIG_RTC_PCF8563
212#define CFG_I2C_RTC_ADDR 0x51
213
214/* RapidIO MMU */
215#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
216#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
217#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
218
219/*
220 * General PCI
221 * Addresses are mapped 1-1.
222 */
223#define CFG_PCI1_MEM_BASE 0x80000000
224#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
225#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
226#define CFG_PCI1_IO_BASE 0xe2000000
227#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
228#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
229
230#if defined(CONFIG_PCI)
231
232#define CONFIG_NET_MULTI
233#define CONFIG_PCI_PNP /* do pci plug-and-play */
234
235#undef CONFIG_EEPRO100
236#undef CONFIG_TULIP
237
238#if !defined(CONFIG_PCI_PNP)
239 #define PCI_ENET0_IOADDR 0xe0000000
240 #define PCI_ENET0_MEMADDR 0xe0000000
241 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
242#endif
243
244#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
245#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
246
247#endif /* CONFIG_PCI */
248
249
250#if defined(CONFIG_TSEC_ENET)
251
252#ifndef CONFIG_NET_MULTI
253#define CONFIG_NET_MULTI 1
254#endif
255
256#define CONFIG_MII 1 /* MII PHY management */
257#define CONFIG_MPC85XX_TSEC1 1
Wolfgang Denk452e8e72005-08-08 00:47:14 +0200258#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200259#define CONFIG_MPC85XX_TSEC2 1
Wolfgang Denk452e8e72005-08-08 00:47:14 +0200260#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200261#undef CONFIG_MPC85XX_FEC
262#define TSEC1_PHY_ADDR 0
263#define TSEC2_PHY_ADDR 1
264#define TSEC1_PHYIDX 0
265#define TSEC2_PHYIDX 0
266
267#endif /* CONFIG_TSEC_ENET */
268
Wolfgang Denk452e8e72005-08-08 00:47:14 +0200269#define CONFIG_ETHPRIME "TSEC0"
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200270
271#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
272#undef CONFIG_ETHER_NONE /* define if ether on something else */
273
274
275/*
276 * - Rx-CLK is CLK15
277 * - Tx-CLK is CLK14
278 * - Select bus for bd/buffers
279 * - Full duplex
280 */
281#define CONFIG_ETHER_ON_FCC3
282#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
283#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
284#define CFG_CPMFCR_RAMTYPE 0
285#define CFG_FCC_PSMR (FCC_PSMR_FDE)
286
287/*
288 * Environment
289 */
290#ifndef CFG_RAMBOOT
291 #define CFG_ENV_IS_IN_FLASH 1
292 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x80000)
293 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
294 #define CFG_ENV_SIZE 0x2000
295#else
296 #define CFG_NO_FLASH 1 /* Flash is not usable now */
297 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
298 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
299 #define CFG_ENV_SIZE 0x2000
300#endif
301
302#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
303#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
304
305#if defined(CFG_RAMBOOT)
306 #if defined(CONFIG_PCI)
307 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
308 | CFG_CMD_PING \
309 | CFG_CMD_PCI \
310 | CFG_CMD_I2C) \
311 & \
312 ~(CFG_CMD_ENV \
313 | CFG_CMD_LOADS))
314 #else
315 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
316 | CFG_CMD_PING \
317 | CFG_CMD_I2C) \
318 & \
319 ~(CFG_CMD_ENV \
320 | CFG_CMD_LOADS))
321 #endif
322#else
323 #if defined(CONFIG_PCI)
324 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
325 | CFG_CMD_EEPROM \
326 | CFG_CMD_DATE \
327 | CFG_CMD_PCI \
328 | CFG_CMD_PING \
329 | CFG_CMD_I2C)
330 #else
331 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
332 | CFG_CMD_EEPROM \
333 | CFG_CMD_DATE \
334 | CFG_CMD_PING \
335 | CFG_CMD_I2C)
336 #endif
337#endif
338
339#include <cmd_confdefs.h>
340
341#undef CONFIG_WATCHDOG /* watchdog disabled */
342
343/*
344 * Miscellaneous configurable options
345 */
346#define CFG_LONGHELP /* undef to save memory */
347#define CFG_LOAD_ADDR 0x1000000 /* default load address */
348#define CFG_PROMPT "=> " /* Monitor Command Prompt */
349
350#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
351 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
352#else
353 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
354#endif
355
356#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
357#define CFG_MAXARGS 16 /* max number of command args */
358#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
359#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
360#define CONFIG_LOOPW
361
362/*
363 * For booting Linux, the board info and command line data
364 * have to be in the first 8 MB of memory, since this is
365 * the maximum mapped by the Linux kernel during initialization.
366 */
367#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
368
369/* Cache Configuration */
370#define CFG_DCACHE_SIZE 32768
371#define CFG_CACHELINE_SIZE 32
372#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
373#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
374#endif
375
376/*
377 * Internal Definitions
378 *
379 * Boot Flags
380 */
381#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
382#define BOOTFLAG_WARM 0x02 /* Software reboot */
383
384#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
385#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
386#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
387#endif
388
389
390/*
391 * Environment Configuration
392 */
393
394/* The mac addresses for all ethernet interface */
395#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
396#define CONFIG_ETHADDR 00:40:42:01:00:00
397#define CONFIG_HAS_ETH1
398#define CONFIG_ETH1ADDR 00:40:42:01:00:01
399#define CONFIG_HAS_ETH2
400#define CONFIG_ETH2ADDR 00:40:42:01:00:02
401#endif
402
403
404#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx
405#define CONFIG_BOOTFILE pm856/uImage
406
407#define CONFIG_HOSTNAME pm856
408#define CONFIG_IPADDR 192.168.0.103
409#define CONFIG_SERVERIP 192.168.0.64
410#define CONFIG_GATEWAYIP 192.168.0.1
411#define CONFIG_NETMASK 255.255.255.0
412
413#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
414
415#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
416#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
417
418#define CONFIG_BAUDRATE 9600
419
420#define CONFIG_EXTRA_ENV_SETTINGS \
421 "netdev=eth0\0" \
422 "consoledev=ttyS0\0" \
423 "ramdiskaddr=400000\0" \
424 "ramdiskfile=pm856/uRamdisk\0"
425
426#define CONFIG_NFSBOOTCOMMAND \
427 "setenv bootargs root=/dev/nfs rw " \
428 "nfsroot=$serverip:$rootpath " \
429 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
430 "console=$consoledev,$baudrate $othbootargs;" \
431 "tftp $loadaddr $bootfile;" \
432 "bootm $loadaddr"
433
434#define CONFIG_RAMBOOTCOMMAND \
435 "setenv bootargs root=/dev/ram rw " \
436 "console=$consoledev,$baudrate $othbootargs;" \
437 "tftp $ramdiskaddr $ramdiskfile;" \
438 "tftp $loadaddr $bootfile;" \
439 "bootm $loadaddr $ramdiskaddr"
440
441#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
442
443#endif /* __CONFIG_H */