blob: 01df8b1273268d17e77397f7484e70e9414ad01b [file] [log] [blame]
Rafal Jaworowski8993e542007-07-27 14:43:59 +02001/*
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +02002 * (C) Copyright 2007-2009 DENX Software Engineering
Rafal Jaworowski8993e542007-07-27 14:43:59 +02003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
Wolfgang Denk72601d02009-05-16 10:47:41 +020024 * MPC5121ADS board configuration file
Rafal Jaworowski8993e542007-07-27 14:43:59 +020025 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Wolfgang Denk72601d02009-05-16 10:47:41 +020030#define CONFIG_MPC5121ADS 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +020031/*
Wolfgang Denk72601d02009-05-16 10:47:41 +020032 * Memory map for the MPC5121ADS board:
Rafal Jaworowski8993e542007-07-27 14:43:59 +020033 *
34 * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB)
35 * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
36 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
37 * 0x8200_0000 - 0x8200_001F CPLD (32 B)
John Rigby5f91db72008-02-26 09:38:14 -070038 * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB)
39 * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB)
40 * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
Rafal Jaworowski8993e542007-07-27 14:43:59 +020041 * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
42 */
43
44/*
45 * High Level Configuration Options
46 */
47#define CONFIG_E300 1 /* E300 Family */
48#define CONFIG_MPC512X 1 /* MPC512X family */
York Sun0e1bad42008-05-05 10:20:01 -050049
Wolfgang Denk2ae18242010-10-06 09:05:45 +020050#define CONFIG_SYS_TEXT_BASE 0xFFF00000
51
York Sun0e1bad42008-05-05 10:20:01 -050052/* video */
Timur Tabi7d3053f2011-02-15 17:09:19 -060053#ifdef CONFIG_FSL_DIU_FB
54#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100)
55#define CONFIG_VIDEO
Timur Tabie69e5202010-08-31 19:56:43 -050056#define CONFIG_CMD_BMP
York Sun0e1bad42008-05-05 10:20:01 -050057#define CONFIG_CFB_CONSOLE
Timur Tabi7d3053f2011-02-15 17:09:19 -060058#define CONFIG_VIDEO_SW_CURSOR
York Sun0e1bad42008-05-05 10:20:01 -050059#define CONFIG_VGA_AS_SINGLE_DEVICE
Timur Tabie69e5202010-08-31 19:56:43 -050060#define CONFIG_VIDEO_LOGO
61#define CONFIG_VIDEO_BMP_LOGO
York Sun0e1bad42008-05-05 10:20:01 -050062#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +020063
John Rigby5f91db72008-02-26 09:38:14 -070064/* CONFIG_PCI is defined at config time */
Rafal Jaworowski8993e542007-07-27 14:43:59 +020065
Wolfgang Denk72601d02009-05-16 10:47:41 +020066#ifdef CONFIG_MPC5121ADS_REV2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */
Martha Marxf31c49d2008-05-29 14:23:25 -040068#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
Martha Marxf31c49d2008-05-29 14:23:25 -040070#define CONFIG_PCI
71#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +020072
73#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
York Sun0e1bad42008-05-05 10:20:01 -050074#define CONFIG_MISC_INIT_R
Rafal Jaworowski8993e542007-07-27 14:43:59 +020075
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_IMMR 0x80000000
Rafal Jaworowski8993e542007-07-27 14:43:59 +020077
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
79#define CONFIG_SYS_MEMTEST_END 0x00400000
Rafal Jaworowski8993e542007-07-27 14:43:59 +020080
81/*
82 * DDR Setup - manually set all parameters as there's no SPD etc.
83 */
Wolfgang Denk72601d02009-05-16 10:47:41 +020084#ifdef CONFIG_MPC5121ADS_REV2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Martha Marxf31c49d2008-05-29 14:23:25 -040086#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_DDR_SIZE 512 /* MB */
Martha Marxf31c49d2008-05-29 14:23:25 -040088#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
90#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Anatolij Gustschinb9947bb2010-04-24 19:27:08 +020091#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
Rafal Jaworowski8993e542007-07-27 14:43:59 +020092
Anatolij Gustschin5d937e82010-04-24 19:27:07 +020093#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
94
Rafal Jaworowski8993e542007-07-27 14:43:59 +020095/* DDR Controller Configuration
Wolfgang Denkb1b54e32007-08-02 21:27:46 +020096 *
97 * SYS_CFG:
98 * [31:31] MDDRC Soft Reset: Diabled
99 * [30:30] DRAM CKE pin: Enabled
100 * [29:29] DRAM CLK: Enabled
101 * [28:28] Command Mode: Enabled (For initialization only)
102 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
103 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
104 * [20:19] Read Test: DON'T USE
105 * [18:18] Self Refresh: Enabled
106 * [17:17] 16bit Mode: Disabled
107 * [16:13] Ready Delay: 2
108 * [12:12] Half DQS Delay: Disabled
109 * [11:11] Quarter DQS Delay: Disabled
110 * [10:08] Write Delay: 2
111 * [07:07] Early ODT: Disabled
112 * [06:06] On DIE Termination: Disabled
113 * [05:05] FIFO Overflow Clear: DON'T USE here
114 * [04:04] FIFO Underflow Clear: DON'T USE here
115 * [03:03] FIFO Overflow Pending: DON'T USE here
116 * [02:02] FIFO Underlfow Pending: DON'T USE here
117 * [01:01] FIFO Overlfow Enabled: Enabled
118 * [00:00] FIFO Underflow Enabled: Enabled
119 * TIME_CFG0
120 * [31:16] DRAM Refresh Time: 0 CSB clocks
121 * [15:8] DRAM Command Time: 0 CSB clocks
122 * [07:00] DRAM Precharge Time: 0 CSB clocks
123 * TIME_CFG1
124 * [31:26] DRAM tRFC:
125 * [25:21] DRAM tWR1:
126 * [20:17] DRAM tWRT1:
127 * [16:11] DRAM tDRR:
128 * [10:05] DRAM tRC:
129 * [04:00] DRAM tRAS:
130 * TIME_CFG2
131 * [31:28] DRAM tRCD:
132 * [27:23] DRAM tFAW:
133 * [22:19] DRAM tRTW1:
134 * [18:15] DRAM tCCD:
135 * [14:10] DRAM tRTP:
136 * [09:05] DRAM tRP:
137 * [04:00] DRAM tRPA
138 */
Wolfgang Denk72601d02009-05-16 10:47:41 +0200139#ifdef CONFIG_MPC5121ADS_REV2
Martha M Stan054197b2009-09-21 14:07:14 -0400140#define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168
142#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864
Martha Marxf31c49d2008-05-29 14:23:25 -0400143#else
Martha M Stan054197b2009-09-21 14:07:14 -0400144#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00
145#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
146#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
Martha Marxf31c49d2008-05-29 14:23:25 -0400147#endif
Martha M Stan054197b2009-09-21 14:07:14 -0400148#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200149
Martha M Stana5aa3992009-09-21 14:08:00 -0400150#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00
151#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189
152#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864
153
Martha M Stan054197b2009-09-21 14:07:14 -0400154#define CONFIG_SYS_DDRCMD_NOP 0x01380000
155#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
156#define CONFIG_SYS_DDRCMD_EM2 0x01020000
157#define CONFIG_SYS_DDRCMD_EM3 0x01030000
158#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000
159#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
Martha M Stana5aa3992009-09-21 14:08:00 -0400160
161#define DDRCMD_EMR_OCD(pr, ohm) ( \
162 (1 << 24) | /* MDDRC Command Request */ \
163 (1 << 16) | /* MODE Reg BA[2:0] */ \
164 (0 << 12) | /* Outputs 0=Enabled */ \
165 (0 << 11) | /* RDQS */ \
166 (1 << 10) | /* DQS# */ \
167 (pr << 7) | /* OCD prog 7=deflt,0=exit */ \
168 /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
169 ((ohm & 0x2) << 5)| /* Rtt1 */ \
170 (0 << 3) | /* additive posted CAS# */ \
171 ((ohm & 0x1) << 2)| /* Rtt0 */ \
172 (0 << 0) | /* Output Drive Strength */ \
173 (0 << 0)) /* DLL Enable 0=Normal */
174
175#define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0)
176#define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0)
177
178#define DDRCMD_MODE_REG(cas, wr) ( \
179 (1 << 24) | /* MDDRC Command Request */ \
180 (0 << 16) | /* MODE Reg BA[2:0] */ \
181 ((wr-1) << 9)| /* Write Recovery */ \
182 (cas << 4) | /* CAS */ \
183 (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \
184 (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */
185
186#define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3)
187#define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4)
188#define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8))
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200189
190/* DDR Priority Manager Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
192#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
193#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
194#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
195#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
196#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
197#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
198#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
199#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
200#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
201#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
202#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
203#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
204#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
205#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
206#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
207#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
208#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
209#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
210#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
211#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
212#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
213#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200214
215/*
216 * NOR FLASH on the Local Bus
217 */
Martha Marxf31c49d2008-05-29 14:23:25 -0400218#undef CONFIG_BKUP_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200220#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Martha Marxf31c49d2008-05-29 14:23:25 -0400221#ifdef CONFIG_BKUP_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
223#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */
Martha Marxf31c49d2008-05-29 14:23:25 -0400224#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
226#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */
Martha Marxf31c49d2008-05-29 14:23:25 -0400227#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
229#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
230#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
231#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#undef CONFIG_SYS_FLASH_CHECKSUM
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200234
235/*
Stefan Roese229549a2009-06-09 16:57:47 +0200236 * NAND FLASH
Wolfgang Denk13946922009-06-14 20:58:50 +0200237 * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
Stefan Roese229549a2009-06-09 16:57:47 +0200238 */
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200239#define CONFIG_CMD_NAND /* enable NAND support */
240#define CONFIG_JFFS2_NAND /* with JFFS2 on it */
Stefan Roese229549a2009-06-09 16:57:47 +0200241#define CONFIG_NAND_MPC5121_NFC
242#define CONFIG_SYS_NAND_BASE 0x40000000
243
244#define CONFIG_SYS_MAX_NAND_DEVICE 2
Stefan Roese229549a2009-06-09 16:57:47 +0200245#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
246
247/*
248 * Configuration parameters for MPC5121 NAND driver
249 */
250#define CONFIG_FSL_NFC_WIDTH 1
251#define CONFIG_FSL_NFC_WRITE_SIZE 2048
252#define CONFIG_FSL_NFC_SPARE_SIZE 64
253#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
254
255/*
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200256 * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
257 * window is 64KB
258 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_CPLD_BASE 0x82000000
260#define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200261
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_SRAM_BASE 0x30000000
263#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200264
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
266#define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
267#define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200268
269/* Use SRAM for initial stack */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200271#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of used area in RAM */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200272
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200273#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200275
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200276#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */
Stefan Roese229549a2009-06-09 16:57:47 +0200277#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
York Sun0e1bad42008-05-05 10:20:01 -0500278#ifdef CONFIG_FSL_DIU_FB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
York Sun0e1bad42008-05-05 10:20:01 -0500280#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
York Sun0e1bad42008-05-05 10:20:01 -0500282#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200283
284/*
285 * Serial Port
286 */
287#define CONFIG_CONS_INDEX 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200288
289/*
290 * Serial console configuration
291 */
292#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
293#if CONFIG_PSC_CONSOLE != 3
294#error CONFIG_PSC_CONSOLE must be 3
295#endif
296#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_BAUDRATE_TABLE \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200298 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
299
300#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
301#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
302#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
303#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
304
305#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
306/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_HUSH_PARSER
308#ifdef CONFIG_SYS_HUSH_PARSER
309#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200310#endif
311
John Rigby5f91db72008-02-26 09:38:14 -0700312/*
313 * PCI
314 */
315#ifdef CONFIG_PCI
316
317/*
318 * General PCI
319 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
321#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
322#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
323#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
324#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
325#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
326#define CONFIG_SYS_PCI_IO_BASE 0x00000000
327#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
328#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
John Rigby5f91db72008-02-26 09:38:14 -0700329
330
331#define CONFIG_PCI_PNP /* do pci plug-and-play */
332
333#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
334
335#endif
336
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200337/* I2C */
338#define CONFIG_HARD_I2C /* I2C with hardware support */
339#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
340#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
342#define CONFIG_SYS_I2C_SLAVE 0x7F
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200343#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200345#endif
346
347/*
Martha Marxabfbd0ae2009-01-26 10:45:07 -0700348 * IIM - IC Identification Module
349 */
350#undef CONFIG_IIM
351
352/*
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200353 * EEPROM configuration
354 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
356#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
357#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
358#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
Grzegorz Bernacki80020122007-10-09 13:58:24 +0200359
360/*
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200361 * Ethernet configuration
362 */
363#define CONFIG_MPC512x_FEC 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200364#define CONFIG_PHY_ADDR 0x1
365#define CONFIG_MII 1 /* MII PHY management */
Martha Marxf31c49d2008-05-29 14:23:25 -0400366#define CONFIG_FEC_AN_TIMEOUT 1
John Rigbyef11df62008-08-05 17:38:57 -0600367#define CONFIG_HAS_ETH0
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200368
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200369/*
370 * Configure on-board RTC
371 */
Martha Marxf31c49d2008-05-29 14:23:25 -0400372#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200374
375/*
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200376 * USB Support
377 */
378#define CONFIG_CMD_USB
379
380#if defined(CONFIG_CMD_USB)
381#define CONFIG_USB_EHCI /* Enable EHCI Support */
382#define CONFIG_USB_EHCI_FSL /* On a FSL platform */
383#define CONFIG_EHCI_MMIO_BIG_ENDIAN /* With big-endian regs */
384#define CONFIG_EHCI_DESC_BIG_ENDIAN
385#define CONFIG_EHCI_IS_TDI
386#define CONFIG_USB_STORAGE
387#endif
388
389/*
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200390 * Environment
391 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200392#define CONFIG_ENV_IS_IN_FLASH 1
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200393/* This has to be a multiple of the Flash sector size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200395#define CONFIG_ENV_SIZE 0x2000
Martha Marxf31c49d2008-05-29 14:23:25 -0400396#ifdef CONFIG_BKUP_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200397#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */
Martha Marxf31c49d2008-05-29 14:23:25 -0400398#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200399#define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
Martha Marxf31c49d2008-05-29 14:23:25 -0400400#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200401
402/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200403#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
404#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200405
406#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200408
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200409#include <config_cmd_default.h>
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200410
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200411#define CONFIG_CMD_ASKENV
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200412#define CONFIG_CMD_DATE
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200413#define CONFIG_CMD_DHCP
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200414#define CONFIG_CMD_EEPROM
415#define CONFIG_CMD_EXT2
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200416#define CONFIG_CMD_I2C
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200417#define CONFIG_CMD_IDE
418#define CONFIG_CMD_JFFS2
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200419#define CONFIG_CMD_MII
420#define CONFIG_CMD_NFS
421#define CONFIG_CMD_PING
422#define CONFIG_CMD_REGINFO
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200423
Martha Marxabfbd0ae2009-01-26 10:45:07 -0700424#undef CONFIG_CMD_FUSE
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200425
426#if defined(CONFIG_PCI)
427#define CONFIG_CMD_PCI
428#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200429
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200430/*
431 * Dynamic MTD partition support
432 */
433#define CONFIG_CMD_MTDPARTS
434#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
435#define CONFIG_FLASH_CFI_MTD
436#define MTDIDS_DEFAULT "nor0=fc000000.flash,nand0=mpc5121.nand"
437
438/*
439 * NOR flash layout:
440 *
441 * FC000000 - FEABFFFF 42.75 MiB User Data
442 * FEAC0000 - FFABFFFF 16 MiB Root File System
443 * FFAC0000 - FFEBFFFF 4 MiB Linux Kernel
444 * FFEC0000 - FFEFFFFF 256 KiB Device Tree
445 * FFF00000 - FFFFFFFF 1 MiB U-Boot (up to 512 KiB) and 2 x * env
446 *
447 * NAND flash layout: one big partition
448 */
449#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:43776k(user)," \
450 "16m(rootfs)," \
451 "4m(kernel)," \
452 "256k(dtb)," \
453 "1m(u-boot);" \
454 "mpc5121.nand:-(data)"
455
456
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200457#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
458
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700459#define CONFIG_DOS_PARTITION
460#define CONFIG_MAC_PARTITION
461#define CONFIG_ISO_PARTITION
Damien Dusha29c6fbe2010-10-14 15:27:06 +0200462
463#define CONFIG_CMD_FAT
464#define CONFIG_SUPPORT_VFAT
465
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700466#endif /* defined(CONFIG_CMD_IDE) */
467
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200468/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469 * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
470 * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200471 * to 0xFFFF, watchdog timeouts after about 64s. For details refer
472 * to chapter 36 of the MPC5121e Reference Manual.
473 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100474/* #define CONFIG_WATCHDOG */ /* enable watchdog */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200476
477 /*
478 * Miscellaneous configurable options
479 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_LONGHELP /* undef to save memory */
481#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
482#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200483
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200484#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200486#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200488#endif
489
490
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
492#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
493#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
494#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200495
496/*
497 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700498 * have to be in the first 256 MB of memory, since this is
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200499 * the maximum mapped by the Linux kernel during initialization.
500 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700501#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200502
503/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#define CONFIG_SYS_DCACHE_SIZE 32768
505#define CONFIG_SYS_CACHELINE_SIZE 32
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200506#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200508#endif
509
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510#define CONFIG_SYS_HID0_INIT 0x000000000
Wolfgang Denke2b66fe2009-03-26 10:00:57 +0100511#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200512#define CONFIG_SYS_HID2 HID2_HBE
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200513
Becky Bruce31d82672008-05-08 19:02:12 -0500514#define CONFIG_HIGH_BATS 1 /* High BATs supported */
515
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200516#ifdef CONFIG_CMD_KGDB
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200517#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
518#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
519#endif
520
521/*
522 * Environment Configuration
523 */
Wolfgang Denk66ffb182008-01-15 17:22:28 +0100524#define CONFIG_TIMESTAMP
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200525
Wolfgang Denk72601d02009-05-16 10:47:41 +0200526#define CONFIG_HOSTNAME mpc5121ads
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000527#define CONFIG_BOOTFILE "mpc5121ads/uImage"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000528#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200529
Wolfgang Denk8d103072008-01-13 23:37:50 +0100530#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200531
Wolfgang Denke27f3a62007-08-12 14:47:54 +0200532#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200533#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
534
535#define CONFIG_BAUDRATE 115200
536
537#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100538 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200539 "echo"
540
541#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100542 "u-boot_addr_r=200000\0" \
Wolfgang Denk51e46e22008-08-26 15:01:28 +0200543 "kernel_addr_r=600000\0" \
544 "fdt_addr_r=880000\0" \
545 "ramdisk_addr_r=900000\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100546 "u-boot_addr=FFF00000\0" \
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200547 "kernel_addr=FFAC0000\0" \
Wolfgang Denk51e46e22008-08-26 15:01:28 +0200548 "fdt_addr=FFEC0000\0" \
Wolfgang Denk7d4450a2009-06-14 20:58:53 +0200549 "ramdisk_addr=FEAC0000\0" \
Wolfgang Denk72601d02009-05-16 10:47:41 +0200550 "ramdiskfile=mpc5121ads/uRamdisk\0" \
551 "u-boot=mpc5121ads/u-boot.bin\0" \
552 "bootfile=mpc5121ads/uImage\0" \
553 "fdtfile=mpc5121ads/mpc5121ads.dtb\0" \
Wolfgang Denk51e46e22008-08-26 15:01:28 +0200554 "rootpath=/opt/eldk/ppc_6xx\n" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200555 "netdev=eth0\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100556 "consdev=ttyPSC0\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200557 "nfsargs=setenv bootargs root=/dev/nfs rw " \
558 "nfsroot=${serverip}:${rootpath}\0" \
559 "ramargs=setenv bootargs root=/dev/ram rw\0" \
560 "addip=setenv bootargs ${bootargs} " \
561 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
562 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100563 "addtty=setenv bootargs ${bootargs} " \
564 "console=${consdev},${baudrate}\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200565 "flash_nfs=run nfsargs addip addtty;" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200566 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200567 "flash_self=run ramargs addip addtty;" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100568 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
569 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
570 "tftp ${fdt_addr_r} ${fdtfile};" \
571 "run nfsargs addip addtty;" \
572 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
573 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
574 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200575 "tftp ${fdt_addr_r} ${fdtfile};" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100576 "run ramargs addip addtty;" \
Wolfgang Denk5b0b2b62008-03-03 12:36:49 +0100577 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
Detlev Zundela99715b2008-04-18 14:50:01 +0200578 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
Wolfgang Denk8d103072008-01-13 23:37:50 +0100579 "update=protect off ${u-boot_addr} +${filesize};" \
580 "era ${u-boot_addr} +${filesize};" \
581 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
582 "upd=run load update\0" \
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200583 ""
584
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200585#define CONFIG_BOOTCOMMAND "run flash_self"
586
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100587#define CONFIG_OF_LIBFDT 1
588#define CONFIG_OF_BOARD_SETUP 1
John Rigbyef11df62008-08-05 17:38:57 -0600589#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100590
591#define OF_CPU "PowerPC,5121@0"
John Rigbyef11df62008-08-05 17:38:57 -0600592#define OF_SOC_COMPAT "fsl,mpc5121-immr"
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100593#define OF_TBCLK (bd->bi_busfreq / 4)
John Rigbyac915282008-01-30 13:36:57 -0700594#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100595
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700596/*-----------------------------------------------------------------------
597 * IDE/ATA stuff
598 *-----------------------------------------------------------------------
599 */
600
601#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
602#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
603#undef CONFIG_IDE_LED /* LED for IDE not supported */
604
605#define CONFIG_IDE_RESET /* reset for IDE supported */
606#define CONFIG_IDE_PREINIT
607
608#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
609#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
610
611#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +0200612#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700613
614/* Offset for data I/O RefMan MPC5121EE Table 28-10 */
615#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
616
617/* Offset for normal register accesses */
618#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
619
620/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
621#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
622
623/* Interval between registers */
624#define CONFIG_SYS_ATA_STRIDE 4
625
Wolfgang Denk3b74e7e2009-05-16 10:47:45 +0200626#define ATA_BASE_ADDR get_pata_base()
Ralph Kondziella70a4da42009-01-26 12:34:36 -0700627
628/*
629 * Control register bit definitions
630 */
631#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
632#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
633#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
634#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
635#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
636#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
637#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
638#define FSL_ATA_CTRL_IORDY_EN 0x01000000
639
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200640#endif /* __CONFIG_H */