blob: bec54cb72c945c55d99e9ab4d37f9a455194283a [file] [log] [blame]
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +02001/*
2 * (C) Copyright 2006 DENX Software Engineering
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24
Jon Loeligerab3abcb2007-07-09 18:45:16 -050025#if defined(CONFIG_CMD_NAND)
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020026
27#include <nand.h>
28#include <asm/arch/pxa-regs.h>
29
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020030#ifdef CONFIG_SYS_DFC_DEBUG1
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020031# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
32#else
33# define DFC_DEBUG1(fmt, args...)
34#endif
35
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#ifdef CONFIG_SYS_DFC_DEBUG2
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020037# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
38#else
39# define DFC_DEBUG2(fmt, args...)
40#endif
41
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#ifdef CONFIG_SYS_DFC_DEBUG3
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020043# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
44#else
45# define DFC_DEBUG3(fmt, args...)
46#endif
47
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020048/* These really don't belong here, as they are specific to the NAND Model */
49static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
50
51static struct nand_bbt_descr delta_bbt_descr = {
52 .options = 0,
53 .offs = 0,
54 .len = 2,
55 .pattern = scan_ff_pattern
56};
57
Scott Wood66446412008-09-10 11:48:49 -050058static struct nand_ecclayout delta_oob = {
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020059 .eccbytes = 6,
60 .eccpos = {2, 3, 4, 5, 6, 7},
61 .oobfree = { {8, 2}, {12, 4} }
62};
63
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020064/*
65 * not required for Monahans DFC
66 */
William Juulcfa460a2007-10-31 13:53:06 +010067static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +020068{
69 return;
70}
71
72#if 0
73/* read device ready pin */
74static int dfc_device_ready(struct mtd_info *mtdinfo)
75{
76 if(NDSR & NDSR_RDY)
77 return 1;
78 else
79 return 0;
80 return 0;
81}
82#endif
83
84/*
85 * Write buf to the DFC Controller Data Buffer
86 */
87static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
88{
89 unsigned long bytes_multi = len & 0xfffffffc;
90 unsigned long rest = len & 0x3;
91 unsigned long *long_buf;
92 int i;
93
94 DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
95 if(bytes_multi) {
96 for(i=0; i<bytes_multi; i+=4) {
97 long_buf = (unsigned long*) &buf[i];
98 NDDB = *long_buf;
99 }
100 }
101 if(rest) {
102 printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
103 }
104 return;
105}
106
107
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200108/* The original:
109 * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
110 *
111 * Shouldn't this be "u_char * const buf" ?
112 */
113static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
114{
115 int i=0, j;
116
117 /* we have to be carefull not to overflow the buffer if len is
118 * not a multiple of 4 */
119 unsigned long bytes_multi = len & 0xfffffffc;
120 unsigned long rest = len & 0x3;
121 unsigned long *long_buf;
122
123 DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
124 /* if there are any, first copy multiple of 4 bytes */
125 if(bytes_multi) {
126 for(i=0; i<bytes_multi; i+=4) {
127 long_buf = (unsigned long*) &buf[i];
128 *long_buf = NDDB;
129 }
130 }
131
132 /* ...then the rest */
133 if(rest) {
134 unsigned long rest_data = NDDB;
135 for(j=0;j<rest; j++)
136 buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
137 }
138
139 return;
140}
141
142/*
143 * read a word. Not implemented as not used in NAND code.
144 */
145static u16 dfc_read_word(struct mtd_info *mtd)
146{
William Juulcfa460a2007-10-31 13:53:06 +0100147 printf("dfc_read_word: UNIMPLEMENTED.\n");
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200148 return 0;
149}
150
151/* global var, too bad: mk@tbd: move to ->priv pointer */
152static unsigned long read_buf = 0;
153static int bytes_read = -1;
154
155/*
156 * read a byte from NDDB Because we can only read 4 bytes from NDDB at
157 * a time, we buffer the remaining bytes. The buffer is reset when a
158 * new command is sent to the chip.
159 *
160 * WARNING:
161 * This function is currently only used to read status and id
162 * bytes. For these commands always 8 bytes need to be read from
163 * NDDB. So we read and discard these bytes right now. In case this
164 * function is used for anything else in the future, we must check
165 * what was the last command issued and read the appropriate amount of
166 * bytes respectively.
167 */
168static u_char dfc_read_byte(struct mtd_info *mtd)
169{
170 unsigned char byte;
171 unsigned long dummy;
172
173 if(bytes_read < 0) {
174 read_buf = NDDB;
175 dummy = NDDB;
176 bytes_read = 0;
177 }
178 byte = (unsigned char) (read_buf>>(8 * bytes_read++));
179 if(bytes_read >= 4)
180 bytes_read = -1;
181
182 DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
183 return byte;
184}
185
186/* calculate delta between OSCR values start and now */
187static unsigned long get_delta(unsigned long start)
188{
189 unsigned long cur = OSCR;
190
191 if(cur < start) /* OSCR overflowed */
192 return (cur + (start^0xffffffff));
193 else
194 return (cur - start);
195}
196
197/* delay function, this doesn't belong here */
198static void wait_us(unsigned long us)
199{
200 unsigned long start = OSCR;
201 us *= OSCR_CLK_FREQ;
202
203 while (get_delta(start) < us) {
204 /* do nothing */
205 }
206}
207
208static void dfc_clear_nddb(void)
209{
210 NDCR &= ~NDCR_ND_RUN;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211 wait_us(CONFIG_SYS_NAND_OTHER_TO);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200212}
213
214/* wait_event with timeout */
215static unsigned long dfc_wait_event(unsigned long event)
216{
217 unsigned long ndsr, timeout, start = OSCR;
218
219 if(!event)
220 return 0xff000000;
221 else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222 timeout = CONFIG_SYS_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200223 else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224 timeout = CONFIG_SYS_NAND_OTHER_TO * OSCR_CLK_FREQ;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200225
226 while(1) {
227 ndsr = NDSR;
228 if(ndsr & event) {
229 NDSR |= event;
230 break;
231 }
232 if(get_delta(start) > timeout) {
Jean-Christophe PLAGNIOL-VILLARD0a5676b2008-07-12 14:36:34 +0200233 DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200234 return 0xff000000;
235 }
236
237 }
238 return ndsr;
239}
240
241/* we don't always wan't to do this */
242static void dfc_new_cmd(void)
243{
244 int retry = 0;
245 unsigned long status;
246
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247 while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200248 /* Clear NDSR */
249 NDSR = 0xFFF;
250
251 /* set NDCR[NDRUN] */
252 if(!(NDCR & NDCR_ND_RUN))
253 NDCR |= NDCR_ND_RUN;
254
255 status = dfc_wait_event(NDSR_WRCMDREQ);
256
257 if(status & NDSR_WRCMDREQ)
258 return;
259
260 DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
261 dfc_clear_nddb();
262 }
263 DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
264}
265
266/* this function is called after Programm and Erase Operations to
267 * check for success or failure */
William Juulcfa460a2007-10-31 13:53:06 +0100268static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200269{
270 unsigned long ndsr=0, event=0;
William Juulcfa460a2007-10-31 13:53:06 +0100271 int state = this->state;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200272
273 if(state == FL_WRITING) {
274 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
275 } else if(state == FL_ERASING) {
276 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
277 }
278
279 ndsr = dfc_wait_event(event);
280
281 if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
282 return(0x1); /* Status Read error */
283 return 0;
284}
285
286/* cmdfunc send commands to the DFC */
287static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
288 int column, int page_addr)
289{
290 /* register struct nand_chip *this = mtd->priv; */
291 unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
292
293 /* clear the ugly byte read buffer */
294 bytes_read = -1;
295 read_buf = 0;
296
297 switch (command) {
298 case NAND_CMD_READ0:
299 DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
300 dfc_new_cmd();
301 ndcb0 = (NAND_CMD_READ0 | (4<<16));
302 column >>= 1; /* adjust for 16 bit bus */
303 ndcb1 = (((column>>1) & 0xff) |
304 ((page_addr<<8) & 0xff00) |
305 ((page_addr<<8) & 0xff0000) |
306 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
307 event = NDSR_RDDREQ;
308 goto write_cmd;
309 case NAND_CMD_READ1:
310 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
311 goto end;
312 case NAND_CMD_READOOB:
313 DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
314 goto end;
315 case NAND_CMD_READID:
316 dfc_new_cmd();
317 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
318 ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
319 event = NDSR_RDDREQ;
320 goto write_cmd;
321 case NAND_CMD_PAGEPROG:
322 /* sent as a multicommand in NAND_CMD_SEQIN */
323 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
324 goto end;
325 case NAND_CMD_ERASE1:
326 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
327 dfc_new_cmd();
328 ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
329 ndcb1 = (page_addr & 0x00ffffff);
330 goto write_cmd;
331 case NAND_CMD_ERASE2:
332 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
333 goto end;
334 case NAND_CMD_SEQIN:
335 /* send PAGE_PROG command(0x1080) */
336 dfc_new_cmd();
337 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
338 ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
339 column >>= 1; /* adjust for 16 bit bus */
340 ndcb1 = (((column>>1) & 0xff) |
341 ((page_addr<<8) & 0xff00) |
342 ((page_addr<<8) & 0xff0000) |
343 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
344 event = NDSR_WRDREQ;
345 goto write_cmd;
346 case NAND_CMD_STATUS:
347 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
348 dfc_new_cmd();
349 ndcb0 = NAND_CMD_STATUS | (4<<21);
350 event = NDSR_RDDREQ;
351 goto write_cmd;
352 case NAND_CMD_RESET:
353 DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
354 ndcb0 = NAND_CMD_RESET | (5<<21);
355 event = NDSR_CS0_CMDD;
356 goto write_cmd;
357 default:
358 printk("dfc_cmdfunc: error, unsupported command.\n");
359 goto end;
360 }
361
362 write_cmd:
363 NDCB0 = ndcb0;
364 NDCB0 = ndcb1;
365 NDCB0 = ndcb2;
366
367 /* wait_event: */
368 dfc_wait_event(event);
369 end:
370 return;
371}
372
373static void dfc_gpio_init(void)
374{
375 DFC_DEBUG2("Setting up DFC GPIO's.\n");
376
377 /* no idea what is done here, see zylonite.c */
378 GPIO4 = 0x1;
379
380 DF_ALE_WE1 = 0x00000001;
381 DF_ALE_WE2 = 0x00000001;
382 DF_nCS0 = 0x00000001;
383 DF_nCS1 = 0x00000001;
384 DF_nWE = 0x00000001;
385 DF_nRE = 0x00000001;
386 DF_IO0 = 0x00000001;
387 DF_IO8 = 0x00000001;
388 DF_IO1 = 0x00000001;
389 DF_IO9 = 0x00000001;
390 DF_IO2 = 0x00000001;
391 DF_IO10 = 0x00000001;
392 DF_IO3 = 0x00000001;
393 DF_IO11 = 0x00000001;
394 DF_IO4 = 0x00000001;
395 DF_IO12 = 0x00000001;
396 DF_IO5 = 0x00000001;
397 DF_IO13 = 0x00000001;
398 DF_IO6 = 0x00000001;
399 DF_IO14 = 0x00000001;
400 DF_IO7 = 0x00000001;
401 DF_IO15 = 0x00000001;
402
403 DF_nWE = 0x1901;
404 DF_nRE = 0x1901;
405 DF_CLE_NOE = 0x1900;
406 DF_ALE_WE1 = 0x1901;
407 DF_INT_RnB = 0x1900;
408}
409
410/*
411 * Board-specific NAND initialization. The following members of the
412 * argument are board-specific (per include/linux/mtd/nand_new.h):
413 * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
414 * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
William Juulcfa460a2007-10-31 13:53:06 +0100415 * - cmd_ctrl: hardwarespecific function for accesing control-lines
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200416 * - dev_ready: hardwarespecific function for accesing device ready/busy line
417 * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
418 * only be provided if a hardware ECC is available
William Juulcfa460a2007-10-31 13:53:06 +0100419 * - ecc.mode: mode of ecc, see defines
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200420 * - chip_delay: chip dependent delay for transfering data from array to
421 * read regs (tR)
422 * - options: various chip options. They can partly be set to inform
423 * nand_scan about special functionality. See the defines for further
424 * explanation
425 * Members with a "?" were not set in the merged testing-NAND branch,
426 * so they are not set here either.
427 */
Heiko Schocherfa230442006-12-21 17:17:02 +0100428int board_nand_init(struct nand_chip *nand)
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200429{
430 unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
431
432 /* set up GPIO Control Registers */
433 dfc_gpio_init();
434
435 /* turn on the NAND Controller Clock (104 MHz @ D0) */
436 CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
437
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#undef CONFIG_SYS_TIMING_TIGHT
439#ifndef CONFIG_SYS_TIMING_TIGHT
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200440 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
441 DFC_MAX_tCH);
442 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
443 DFC_MAX_tCS);
444 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
445 DFC_MAX_tWH);
446 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
447 DFC_MAX_tWP);
448 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
449 DFC_MAX_tRH);
450 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
451 DFC_MAX_tRP);
452 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
453 DFC_MAX_tR);
454 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
455 DFC_MAX_tWHR);
456 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
457 DFC_MAX_tAR);
458#else /* this is the tight timing */
459
460 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
461 DFC_MAX_tCH);
462 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
463 DFC_MAX_tCS);
464 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
465 DFC_MAX_tWH);
466 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
467 DFC_MAX_tWP);
468 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
469 DFC_MAX_tRH);
470 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
471 DFC_MAX_tRP);
472 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
473 DFC_MAX_tR);
474 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
475 DFC_MAX_tWHR);
476 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
477 DFC_MAX_tAR);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#endif /* CONFIG_SYS_TIMING_TIGHT */
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200479
480
481 DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
482
483 /* tRP value is split in the register */
484 if(tRP & (1 << 4)) {
485 tRP_high = 1;
486 tRP &= ~(1 << 4);
487 } else {
488 tRP_high = 0;
489 }
490
491 NDTR0CS0 = (tCH << 19) |
492 (tCS << 16) |
493 (tWH << 11) |
494 (tWP << 8) |
495 (tRP_high << 6) |
496 (tRH << 3) |
497 (tRP << 0);
498
499 NDTR1CS0 = (tR << 16) |
500 (tWHR << 4) |
501 (tAR << 0);
502
503 /* If it doesn't work (unlikely) think about:
504 * - ecc enable
505 * - chip select don't care
506 * - read id byte count
507 *
508 * Intentionally enabled by not setting bits:
509 * - dma (DMA_EN)
510 * - page size = 512
511 * - cs don't care, see if we can enable later!
512 * - row address start position (after second cycle)
513 * - pages per block = 32
514 * - ND_RDY : clears command buffer
515 */
516 /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
517
518 NDCR = (NDCR_SPARE_EN | /* use the spare area */
519 NDCR_DWIDTH_C | /* 16bit DFC data bus width */
520 NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
521 (2 << 16) | /* read id count = 7 ???? mk@tbd */
522 NDCR_ND_ARB_EN | /* enable bus arbiter */
523 NDCR_RDYM | /* flash device ready ir masked */
524 NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
525 NDCR_CS1_PAGEDM |
526 NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
527 NDCR_CS1_CMDDM |
528 NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
529 NDCR_CS1_BBDM |
530 NDCR_DBERRM | /* double bit error ir masked */
531 NDCR_SBERRM | /* single bit error ir masked */
532 NDCR_WRDREQM | /* write data request ir masked */
533 NDCR_RDDREQM | /* read data request ir masked */
534 NDCR_WRCMDREQM); /* write command request ir masked */
535
536
537 /* wait 10 us due to cmd buffer clear reset */
538 /* wait(10); */
539
William Juulcfa460a2007-10-31 13:53:06 +0100540 nand->cmd_ctrl = dfc_hwcontrol;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200541/* nand->dev_ready = dfc_device_ready; */
William Juulcfa460a2007-10-31 13:53:06 +0100542 nand->ecc.mode = NAND_ECC_SOFT;
Scott Wood66446412008-09-10 11:48:49 -0500543 nand->ecc.layout = &delta_oob;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200544 nand->options = NAND_BUSWIDTH_16;
545 nand->waitfunc = dfc_wait;
546 nand->read_byte = dfc_read_byte;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200547 nand->read_word = dfc_read_word;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200548 nand->read_buf = dfc_read_buf;
549 nand->write_buf = dfc_write_buf;
550
551 nand->cmdfunc = dfc_cmdfunc;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200552 nand->badblock_pattern = &delta_bbt_descr;
Heiko Schocherfa230442006-12-21 17:17:02 +0100553 return 0;
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200554}
555
Markus Klotzbuecher7c93b242006-04-25 16:48:48 +0200556#endif