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wdenkf12e5682003-07-07 20:07:54 +00001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2000-2008
wdenkf12e5682003-07-07 20:07:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
37#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42
43#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44
wdenkae3af052003-08-07 22:18:11 +000045#define CONFIG_BOOTCOUNT_LIMIT
wdenkf12e5682003-07-07 20:07:54 +000046
wdenkae3af052003-08-07 22:18:11 +000047#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf12e5682003-07-07 20:07:54 +000048
49#define CONFIG_BOARD_TYPES 1 /* support board types */
50
51#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010052 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkf12e5682003-07-07 20:07:54 +000053 "echo"
54
55#undef CONFIG_BOOTARGS
56
57#define CONFIG_EXTRA_ENV_SETTINGS \
58 "netdev=eth0\0" \
59 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010060 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf12e5682003-07-07 20:07:54 +000061 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "addip=setenv bootargs ${bootargs} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
64 ":${hostname}:${netdev}:off panic=1\0" \
wdenkf12e5682003-07-07 20:07:54 +000065 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010066 "bootm ${kernel_addr}\0" \
wdenkf12e5682003-07-07 20:07:54 +000067 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010068 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkf12e5682003-07-07 20:07:54 +000070 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020071 "hostname=TQM855M\0" \
72 "bootfile=TQM855M/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020073 "fdt_addr=40080000\0" \
74 "kernel_addr=400A0000\0" \
75 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020076 "u-boot=TQM855M/u-image.bin\0" \
77 "load=tftp 200000 ${u-boot}\0" \
78 "update=prot off 40000000 +${filesize};" \
79 "era 40000000 +${filesize};" \
80 "cp.b 200000 40000000 ${filesize};" \
81 "sete filesize;save\0" \
wdenkf12e5682003-07-07 20:07:54 +000082 ""
83#define CONFIG_BOOTCOMMAND "run flash_self"
84
85#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf12e5682003-07-07 20:07:54 +000087
88#undef CONFIG_WATCHDOG /* watchdog disabled */
89
90#define CONFIG_STATUS_LED 1 /* Status LED enabled */
91
92#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
93
wdenkd4ca31c2004-01-02 14:00:00 +000094/* enable I2C and select the hardware/software driver */
95#undef CONFIG_HARD_I2C /* I2C with hardware support */
96#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
99#define CONFIG_SYS_I2C_SLAVE 0xFE
wdenkd4ca31c2004-01-02 14:00:00 +0000100
101#ifdef CONFIG_SOFT_I2C
102/*
103 * Software (bit-bang) I2C driver configuration
104 */
105#define PB_SCL 0x00000020 /* PB 26 */
106#define PB_SDA 0x00000010 /* PB 27 */
107
108#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
109#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
110#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
111#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
112#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
113 else immr->im_cpm.cp_pbdat &= ~PB_SDA
114#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
115 else immr->im_cpm.cp_pbdat &= ~PB_SCL
116#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
117#endif /* CONFIG_SOFT_I2C */
118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
120#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
wdenkd4ca31c2004-01-02 14:00:00 +0000121#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
123#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
124#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
wdenkd4ca31c2004-01-02 14:00:00 +0000125#endif
126
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500127/*
128 * BOOTP options
129 */
130#define CONFIG_BOOTP_SUBNETMASK
131#define CONFIG_BOOTP_GATEWAY
132#define CONFIG_BOOTP_HOSTNAME
133#define CONFIG_BOOTP_BOOTPATH
134#define CONFIG_BOOTP_BOOTFILESIZE
135
wdenkf12e5682003-07-07 20:07:54 +0000136
137#define CONFIG_MAC_PARTITION
138#define CONFIG_DOS_PARTITION
139
140#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
141
wdenkf12e5682003-07-07 20:07:54 +0000142
Jon Loeliger26946902007-07-04 22:30:50 -0500143/*
144 * Command line configuration.
145 */
146#include <config_cmd_default.h>
147
148#define CONFIG_CMD_ASKENV
149#define CONFIG_CMD_DATE
150#define CONFIG_CMD_DHCP
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200151#define CONFIG_CMD_ELF
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100152#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500153#define CONFIG_CMD_EEPROM
154#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200155#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500156#define CONFIG_CMD_NFS
157#define CONFIG_CMD_SNTP
158
wdenkf12e5682003-07-07 20:07:54 +0000159
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200160#define CONFIG_NETCONSOLE
161
162
wdenkf12e5682003-07-07 20:07:54 +0000163/*
164 * Miscellaneous configurable options
165 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_LONGHELP /* undef to save memory */
167#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkf12e5682003-07-07 20:07:54 +0000168
Wolfgang Denk2751a952006-10-28 02:29:14 +0200169#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
171#ifdef CONFIG_SYS_HUSH_PARSER
172#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkf12e5682003-07-07 20:07:54 +0000173#endif
174
Jon Loeliger26946902007-07-04 22:30:50 -0500175#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000177#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000179#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
181#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
182#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
185#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf12e5682003-07-07 20:07:54 +0000186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf12e5682003-07-07 20:07:54 +0000188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkf12e5682003-07-07 20:07:54 +0000190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkf12e5682003-07-07 20:07:54 +0000192
193/*
194 * Low Level Configuration Settings
195 * (address mappings, register initial values, etc.)
196 * You should know what you are doing if you make changes here.
197 */
198/*-----------------------------------------------------------------------
199 * Internal Memory Mapped Register
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf12e5682003-07-07 20:07:54 +0000202
203/*-----------------------------------------------------------------------
204 * Definitions for initial stack pointer and data area (in DPRAM)
205 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
207#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
208#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
209#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
210#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf12e5682003-07-07 20:07:54 +0000211
212/*-----------------------------------------------------------------------
213 * Start addresses for the final memory configuration
214 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf12e5682003-07-07 20:07:54 +0000216 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_SDRAM_BASE 0x00000000
218#define CONFIG_SYS_FLASH_BASE 0x40000000
219#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
220#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
221#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf12e5682003-07-07 20:07:54 +0000222
223/*
224 * For booting Linux, the board info and command line data
225 * have to be in the first 8 MB of memory, since this is
226 * the maximum mapped by the Linux kernel during initialization.
227 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf12e5682003-07-07 20:07:54 +0000229
230/*-----------------------------------------------------------------------
231 * FLASH organization
232 */
wdenkf12e5682003-07-07 20:07:54 +0000233
Martin Krausee318d9e2007-09-27 11:10:08 +0200234/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200236#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
238#define CONFIG_SYS_FLASH_EMPTY_INFO
239#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
240#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
241#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkf12e5682003-07-07 20:07:54 +0000242
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200243#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200244#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
245#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
246#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
wdenkf12e5682003-07-07 20:07:54 +0000247
248/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200249#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
250#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf12e5682003-07-07 20:07:54 +0000251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200253
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200254#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
255
wdenkf12e5682003-07-07 20:07:54 +0000256/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200257 * Dynamic MTD partition support
258 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100259#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200260#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
261#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200262#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
263
264#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
265 "128k(dtb)," \
266 "1920k(kernel)," \
267 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200268 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200269
270/*-----------------------------------------------------------------------
wdenkf12e5682003-07-07 20:07:54 +0000271 * Hardware Information Block
272 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
274#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
275#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf12e5682003-07-07 20:07:54 +0000276
277/*-----------------------------------------------------------------------
278 * Cache Configuration
279 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500281#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf12e5682003-07-07 20:07:54 +0000283#endif
284
285/*-----------------------------------------------------------------------
286 * SYPCR - System Protection Control 11-9
287 * SYPCR can only be written once after reset!
288 *-----------------------------------------------------------------------
289 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
290 */
291#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf12e5682003-07-07 20:07:54 +0000293 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
294#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf12e5682003-07-07 20:07:54 +0000296#endif
297
298/*-----------------------------------------------------------------------
299 * SIUMCR - SIU Module Configuration 11-6
300 *-----------------------------------------------------------------------
301 * PCMCIA config., multi-function pin tri-state
302 */
303#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000305#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000307#endif /* CONFIG_CAN_DRIVER */
308
309/*-----------------------------------------------------------------------
310 * TBSCR - Time Base Status and Control 11-26
311 *-----------------------------------------------------------------------
312 * Clear Reference Interrupt Status, Timebase freezing enabled
313 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf12e5682003-07-07 20:07:54 +0000315
316/*-----------------------------------------------------------------------
317 * RTCSC - Real-Time Clock Status and Control Register 11-27
318 *-----------------------------------------------------------------------
319 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf12e5682003-07-07 20:07:54 +0000321
322/*-----------------------------------------------------------------------
323 * PISCR - Periodic Interrupt Status and Control 11-31
324 *-----------------------------------------------------------------------
325 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
326 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf12e5682003-07-07 20:07:54 +0000328
329/*-----------------------------------------------------------------------
330 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
331 *-----------------------------------------------------------------------
332 * Reset PLL lock status sticky bit, timer expired status bit and timer
333 * interrupt status bit
wdenkf12e5682003-07-07 20:07:54 +0000334 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf12e5682003-07-07 20:07:54 +0000336
337/*-----------------------------------------------------------------------
338 * SCCR - System Clock and reset Control Register 15-27
339 *-----------------------------------------------------------------------
340 * Set clock output, timebase and RTC source and divider,
341 * power management and some other internal clocks
342 */
343#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf12e5682003-07-07 20:07:54 +0000345 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
346 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000347
348/*-----------------------------------------------------------------------
349 * PCMCIA stuff
350 *-----------------------------------------------------------------------
351 *
352 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
354#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
355#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
356#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
357#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
358#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
359#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
360#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf12e5682003-07-07 20:07:54 +0000361
362/*-----------------------------------------------------------------------
363 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
364 *-----------------------------------------------------------------------
365 */
366
367#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
368
369#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
370#undef CONFIG_IDE_LED /* LED for ide not supported */
371#undef CONFIG_IDE_RESET /* reset for ide not supported */
372
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
374#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf12e5682003-07-07 20:07:54 +0000375
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf12e5682003-07-07 20:07:54 +0000377
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf12e5682003-07-07 20:07:54 +0000379
380/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000382
383/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000385
386/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf12e5682003-07-07 20:07:54 +0000388
389/*-----------------------------------------------------------------------
390 *
391 *-----------------------------------------------------------------------
392 *
393 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_DER 0
wdenkf12e5682003-07-07 20:07:54 +0000395
396/*
397 * Init Memory Controller:
398 *
399 * BR0/1 and OR0/1 (FLASH)
400 */
401
402#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
403#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
404
405/* used to re-map FLASH both when starting from SRAM or FLASH:
406 * restrict access enough to keep SRAM working (if any)
407 * but not too much to meddle with FLASH accesses
408 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
410#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf12e5682003-07-07 20:07:54 +0000411
412/*
413 * FLASH timing:
414 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf12e5682003-07-07 20:07:54 +0000416 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf12e5682003-07-07 20:07:54 +0000417
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
419#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
420#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000421
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
423#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
424#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000425
426/*
427 * BR2/3 and OR2/3 (SDRAM)
428 *
429 */
430#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
431#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
432#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
433
434/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf12e5682003-07-07 20:07:54 +0000436
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
438#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000439
440#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
442#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000443#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
445#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
446#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
447#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf12e5682003-07-07 20:07:54 +0000448 BR_PS_8 | BR_MS_UPMB | BR_V )
449#endif /* CONFIG_CAN_DRIVER */
450
451/*
452 * Memory Periodic Timer Prescaler
453 *
454 * The Divider for PTA (refresh timer) configuration is based on an
455 * example SDRAM configuration (64 MBit, one bank). The adjustment to
456 * the number of chip selects (NCS) and the actually needed refresh
457 * rate is done by setting MPTPR.
458 *
459 * PTA is calculated from
460 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
461 *
462 * gclk CPU clock (not bus clock!)
463 * Trefresh Refresh cycle * 4 (four word bursts used)
464 *
465 * 4096 Rows from SDRAM example configuration
466 * 1000 factor s -> ms
467 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
468 * 4 Number of refresh cycles per period
469 * 64 Refresh cycle in ms per number of rows
470 * --------------------------------------------
471 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
472 *
473 * 50 MHz => 50.000.000 / Divider = 98
474 * 66 Mhz => 66.000.000 / Divider = 129
475 * 80 Mhz => 80.000.000 / Divider = 156
476 */
wdenke9132ea2004-04-24 23:23:30 +0000477
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
479#define CONFIG_SYS_MAMR_PTA 98
wdenkf12e5682003-07-07 20:07:54 +0000480
481/*
482 * For 16 MBit, refresh rates could be 31.3 us
483 * (= 64 ms / 2K = 125 / quad bursts).
484 * For a simpler initialization, 15.6 us is used instead.
485 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
487 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf12e5682003-07-07 20:07:54 +0000488 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
490#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000491
492/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
494#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000495
496/*
497 * MAMR settings for SDRAM
498 */
499
500/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000502 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
503 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
504/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200505#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000506 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
507 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
508
509
510/*
511 * Internal Definitions
512 *
513 * Boot Flags
514 */
515#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
516#define BOOTFLAG_WARM 0x02 /* Software reboot */
517
518#define CONFIG_SCC1_ENET
519#define CONFIG_FEC_ENET
520#define CONFIG_ETHPRIME "SCC ETHERNET"
521
522#endif /* __CONFIG_H */