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stroesea20b27a2004-12-16 18:05:42 +00001/*
2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
stroesea20b27a2004-12-16 18:05:42 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_405GP 1 /* This is a PPC405 CPU */
21#define CONFIG_4xx 1 /* ...member of PPC4xx family */
22#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
23#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
24
Wolfgang Denk2ae18242010-10-06 09:05:45 +020025#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
26
stroesea20b27a2004-12-16 18:05:42 +000027#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
Peter Tyser3a8f28d2009-09-16 22:03:07 -050028#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroesea20b27a2004-12-16 18:05:42 +000029
30#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
31
32#define CONFIG_BAUDRATE 9600
33#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
34
35#undef CONFIG_BOOTARGS
36#undef CONFIG_BOOTCOMMAND
37
38#define CONFIG_PREBOOT /* enable preboot variable */
39
40#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroesea20b27a2004-12-16 18:05:42 +000042
Ben Warren96e21f82008-10-27 23:50:15 -070043#define CONFIG_PPC4xx_EMAC
stroesea20b27a2004-12-16 18:05:42 +000044#define CONFIG_MII 1 /* MII PHY management */
45#define CONFIG_PHY_ADDR 0 /* PHY address */
46#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchs6f35c532007-06-24 17:41:21 +020047#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
48
Matthias Fuchs6f35c532007-06-24 17:41:21 +020049#undef CONFIG_HAS_ETH1
stroesea20b27a2004-12-16 18:05:42 +000050
51#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
52
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050053/*
54 * BOOTP options
55 */
56#define CONFIG_BOOTP_SUBNETMASK
57#define CONFIG_BOOTP_GATEWAY
58#define CONFIG_BOOTP_HOSTNAME
59#define CONFIG_BOOTP_BOOTPATH
60#define CONFIG_BOOTP_DNS
61#define CONFIG_BOOTP_DNS2
62#define CONFIG_BOOTP_SEND_HOSTNAME
stroesea20b27a2004-12-16 18:05:42 +000063
stroesea20b27a2004-12-16 18:05:42 +000064
Jon Loeliger49cf7e82007-07-05 19:52:35 -050065/*
66 * Command line configuration.
67 */
68#include <config_cmd_default.h>
69
70#define CONFIG_CMD_DHCP
71#define CONFIG_CMD_PCI
72#define CONFIG_CMD_IRQ
73#define CONFIG_CMD_IDE
74#define CONFIG_CMD_FAT
75#define CONFIG_CMD_ELF
76#define CONFIG_CMD_DATE
Jon Loeliger49cf7e82007-07-05 19:52:35 -050077#define CONFIG_CMD_I2C
78#define CONFIG_CMD_MII
79#define CONFIG_CMD_PING
80#define CONFIG_CMD_BSP
81#define CONFIG_CMD_EEPROM
82
stroesea20b27a2004-12-16 18:05:42 +000083#define CONFIG_MAC_PARTITION
84#define CONFIG_DOS_PARTITION
85
86#define CONFIG_SUPPORT_VFAT
87
88#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */
89
stroesea20b27a2004-12-16 18:05:42 +000090#undef CONFIG_WATCHDOG /* watchdog disabled */
91
92#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
93
94/*
95 * Miscellaneous configurable options
96 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_LONGHELP /* undef to save memory */
98#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
stroesea20b27a2004-12-16 18:05:42 +000099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
stroesea20b27a2004-12-16 18:05:42 +0000101
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500102#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000104#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000106#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
108#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
109#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroesea20b27a2004-12-16 18:05:42 +0000112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroesea20b27a2004-12-16 18:05:42 +0000114
115#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
118#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroesea20b27a2004-12-16 18:05:42 +0000119
Stefan Roese550650d2010-09-20 16:05:31 +0200120#define CONFIG_CONS_INDEX 1 /* Use UART0 */
121#define CONFIG_SYS_NS16550
122#define CONFIG_SYS_NS16550_SERIAL
123#define CONFIG_SYS_NS16550_REG_SIZE 1
124#define CONFIG_SYS_NS16550_CLK get_serial_clock()
125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_BASE_BAUD 691200
stroesea20b27a2004-12-16 18:05:42 +0000128
129/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_BAUDRATE_TABLE \
stroesea20b27a2004-12-16 18:05:42 +0000131 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
132 57600, 115200, 230400, 460800, 921600 }
133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
135#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroesea20b27a2004-12-16 18:05:42 +0000136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
stroesea20b27a2004-12-16 18:05:42 +0000138
139#define CONFIG_LOOPW 1 /* enable loopw command */
140
141#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
142
143/* Only interrupt boot if special string is typed */
Stefan Roesef2302d42008-08-06 14:05:38 +0200144#define CONFIG_AUTOBOOT_KEYED 1
145#define CONFIG_AUTOBOOT_PROMPT \
146 "Autobooting in %d seconds\n", bootdelay
stroesea20b27a2004-12-16 18:05:42 +0000147#undef CONFIG_AUTOBOOT_DELAY_STR
148#undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */
149#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/
150
151#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroesea20b27a2004-12-16 18:05:42 +0000154
155/*-----------------------------------------------------------------------
156 * PCI stuff
157 *-----------------------------------------------------------------------
158 */
159#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
160#define PCI_HOST_FORCE 1 /* configure as pci host */
161#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
162
163#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000164#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
stroesea20b27a2004-12-16 18:05:42 +0000165#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
166#define CONFIG_PCI_PNP /* do pci plug-and-play */
167 /* resource configuration */
168
169#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
170
171#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
172
173#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
176#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
177#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
178#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
179#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
180#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
181#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
182#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
183#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
Matthias Fuchs468ebf12012-11-02 14:30:34 +0100184#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
stroesea20b27a2004-12-16 18:05:42 +0000185
Matthias Fuchs82379b52009-09-07 17:00:41 +0200186#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
187
stroesea20b27a2004-12-16 18:05:42 +0000188/*-----------------------------------------------------------------------
189 * IDE/ATA stuff
190 *-----------------------------------------------------------------------
191 */
192#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
193#undef CONFIG_IDE_LED /* no led for ide supported */
194#define CONFIG_IDE_RESET 1 /* reset for ide supported */
195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
197#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
stroesea20b27a2004-12-16 18:05:42 +0000198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
200#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
stroesea20b27a2004-12-16 18:05:42 +0000201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
203#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
204#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
stroesea20b27a2004-12-16 18:05:42 +0000205
206/*-----------------------------------------------------------------------
207 * Start addresses for the final memory configuration
208 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroesea20b27a2004-12-16 18:05:42 +0000210 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_SDRAM_BASE 0x00000000
212#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
213#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
214#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
215#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
stroesea20b27a2004-12-16 18:05:42 +0000216
217/*
218 * For booting Linux, the board info and command line data
219 * have to be in the first 8 MB of memory, since this is
220 * the maximum mapped by the Linux kernel during initialization.
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
stroesea20b27a2004-12-16 18:05:42 +0000223/*-----------------------------------------------------------------------
224 * FLASH organization
225 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
227#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
stroesea20b27a2004-12-16 18:05:42 +0000228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
230#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
stroesea20b27a2004-12-16 18:05:42 +0000231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
233#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
234#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroesea20b27a2004-12-16 18:05:42 +0000235/*
236 * The following defines are added for buggy IOP480 byte interface.
237 * All other boards should use the standard values (CPCI405 etc.)
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
240#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
241#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
stroesea20b27a2004-12-16 18:05:42 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroesea20b27a2004-12-16 18:05:42 +0000244
stroesea20b27a2004-12-16 18:05:42 +0000245#if 0 /* Use NVRAM for environment variables */
246/*-----------------------------------------------------------------------
247 * NVRAM organization
248 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200249#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200250#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
251#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
stroesea20b27a2004-12-16 18:05:42 +0000253
254#else /* Use EEPROM for environment variables */
255
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200256#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200257#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
258#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
stroesea20b27a2004-12-16 18:05:42 +0000259 /* total size of a CAT24WC16 is 2048 bytes */
260#endif
261
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
263#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
264#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
stroesea20b27a2004-12-16 18:05:42 +0000265
266/*-----------------------------------------------------------------------
267 * I2C EEPROM (CAT24WC16) for environment
268 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000269#define CONFIG_SYS_I2C
270#define CONFIG_SYS_I2C_PPC4XX
271#define CONFIG_SYS_I2C_PPC4XX_CH0
272#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
273#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
stroesea20b27a2004-12-16 18:05:42 +0000274
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
276#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
stroesea20b27a2004-12-16 18:05:42 +0000277/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
279#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
stroesea20b27a2004-12-16 18:05:42 +0000280 /* 16 byte page write mode using*/
281 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroesea20b27a2004-12-16 18:05:42 +0000283
stroesea20b27a2004-12-16 18:05:42 +0000284/*
285 * Init Memory Controller:
286 *
287 * BR0/1 and OR0/1 (FLASH)
288 */
289
290#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
291#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
292
293/*-----------------------------------------------------------------------
294 * External Bus Controller (EBC) Setup
295 */
296
297/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_EBC_PB0AP 0x92015480
299#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000300
301/* Memory Bank 1 (Flash Bank 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_EBC_PB1AP 0x92015480
303#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000304
305/* Memory Bank 2 (CAN0, 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
307#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
308#define CONFIG_SYS_LED_ADDR 0xF0000380
stroesea20b27a2004-12-16 18:05:42 +0000309
310/* Memory Bank 3 (CompactFlash IDE) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
312#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000313
314/* Memory Bank 4 (NVRAM/RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
316#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
317#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
stroesea20b27a2004-12-16 18:05:42 +0000318
319/* Memory Bank 5 (optional Quart) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
321#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
stroesea20b27a2004-12-16 18:05:42 +0000322
323/* Memory Bank 6 (FPGA internal) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
325#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
326#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
stroesea20b27a2004-12-16 18:05:42 +0000327
328/*-----------------------------------------------------------------------
329 * FPGA stuff
330 */
331/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_FPGA_MODE 0x00
333#define CONFIG_SYS_FPGA_STATUS 0x02
334#define CONFIG_SYS_FPGA_TS 0x04
335#define CONFIG_SYS_FPGA_TS_LOW 0x06
336#define CONFIG_SYS_FPGA_TS_CAP0 0x10
337#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
338#define CONFIG_SYS_FPGA_TS_CAP1 0x14
339#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
340#define CONFIG_SYS_FPGA_TS_CAP2 0x18
341#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
342#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
343#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
stroesea20b27a2004-12-16 18:05:42 +0000344
345/* FPGA Mode Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
347#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
348#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
349#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
350#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
351#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
stroesea20b27a2004-12-16 18:05:42 +0000352
353/* FPGA Status Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
355#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
356#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
357#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
358#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
stroesea20b27a2004-12-16 18:05:42 +0000359
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
361#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
stroesea20b27a2004-12-16 18:05:42 +0000362
363/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
365#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
366#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
367#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
368#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroesea20b27a2004-12-16 18:05:42 +0000369
370/*-----------------------------------------------------------------------
371 * Definitions for initial stack pointer and data area (in data cache)
372 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
stroesea20b27a2004-12-16 18:05:42 +0000374
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200376#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200377#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroesea20b27a2004-12-16 18:05:42 +0000379
stroesea20b27a2004-12-16 18:05:42 +0000380#endif /* __CONFIG_H */