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wdenkc6097192002-11-03 00:24:07 +00001/*
Stefan Roese4fb25a32008-06-25 10:59:22 +02002 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
wdenkc6097192002-11-03 00:24:07 +00003 *
Stefan Roese952e7762009-09-24 09:55:50 +02004 * (C) Copyright 2008-2009
Stefan Roese4fb25a32008-06-25 10:59:22 +02005 * Stefan Roese, DENX Software Engineering, sr@denx.de.
wdenkc6097192002-11-03 00:24:07 +00006 *
Stefan Roese4fb25a32008-06-25 10:59:22 +02007 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
wdenkc6097192002-11-03 00:24:07 +000024 */
25
Stefan Roese4fb25a32008-06-25 10:59:22 +020026#ifndef _PPC4xx_UIC_H_
27#define _PPC4xx_UIC_H_
wdenkc6097192002-11-03 00:24:07 +000028
Stefan Roesed1631fe2008-06-26 13:40:57 +020029/*
30 * Define the number of UIC's
31 */
Stefan Roese5de85142008-06-26 17:36:39 +020032#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
Stefan Roese3a821132008-07-10 16:37:09 +020033 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Tirumala Marri1b8fec12010-09-28 14:15:14 -070034 defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
Stefan Roesed1631fe2008-06-26 13:40:57 +020035#define UIC_MAX 4
Stefan Roese5de85142008-06-26 17:36:39 +020036#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesed1631fe2008-06-26 13:40:57 +020037 defined(CONFIG_405EX)
38#define UIC_MAX 3
39#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
40 defined(CONFIG_440EP) || defined(CONFIG_440GR)
41#define UIC_MAX 2
42#else
43#define UIC_MAX 1
44#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +020045
Stefan Roese952e7762009-09-24 09:55:50 +020046#define IRQ_MAX (UIC_MAX * 32)
Ricardo Ribalda Delgadod865fd02008-07-17 11:44:12 +020047
Stefan Roesed1631fe2008-06-26 13:40:57 +020048/*
49 * UIC register
50 */
51#define UIC_SR 0x0 /* UIC status */
52#define UIC_ER 0x2 /* UIC enable */
53#define UIC_CR 0x3 /* UIC critical */
54#define UIC_PR 0x4 /* UIC polarity */
55#define UIC_TR 0x5 /* UIC triggering */
56#define UIC_MSR 0x6 /* UIC masked status */
57#define UIC_VR 0x7 /* UIC vector */
58#define UIC_VCR 0x8 /* UIC vector configuration */
Stefan Roese887e2ec2006-09-07 11:51:23 +020059
Stefan Roese5de85142008-06-26 17:36:39 +020060/*
61 * On 440GX we use the UICB0 as UIC0. Its the root UIC where all other UIC's
62 * are cascaded on. With this trick we can use the common UIC code for 440GX
63 * too.
64 */
65#if defined(CONFIG_440GX)
66#define UIC0_DCR_BASE 0x200
67#define UIC1_DCR_BASE 0xc0
68#define UIC2_DCR_BASE 0xd0
69#define UIC3_DCR_BASE 0x210
70#else
Stefan Roesed1631fe2008-06-26 13:40:57 +020071#define UIC0_DCR_BASE 0xc0
Stefan Roese5de85142008-06-26 17:36:39 +020072#define UIC1_DCR_BASE 0xd0
73#define UIC2_DCR_BASE 0xe0
74#define UIC3_DCR_BASE 0xf0
75#endif
76
Stefan Roese952e7762009-09-24 09:55:50 +020077#define UIC0SR (UIC0_DCR_BASE+0x0) /* UIC0 status */
78#define UIC0ER (UIC0_DCR_BASE+0x2) /* UIC0 enable */
79#define UIC0CR (UIC0_DCR_BASE+0x3) /* UIC0 critical */
80#define UIC0PR (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
81#define UIC0TR (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
82#define UIC0MSR (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
83#define UIC0VR (UIC0_DCR_BASE+0x7) /* UIC0 vector */
84#define UIC0VCR (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
Stefan Roese887e2ec2006-09-07 11:51:23 +020085
Stefan Roese952e7762009-09-24 09:55:50 +020086#define UIC1SR (UIC1_DCR_BASE+0x0) /* UIC1 status */
87#define UIC1ER (UIC1_DCR_BASE+0x2) /* UIC1 enable */
88#define UIC1CR (UIC1_DCR_BASE+0x3) /* UIC1 critical */
89#define UIC1PR (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
90#define UIC1TR (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
91#define UIC1MSR (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
92#define UIC1VR (UIC1_DCR_BASE+0x7) /* UIC1 vector */
93#define UIC1VCR (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
Stefan Roese887e2ec2006-09-07 11:51:23 +020094
Stefan Roese952e7762009-09-24 09:55:50 +020095#define UIC2SR (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
96#define UIC2ER (UIC2_DCR_BASE+0x2) /* UIC2 enable */
97#define UIC2CR (UIC2_DCR_BASE+0x3) /* UIC2 critical */
98#define UIC2PR (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
99#define UIC2TR (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
100#define UIC2MSR (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
101#define UIC2VR (UIC2_DCR_BASE+0x7) /* UIC2 vector */
102#define UIC2VCR (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200103
Stefan Roese952e7762009-09-24 09:55:50 +0200104#define UIC3SR (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
105#define UIC3ER (UIC3_DCR_BASE+0x2) /* UIC3 enable */
106#define UIC3CR (UIC3_DCR_BASE+0x3) /* UIC3 critical */
107#define UIC3PR (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
108#define UIC3TR (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
109#define UIC3MSR (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
110#define UIC3VR (UIC3_DCR_BASE+0x7) /* UIC3 vector */
111#define UIC3VCR (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
Stefan Roese999ecd52008-03-11 15:07:10 +0100112
Stefan Roesed1631fe2008-06-26 13:40:57 +0200113/*
114 * Now the interrupt vector definitions. They are different for most of
115 * the 4xx variants, so we need some more #ifdef's here. No mask
116 * definitions anymore here. For this please use the UIC_MASK macro below.
117 *
118 * Note: Please only define the interrupts really used in U-Boot here.
119 * Those are the cascading and EMAC/MAL related interrupt.
120 */
Stefan Roese999ecd52008-03-11 15:07:10 +0100121
Stefan Roesed1631fe2008-06-26 13:40:57 +0200122#if defined(CONFIG_405EP) || defined(CONFIG_405GP)
123#define VECNUM_MAL_SERR 10
124#define VECNUM_MAL_TXEOB 11
125#define VECNUM_MAL_RXEOB 12
126#define VECNUM_MAL_TXDE 13
127#define VECNUM_MAL_RXDE 14
128#define VECNUM_ETH0 15
129#define VECNUM_ETH1_OFFS 2
130#define VECNUM_EIRQ6 29
131#endif /* defined(CONFIG_405EP) */
wdenkc6097192002-11-03 00:24:07 +0000132
Stefan Roesee01bd212007-03-21 13:38:59 +0100133#if defined(CONFIG_405EZ)
Stefan Roesed1631fe2008-06-26 13:40:57 +0200134#define VECNUM_USBDEV 15
135#define VECNUM_ETH0 16
136#define VECNUM_MAL_SERR 18
137#define VECNUM_MAL_TXDE 18
138#define VECNUM_MAL_RXDE 18
139#define VECNUM_MAL_TXEOB 19
140#define VECNUM_MAL_RXEOB 21
141#endif /* CONFIG_405EX */
Stefan Roesee01bd212007-03-21 13:38:59 +0100142
Stefan Roesed1631fe2008-06-26 13:40:57 +0200143#if defined(CONFIG_405EX)
Stefan Roesedbbd1252007-10-05 17:10:59 +0200144/* UIC 0 */
Stefan Roesed1631fe2008-06-26 13:40:57 +0200145#define VECNUM_MAL_TXEOB 10
146#define VECNUM_MAL_RXEOB 11
Stefan Roesedbbd1252007-10-05 17:10:59 +0200147#define VECNUM_ETH0 24
Stefan Roesed1631fe2008-06-26 13:40:57 +0200148#define VECNUM_ETH1_OFFS 1
149#define VECNUM_UIC2NCI 28
150#define VECNUM_UIC2CI 29
151#define VECNUM_UIC1NCI 30
152#define VECNUM_UIC1CI 31
Stefan Roesedbbd1252007-10-05 17:10:59 +0200153
154/* UIC 1 */
Stefan Roesed1631fe2008-06-26 13:40:57 +0200155#define VECNUM_MAL_SERR (32 + 0)
156#define VECNUM_MAL_TXDE (32 + 1)
157#define VECNUM_MAL_RXDE (32 + 2)
158#endif /* CONFIG_405EX */
159
160#if defined(CONFIG_440GP) || \
161 defined(CONFIG_440EP) || defined(CONFIG_440GR)
162/* UIC 0 */
163#define VECNUM_MAL_TXEOB 10
164#define VECNUM_MAL_RXEOB 11
165#define VECNUM_UIC1NCI 30
166#define VECNUM_UIC1CI 31
167
168/* UIC 1 */
169#define VECNUM_MAL_SERR (32 + 0)
170#define VECNUM_MAL_TXDE (32 + 1)
171#define VECNUM_MAL_RXDE (32 + 2)
172#define VECNUM_USBDEV (32 + 23)
173#define VECNUM_ETH0 (32 + 28)
174#define VECNUM_ETH1_OFFS 2
175#endif /* CONFIG_440GP */
176
177#if defined(CONFIG_440GX)
Stefan Roesed1631fe2008-06-26 13:40:57 +0200178/* UICB 0 (440GX only) */
Stefan Roese5de85142008-06-26 17:36:39 +0200179/*
180 * All those defines below are off-by-one, so that the common UIC code
181 * can be used. So VECNUM_UIC1CI refers to VECNUM_UIC0CI etc.
182 */
183#define VECNUM_UIC1CI 0
184#define VECNUM_UIC1NCI 1
185#define VECNUM_UIC2CI 2
186#define VECNUM_UIC2NCI 3
187#define VECNUM_UIC3CI 4
188#define VECNUM_UIC3NCI 5
189
190/* UIC 0, used as UIC1 on 440GX because of UICB0 */
191#define VECNUM_MAL_TXEOB (32 + 10)
192#define VECNUM_MAL_RXEOB (32 + 11)
193
194/* UIC 1, used as UIC2 on 440GX because of UICB0 */
195#define VECNUM_MAL_SERR (64 + 0)
196#define VECNUM_MAL_TXDE (64 + 1)
197#define VECNUM_MAL_RXDE (64 + 2)
198#define VECNUM_ETH0 (64 + 28)
199#define VECNUM_ETH1_OFFS 2
Stefan Roesed1631fe2008-06-26 13:40:57 +0200200#endif /* CONFIG_440GX */
201
202#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
203/* UIC 0 */
204#define VECNUM_MAL_TXEOB 10
205#define VECNUM_MAL_RXEOB 11
206#define VECNUM_USBDEV 20
207#define VECNUM_ETH0 24
208#define VECNUM_ETH1_OFFS 1
209#define VECNUM_UIC2NCI 28
210#define VECNUM_UIC2CI 29
211#define VECNUM_UIC1NCI 30
212#define VECNUM_UIC1CI 31
213
214/* UIC 1 */
215#define VECNUM_MAL_SERR (32 + 0)
216#define VECNUM_MAL_TXDE (32 + 1)
217#define VECNUM_MAL_RXDE (32 + 2)
Stefan Roesedbbd1252007-10-05 17:10:59 +0200218
219/* UIC 2 */
Stefan Roesed1631fe2008-06-26 13:40:57 +0200220#define VECNUM_EIRQ2 (64 + 3)
221#endif /* CONFIG_440EPX */
Stefan Roesedbbd1252007-10-05 17:10:59 +0200222
Stefan Roesed1631fe2008-06-26 13:40:57 +0200223#if defined(CONFIG_440SP)
224/* UIC 0 */
225#define VECNUM_UIC1NCI 30
226#define VECNUM_UIC1CI 31
Stefan Roesee01bd212007-03-21 13:38:59 +0100227
Stefan Roesed1631fe2008-06-26 13:40:57 +0200228/* UIC 1 */
229#define VECNUM_MAL_SERR (32 + 1)
230#define VECNUM_MAL_TXDE (32 + 2)
231#define VECNUM_MAL_RXDE (32 + 3)
232#define VECNUM_MAL_TXEOB (32 + 6)
233#define VECNUM_MAL_RXEOB (32 + 7)
234#define VECNUM_ETH0 (32 + 28)
235#endif /* CONFIG_440SP */
wdenkc6097192002-11-03 00:24:07 +0000236
Stefan Roesed1631fe2008-06-26 13:40:57 +0200237#if defined(CONFIG_440SPE)
238/* UIC 0 */
239#define VECNUM_UIC2NCI 10
240#define VECNUM_UIC2CI 11
241#define VECNUM_UIC3NCI 16
242#define VECNUM_UIC3CI 17
243#define VECNUM_UIC1NCI 30
244#define VECNUM_UIC1CI 31
245
246/* UIC 1 */
247#define VECNUM_MAL_SERR (32 + 1)
248#define VECNUM_MAL_TXDE (32 + 2)
249#define VECNUM_MAL_RXDE (32 + 3)
250#define VECNUM_MAL_TXEOB (32 + 6)
251#define VECNUM_MAL_RXEOB (32 + 7)
252#define VECNUM_ETH0 (32 + 28)
253#endif /* CONFIG_440SPE */
254
Tirumala Marri1b8fec12010-09-28 14:15:14 -0700255#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
256 defined(CONFIG_APM821XX)
Stefan Roesed1631fe2008-06-26 13:40:57 +0200257/* UIC 0 */
258#define VECNUM_UIC2NCI 10
259#define VECNUM_UIC2CI 11
260#define VECNUM_UIC3NCI 16
261#define VECNUM_UIC3CI 17
262#define VECNUM_UIC1NCI 30
263#define VECNUM_UIC1CI 31
264
265/* UIC 2 */
266#define VECNUM_MAL_SERR (64 + 3)
267#define VECNUM_MAL_TXDE (64 + 4)
268#define VECNUM_MAL_RXDE (64 + 5)
269#define VECNUM_MAL_TXEOB (64 + 6)
270#define VECNUM_MAL_RXEOB (64 + 7)
271#define VECNUM_ETH0 (64 + 16)
272#define VECNUM_ETH1_OFFS 1
273#endif /* CONFIG_460EX */
274
Stefan Roese3a821132008-07-10 16:37:09 +0200275#if defined(CONFIG_460SX)
276/* UIC 0 */
277#define VECNUM_UIC2NCI 10
278#define VECNUM_UIC2CI 11
279#define VECNUM_UIC3NCI 16
280#define VECNUM_UIC3CI 17
281#define VECNUM_ETH0 19
282#define VECNUM_ETH1_OFFS 1
283#define VECNUM_UIC1NCI 30
284#define VECNUM_UIC1CI 31
285
286/* UIC 1 */
287#define VECNUM_MAL_SERR (32 + 1)
288#define VECNUM_MAL_TXDE (32 + 2)
289#define VECNUM_MAL_RXDE (32 + 3)
290#define VECNUM_MAL_TXEOB (32 + 6)
291#define VECNUM_MAL_RXEOB (32 + 7)
292#endif /* CONFIG_460EX */
293
Stefan Roesed1631fe2008-06-26 13:40:57 +0200294#if !defined(VECNUM_ETH1_OFFS)
295#define VECNUM_ETH1_OFFS 1
296#endif
297
298/*
299 * Mask definitions (used for example in 4xx_enet.c)
300 */
301#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f))
Stefan Roese5de85142008-06-26 17:36:39 +0200302/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */
Stefan Roesed1631fe2008-06-26 13:40:57 +0200303#define UIC_NR(vec) ((vec) >> 5)
wdenkc6097192002-11-03 00:24:07 +0000304
Stefan Roese4fb25a32008-06-25 10:59:22 +0200305#endif /* _PPC4xx_UIC_H_ */