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Simon Glass2444dae2015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stübner041cdb52016-07-16 00:17:15 +02003config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
Lokesh Vutlaacf15002018-04-26 18:21:26 +05305 select CPU_V7A
Kever Yanga381bcf2016-07-19 21:16:59 +08006 select SUPPORT_SPL
7 select SPL
Eddie Cai451dcf52018-01-17 09:51:41 +08008 imply USB_FUNCTION_ROCKUSB
9 imply CMD_ROCKUSB
Heiko Stübner041cdb52016-07-16 00:17:15 +020010 help
11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
13 and video codec support. Peripherals include Gigabit Ethernet,
14 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
15
Kever Yangdaeed1d2017-11-28 16:04:16 +080016config ROCKCHIP_RK3128
17 bool "Support Rockchip RK3128"
Lokesh Vutlaacf15002018-04-26 18:21:26 +053018 select CPU_V7A
Kever Yangdaeed1d2017-11-28 16:04:16 +080019 help
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
22 and video codec support. Peripherals include Gigabit Ethernet,
23 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
Heiko Stübner0a2be692017-02-18 19:46:36 +010025config ROCKCHIP_RK3188
26 bool "Support Rockchip RK3188"
Lokesh Vutlaacf15002018-04-26 18:21:26 +053027 select CPU_V7A
Ley Foon Tan0680f1b2017-05-03 17:13:32 +080028 select SPL_BOARD_INIT if SPL
Heiko Stübner0a2be692017-02-18 19:46:36 +010029 select SUPPORT_SPL
Heiko Stübner0a2be692017-02-18 19:46:36 +010030 select SPL
Philipp Tomsich4bbb05b2017-10-10 16:21:17 +020031 select SPL_CLK
32 select SPL_PINCTRL
33 select SPL_REGMAP
34 select SPL_SYSCON
35 select SPL_RAM
36 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich4d9253f2017-10-10 16:21:15 +020037 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Heiko Stübner008a6102017-04-06 00:19:36 +020038 select BOARD_LATE_INIT
Heiko Stübner0a2be692017-02-18 19:46:36 +010039 select ROCKCHIP_BROM_HELPER
40 help
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
43 video interfaces, several memory options and video codec support.
44 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
45 UART, SPI, I2C and PWMs.
46
Kever Yang168eef72017-06-23 17:17:52 +080047config ROCKCHIP_RK322X
48 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutlaacf15002018-04-26 18:21:26 +053049 select CPU_V7A
Kever Yang168eef72017-06-23 17:17:52 +080050 select SUPPORT_SPL
51 select SPL
52 select ROCKCHIP_BROM_HELPER
53 select DEBUG_UART_BOARD_INIT
54 help
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
57 and video codec support. Peripherals include Gigabit Ethernet,
58 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
59
Simon Glass2444dae2015-08-30 16:55:38 -060060config ROCKCHIP_RK3288
61 bool "Support Rockchip RK3288"
Lokesh Vutlaacf15002018-04-26 18:21:26 +053062 select CPU_V7A
Ley Foon Tan0680f1b2017-05-03 17:13:32 +080063 select SPL_BOARD_INIT if SPL
Kever Yanga381bcf2016-07-19 21:16:59 +080064 select SUPPORT_SPL
65 select SPL
Eddie Caic3d098e2017-12-15 08:17:13 +080066 imply USB_FUNCTION_ROCKUSB
67 imply CMD_ROCKUSB
Simon Glass2444dae2015-08-30 16:55:38 -060068 help
69 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
70 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
71 video interfaces supporting HDMI and eDP, several DDR3 options
72 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färberef904bf2016-11-02 18:03:01 +010073 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2444dae2015-08-30 16:55:38 -060074
Jagan Teki849f6722018-02-23 13:13:10 +053075if ROCKCHIP_RK3288
76
77config TPL_LDSCRIPT
78 default "arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds"
79
Jagan Teki33554fc2018-02-23 13:13:11 +053080config TPL_TEXT_BASE
81 default 0xff704000
82
Jagan Teki849f6722018-02-23 13:13:10 +053083endif
84
Kever Yang85a3cfb2017-02-23 15:37:51 +080085config ROCKCHIP_RK3328
86 bool "Support Rockchip RK3328"
87 select ARM64
88 help
89 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
90 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
91 video interfaces supporting HDMI and eDP, several DDR3 options
92 and video codec support. Peripherals include Gigabit Ethernet,
93 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
94
Andreas Färber37a0c602017-05-15 17:51:18 +080095config ROCKCHIP_RK3368
96 bool "Support Rockchip RK3368"
97 select ARM64
Philipp Tomsich50714572017-06-11 23:46:25 +020098 select SUPPORT_SPL
99 select SUPPORT_TPL
Philipp Tomsich4cf43782017-07-28 20:03:07 +0200100 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
101 select TPL_NEEDS_SEPARATE_STACK if TPL
Philipp Tomsich50714572017-06-11 23:46:25 +0200102 imply SPL_SEPARATE_BSS
103 imply SPL_SERIAL_SUPPORT
104 imply TPL_SERIAL_SUPPORT
Philipp Tomsich50714572017-06-11 23:46:25 +0200105 select DEBUG_UART_BOARD_INIT
Andreas Färber37a0c602017-05-15 17:51:18 +0800106 help
Philipp Tomsich9a8f0092017-06-10 00:47:53 +0200107 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
108 into a big and little cluster with 4 cores each) Cortex-A53 including
109 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
110 (for the little cluster), PowerVR G6110 based graphics, one video
111 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
112 video codec support.
113
114 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
115 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber37a0c602017-05-15 17:51:18 +0800116
Philipp Tomsichd9d12422017-08-02 21:26:18 +0200117if ROCKCHIP_RK3368
118
119config TPL_LDSCRIPT
120 default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
121
Philipp Tomsich5aa49af2017-07-28 20:20:41 +0200122config TPL_TEXT_BASE
123 default 0xff8c1000
124
125config TPL_MAX_SIZE
126 default 28672
127
128config TPL_STACK
129 default 0xff8cffff
130
Philipp Tomsichd9d12422017-08-02 21:26:18 +0200131endif
132
Kever Yanga381bcf2016-07-19 21:16:59 +0800133config ROCKCHIP_RK3399
134 bool "Support Rockchip RK3399"
135 select ARM64
Kever Yang66e87cc2017-02-22 16:56:38 +0800136 select SUPPORT_SPL
137 select SPL
138 select SPL_SEPARATE_BSS
Philipp Tomsichc0508e42017-07-26 12:29:01 +0200139 select SPL_SERIAL_SUPPORT
140 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich7ee16de2017-04-01 12:59:25 +0200141 select DEBUG_UART_BOARD_INIT
Andy Yane3067792017-10-11 15:00:16 +0800142 select BOARD_LATE_INIT
Andy Yanb4d23f72017-10-11 15:00:49 +0800143 select ROCKCHIP_BROM_HELPER
Kever Yanga381bcf2016-07-19 21:16:59 +0800144 help
145 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
146 and quad-core Cortex-A53.
147 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
148 video interfaces supporting HDMI and eDP, several DDR3 options
149 and video codec support. Peripherals include Gigabit Ethernet,
150 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
151
Andy Yan2c1e11d2017-06-01 18:00:55 +0800152config ROCKCHIP_RV1108
153 bool "Support Rockchip RV1108"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530154 select CPU_V7A
Andy Yan2c1e11d2017-06-01 18:00:55 +0800155 help
156 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
157 and a DSP.
158
Philipp Tomsichee14d292017-06-29 11:21:15 +0200159config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuanb47ea792016-07-12 19:09:49 +0800160 bool "SPL returns to bootrom"
161 default y if ROCKCHIP_RK3036
Heiko Stübner1d845942017-02-18 19:46:25 +0100162 select ROCKCHIP_BROM_HELPER
Philipp Tomsichee14d292017-06-29 11:21:15 +0200163 depends on SPL
164 help
165 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
166 SPL will return to the boot rom, which will then load the U-Boot
167 binary to keep going on.
168
169config TPL_ROCKCHIP_BACK_TO_BROM
170 bool "TPL returns to bootrom"
171 default y if ROCKCHIP_RK3368
172 select ROCKCHIP_BROM_HELPER
173 depends on TPL
Xu Ziyuanb47ea792016-07-12 19:09:49 +0800174 help
175 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
176 SPL will return to the boot rom, which will then load the U-Boot
177 binary to keep going on.
178
Andy Yane3067792017-10-11 15:00:16 +0800179config ROCKCHIP_BOOT_MODE_REG
180 hex "Rockchip boot mode flag register address"
181 default 0x200081c8 if ROCKCHIP_RK3036
182 default 0x20004040 if ROCKCHIP_RK3188
183 default 0x110005c8 if ROCKCHIP_RK322X
184 default 0xff730094 if ROCKCHIP_RK3288
185 default 0xff738200 if ROCKCHIP_RK3368
186 default 0xff320300 if ROCKCHIP_RK3399
187 default 0x10300580 if ROCKCHIP_RV1108
188 default 0
189 help
190 The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
191 according to the value from this register.
192
Kever Yangfa1392a2017-04-20 17:03:46 +0800193config ROCKCHIP_SPL_RESERVE_IRAM
194 hex "Size of IRAM reserved in SPL"
Kever Yang8a8106f2017-12-18 15:13:19 +0800195 default 0
Kever Yangfa1392a2017-04-20 17:03:46 +0800196 help
197 SPL may need reserve memory for firmware loaded by SPL, whose load
198 address is in IRAM and may overlay with SPL text area if not
199 reserved.
200
Heiko Stübner1d845942017-02-18 19:46:25 +0100201config ROCKCHIP_BROM_HELPER
202 bool
203
Philipp Tomsichb377d222017-10-10 16:21:10 +0200204config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
205 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
206 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
207 help
208 Some Rockchip BROM variants (e.g. on the RK3188) load the
209 first stage in segments and enter multiple times. E.g. on
210 the RK3188, the first 1KB of the first stage are loaded
211 first and entered; after returning to the BROM, the
212 remainder of the first stage is loaded, but the BROM
213 re-enters at the same address/to the same code as previously.
214
215 This enables support code in the BOOT0 hook for the SPL stage
216 to allow multiple entries.
217
218config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
219 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
220 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
221 help
222 Some Rockchip BROM variants (e.g. on the RK3188) load the
223 first stage in segments and enter multiple times. E.g. on
224 the RK3188, the first 1KB of the first stage are loaded
225 first and entered; after returning to the BROM, the
226 remainder of the first stage is loaded, but the BROM
227 re-enters at the same address/to the same code as previously.
228
229 This enables support code in the BOOT0 hook for the TPL stage
230 to allow multiple entries.
231
Sandy Patterson230e0e02016-08-29 07:31:16 -0400232config SPL_MMC_SUPPORT
Philipp Tomsichee14d292017-06-29 11:21:15 +0200233 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Patterson230e0e02016-08-29 07:31:16 -0400234
huang linbe1d5e02015-11-17 14:20:27 +0800235source "arch/arm/mach-rockchip/rk3036/Kconfig"
Kever Yangdaeed1d2017-11-28 16:04:16 +0800236source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübner0a2be692017-02-18 19:46:36 +0100237source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yangb24a8ec2017-06-23 17:17:54 +0800238source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner041cdb52016-07-16 00:17:15 +0200239source "arch/arm/mach-rockchip/rk3288/Kconfig"
Kever Yang85a3cfb2017-02-23 15:37:51 +0800240source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber37a0c602017-05-15 17:51:18 +0800241source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yanga381bcf2016-07-19 21:16:59 +0800242source "arch/arm/mach-rockchip/rk3399/Kconfig"
Andy Yan2c1e11d2017-06-01 18:00:55 +0800243source "arch/arm/mach-rockchip/rv1108/Kconfig"
Simon Glass2444dae2015-08-30 16:55:38 -0600244endif