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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Bo Shen3225f342013-05-12 22:40:54 +00002/*
3 * Configuation settings for the SAMA5D3xEK board.
4 *
5 * Copyright (C) 2012 - 2013 Atmel
6 *
7 * based on at91sam9m10g45ek.h by:
8 * Stelian Pop <stelian@popies.net>
9 * Lead Tech Design <www.leadtechdesign.com>
Bo Shen3225f342013-05-12 22:40:54 +000010 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
Wu, Joshb2d387b2015-03-30 14:51:19 +080015#include "at91-sama5_common.h"
Bo Shen3225f342013-05-12 22:40:54 +000016
Bo Shen3225f342013-05-12 22:40:54 +000017/*
18 * This needs to be defined for the OHCI code to work but it is defined as
19 * ATMEL_ID_UHPHS in the CPU specific header files.
20 */
Wenyou Yange61ed482017-09-14 11:07:42 +080021#define ATMEL_ID_UHP 32
Bo Shen3225f342013-05-12 22:40:54 +000022
23/*
24 * Specify the clock enable bit in the PMC_SCER register.
25 */
Wenyou Yange61ed482017-09-14 11:07:42 +080026#define ATMEL_PMC_UHP (1 << 6)
Bo Shen3225f342013-05-12 22:40:54 +000027
Bo Shen3225f342013-05-12 22:40:54 +000028/* board specific (not enough SRAM) */
29#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
30
Bo Shend6b79432014-07-18 16:43:08 +080031/* NOR flash */
Masahiro Yamadae856bdc2017-02-11 22:43:54 +090032#ifdef CONFIG_MTD_NOR_FLASH
Bo Shend6b79432014-07-18 16:43:08 +080033#define CONFIG_SYS_FLASH_BASE 0x10000000
34#define CONFIG_SYS_MAX_FLASH_SECT 131
35#define CONFIG_SYS_MAX_FLASH_BANKS 1
Bo Shend6b79432014-07-18 16:43:08 +080036#endif
Bo Shen3225f342013-05-12 22:40:54 +000037
Bo Shen3225f342013-05-12 22:40:54 +000038/* SDRAM */
Wenyou Yange61ed482017-09-14 11:07:42 +080039#define CONFIG_SYS_SDRAM_BASE 0x20000000
Bo Shen3225f342013-05-12 22:40:54 +000040#define CONFIG_SYS_SDRAM_SIZE 0x20000000
41
Bo Shenc5e88852013-11-15 11:12:38 +080042#ifdef CONFIG_SPL_BUILD
Wenyou Yanga97cb062017-04-14 08:51:42 +080043#define CONFIG_SYS_INIT_SP_ADDR 0x318000
Bo Shenc5e88852013-11-15 11:12:38 +080044#else
Bo Shen3225f342013-05-12 22:40:54 +000045#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yanga97cb062017-04-14 08:51:42 +080046 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shenc5e88852013-11-15 11:12:38 +080047#endif
Bo Shen3225f342013-05-12 22:40:54 +000048
49/* SerialFlash */
Bo Shen3225f342013-05-12 22:40:54 +000050
Bo Shen3225f342013-05-12 22:40:54 +000051/* NAND flash */
Bo Shen3225f342013-05-12 22:40:54 +000052#ifdef CONFIG_CMD_NAND
Bo Shen3225f342013-05-12 22:40:54 +000053#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wenyou Yange61ed482017-09-14 11:07:42 +080054#define CONFIG_SYS_NAND_BASE 0x60000000
Bo Shen3225f342013-05-12 22:40:54 +000055/* our ALE is AD21 */
56#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
57/* our CLE is AD22 */
58#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
59#define CONFIG_SYS_NAND_ONFI_DETECTION
Tom Rini8f1a80e2017-07-28 21:31:42 -040060#endif
Bo Shen3225f342013-05-12 22:40:54 +000061
Bo Shen3225f342013-05-12 22:40:54 +000062/* USB */
Bo Shen3225f342013-05-12 22:40:54 +000063#ifdef CONFIG_CMD_USB
Bo Shendcd2f1a2013-10-21 16:14:00 +080064#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Bo Shen3225f342013-05-12 22:40:54 +000065#define CONFIG_USB_OHCI_NEW
66#define CONFIG_SYS_USB_OHCI_CPU_INIT
67#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
68#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3"
69#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
Bo Shen3225f342013-05-12 22:40:54 +000070#endif
71
Bo Shen3225f342013-05-12 22:40:54 +000072#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
73
Bo Shenc5e88852013-11-15 11:12:38 +080074/* SPL */
Wenyou Yanga97cb062017-04-14 08:51:42 +080075#define CONFIG_SPL_MAX_SIZE 0x18000
Bo Shenc5e88852013-11-15 11:12:38 +080076#define CONFIG_SPL_BSS_START_ADDR 0x20000000
77#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
78#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
79#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
80
Bo Shen8a45b0b2014-03-03 14:47:15 +080081#define CONFIG_SYS_MONITOR_LEN (512 << 10)
82
Wenyou Yang55415432017-09-14 11:07:44 +080083#ifdef CONFIG_SD_BOOT
Guillaume GARDET205b4f32014-10-15 17:53:11 +020084#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Wenyou Yang55415432017-09-14 11:07:44 +080085#endif
Bo Shen27019e42014-03-03 14:47:17 +080086#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
87#define CONFIG_SYS_NAND_5_ADDR_CYCLE
88#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
89#define CONFIG_SYS_NAND_PAGE_COUNT 64
90#define CONFIG_SYS_NAND_OOBSIZE 64
91#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
92#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
93
Bo Shen3225f342013-05-12 22:40:54 +000094#endif