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wdenk4d75a502003-03-25 16:50:56 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk716c1dc2005-09-25 18:49:35 +02005 * Copyright (c) 2005 MontaVista Software, Inc.
Wolfgang Denk1972dc02005-09-25 16:27:55 +02006 * Vitaly Bordug <vbordug@ru.mvista.com>
7 * Added support for PCI bridge on MPC8272ADS
8 *
wdenk4d75a502003-03-25 16:50:56 +00009 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29
30#ifdef CONFIG_PCI
31
32#include <pci.h>
wdenk5d232d02003-05-22 22:52:13 +000033#include <mpc8260.h>
wdenk4d75a502003-03-25 16:50:56 +000034#include <asm/m8260_pci.h>
wdenk3c74e322004-02-22 23:46:08 +000035#include <asm/io.h>
Wolfgang Denkd87080b2006-03-31 18:32:53 +020036
37#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
38DECLARE_GLOBAL_DATA_PTR;
39#endif
40
wdenk4d75a502003-03-25 16:50:56 +000041/*
wdenk3c74e322004-02-22 23:46:08 +000042 * Local->PCI map (from CPU) controlled by
wdenk4d75a502003-03-25 16:50:56 +000043 * MPC826x master window
44 *
wdenk3c74e322004-02-22 23:46:08 +000045 * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
46 * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
wdenk8bde7f72003-06-27 21:31:46 +000047 *
wdenk3c74e322004-02-22 23:46:08 +000048 * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
49 * PCI Mem with prefetch
wdenk5d232d02003-05-22 22:52:13 +000050 *
wdenk3c74e322004-02-22 23:46:08 +000051 * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
52 * PCI Mem w/o prefetch
wdenk5d232d02003-05-22 22:52:13 +000053 *
wdenk3c74e322004-02-22 23:46:08 +000054 * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
55 * 32-bit PCI IO
wdenk8bde7f72003-06-27 21:31:46 +000056 *
wdenk4d75a502003-03-25 16:50:56 +000057 * PCI->Local map (from PCI)
wdenk3c74e322004-02-22 23:46:08 +000058 * MPC826x slave window controlled by
wdenk4d75a502003-03-25 16:50:56 +000059 *
wdenk3c74e322004-02-22 23:46:08 +000060 * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
61 * MPC826x local memory
wdenk4d75a502003-03-25 16:50:56 +000062 */
63
wdenk8bde7f72003-06-27 21:31:46 +000064/*
65 * Slave window that allows PCI masters to access MPC826x local memory.
wdenk4d75a502003-03-25 16:50:56 +000066 * This window is set up using the first set of Inbound ATU registers
67 */
68
wdenk8bde7f72003-06-27 21:31:46 +000069#ifndef CFG_PCI_SLV_MEM_LOCAL
wdenk3c74e322004-02-22 23:46:08 +000070#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +000071#else
72#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
wdenk5d232d02003-05-22 22:52:13 +000073#endif
74
75#ifndef CFG_PCI_SLV_MEM_BUS
wdenk3c74e322004-02-22 23:46:08 +000076#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
wdenk5d232d02003-05-22 22:52:13 +000077#else
78#define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS
79#endif
80
81#ifndef CFG_PICMR0_MASK_ATTRIB
wdenk4d75a502003-03-25 16:50:56 +000082#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
wdenk8bde7f72003-06-27 21:31:46 +000083 PICMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +000084#else
85#define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
86#endif
wdenk4d75a502003-03-25 16:50:56 +000087
wdenk8bde7f72003-06-27 21:31:46 +000088/*
wdenk5d232d02003-05-22 22:52:13 +000089 * These are the windows that allow the CPU to access PCI address space.
wdenk8bde7f72003-06-27 21:31:46 +000090 * All three PCI master windows, which allow the CPU to access PCI
91 * prefetch, non prefetch, and IO space (see below), must all fit within
wdenk5d232d02003-05-22 22:52:13 +000092 * these windows.
wdenk4d75a502003-03-25 16:50:56 +000093 */
94
wdenk5d232d02003-05-22 22:52:13 +000095/* PCIBR0 */
96#ifndef CFG_PCI_MSTR0_LOCAL
wdenk3c74e322004-02-22 23:46:08 +000097#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +000098#else
wdenk5d232d02003-05-22 22:52:13 +000099#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
100#endif
101
102#ifndef CFG_PCIMSK0_MASK
wdenk3c74e322004-02-22 23:46:08 +0000103#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +0000104#else
105#define PCIMSK0_MASK CFG_PCIMSK0_MASK
106#endif
107
108/* PCIBR1 */
109#ifndef CFG_PCI_MSTR1_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000110#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +0000111#else
112#define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL
wdenk5d232d02003-05-22 22:52:13 +0000113#endif
114
115#ifndef CFG_PCIMSK1_MASK
wdenk3c74e322004-02-22 23:46:08 +0000116#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +0000117#else
wdenk3c74e322004-02-22 23:46:08 +0000118#define PCIMSK1_MASK CFG_PCIMSK1_MASK
wdenk5d232d02003-05-22 22:52:13 +0000119#endif
wdenk4d75a502003-03-25 16:50:56 +0000120
wdenk8bde7f72003-06-27 21:31:46 +0000121/*
wdenk4d75a502003-03-25 16:50:56 +0000122 * Master window that allows the CPU to access PCI Memory (prefetch).
123 * This window will be setup with the first set of Outbound ATU registers
124 * in the bridge.
125 */
126
wdenk5d232d02003-05-22 22:52:13 +0000127#ifndef CFG_PCI_MSTR_MEM_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000128#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
wdenk5d232d02003-05-22 22:52:13 +0000129#else
130#define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL
131#endif
132
133#ifndef CFG_PCI_MSTR_MEM_BUS
wdenk3c74e322004-02-22 23:46:08 +0000134#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
wdenk5d232d02003-05-22 22:52:13 +0000135#else
136#define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS
137#endif
138
139#ifndef CFG_CPU_PCI_MEM_START
140#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
141#else
142#define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START
143#endif
144
145#ifndef CFG_PCI_MSTR_MEM_SIZE
wdenk3c74e322004-02-22 23:46:08 +0000146#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
wdenk5d232d02003-05-22 22:52:13 +0000147#else
148#define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE
149#endif
150
151#ifndef CFG_POCMR0_MASK_ATTRIB
wdenk4d75a502003-03-25 16:50:56 +0000152#define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +0000153#else
154#define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
155#endif
wdenk4d75a502003-03-25 16:50:56 +0000156
wdenk8bde7f72003-06-27 21:31:46 +0000157/*
wdenk4d75a502003-03-25 16:50:56 +0000158 * Master window that allows the CPU to access PCI Memory (non-prefetch).
159 * This window will be setup with the second set of Outbound ATU registers
160 * in the bridge.
161 */
162
wdenk8bde7f72003-06-27 21:31:46 +0000163#ifndef CFG_PCI_MSTR_MEMIO_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000164#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +0000165#else
166#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
wdenk5d232d02003-05-22 22:52:13 +0000167#endif
168
wdenk8bde7f72003-06-27 21:31:46 +0000169#ifndef CFG_PCI_MSTR_MEMIO_BUS
wdenk3c74e322004-02-22 23:46:08 +0000170#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
wdenk8bde7f72003-06-27 21:31:46 +0000171#else
172#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
wdenk5d232d02003-05-22 22:52:13 +0000173#endif
174
wdenk8bde7f72003-06-27 21:31:46 +0000175#ifndef CFG_CPU_PCI_MEMIO_START
176#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
177#else
178#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START
wdenk5d232d02003-05-22 22:52:13 +0000179#endif
180
wdenk8bde7f72003-06-27 21:31:46 +0000181#ifndef CFG_PCI_MSTR_MEMIO_SIZE
wdenk3c74e322004-02-22 23:46:08 +0000182#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
wdenk8bde7f72003-06-27 21:31:46 +0000183#else
184#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
wdenk5d232d02003-05-22 22:52:13 +0000185#endif
186
187#ifndef CFG_POCMR1_MASK_ATTRIB
wdenk3c74e322004-02-22 23:46:08 +0000188#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
wdenk5d232d02003-05-22 22:52:13 +0000189#else
190#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
191#endif
wdenk4d75a502003-03-25 16:50:56 +0000192
wdenk8bde7f72003-06-27 21:31:46 +0000193/*
wdenk4d75a502003-03-25 16:50:56 +0000194 * Master window that allows the CPU to access PCI IO space.
195 * This window will be setup with the third set of Outbound ATU registers
196 * in the bridge.
197 */
198
wdenk8bde7f72003-06-27 21:31:46 +0000199#ifndef CFG_PCI_MSTR_IO_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000200#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +0000201#else
202#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
wdenk66fd3d12003-05-18 11:30:09 +0000203#endif
wdenk5d232d02003-05-22 22:52:13 +0000204
wdenk8bde7f72003-06-27 21:31:46 +0000205#ifndef CFG_PCI_MSTR_IO_BUS
wdenk3c74e322004-02-22 23:46:08 +0000206#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
wdenk8bde7f72003-06-27 21:31:46 +0000207#else
208#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
wdenk5d232d02003-05-22 22:52:13 +0000209#endif
210
wdenk8bde7f72003-06-27 21:31:46 +0000211#ifndef CFG_CPU_PCI_IO_START
212#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
213#else
214#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START
wdenk5d232d02003-05-22 22:52:13 +0000215#endif
216
wdenk8bde7f72003-06-27 21:31:46 +0000217#ifndef CFG_PCI_MSTR_IO_SIZE
wdenk3c74e322004-02-22 23:46:08 +0000218#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
wdenk8bde7f72003-06-27 21:31:46 +0000219#else
220#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
wdenk5d232d02003-05-22 22:52:13 +0000221#endif
222
223#ifndef CFG_POCMR2_MASK_ATTRIB
wdenk3c74e322004-02-22 23:46:08 +0000224#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
wdenk5d232d02003-05-22 22:52:13 +0000225#else
226#define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB
227#endif
wdenk4d75a502003-03-25 16:50:56 +0000228
229/* PCI bus configuration registers.
230 */
231
232#define PCI_CLASS_BRIDGE_CTLR 0x06
233
234
wdenk3c74e322004-02-22 23:46:08 +0000235static inline void pci_outl (u32 addr, u32 data)
wdenk4d75a502003-03-25 16:50:56 +0000236{
wdenk3c74e322004-02-22 23:46:08 +0000237 *(volatile u32 *) addr = cpu_to_le32 (data);
wdenk4d75a502003-03-25 16:50:56 +0000238}
239
wdenk3c74e322004-02-22 23:46:08 +0000240void pci_mpc8250_init (struct pci_controller *hose)
wdenk4d75a502003-03-25 16:50:56 +0000241{
wdenk3c74e322004-02-22 23:46:08 +0000242 u16 tempShort;
wdenk4d75a502003-03-25 16:50:56 +0000243
wdenk3c74e322004-02-22 23:46:08 +0000244 volatile immap_t *immap = (immap_t *) CFG_IMMR;
245 pci_dev_t host_devno = PCI_BDF (0, 0, 0);
wdenk4d75a502003-03-25 16:50:56 +0000246
wdenk3c74e322004-02-22 23:46:08 +0000247 pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG,
248 CFG_IMMR + PCI_CFG_DATA_REG);
249
250 /*
251 * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
252 */
wdenk5d232d02003-05-22 22:52:13 +0000253#ifdef CONFIG_MPC8266ADS
wdenk3c74e322004-02-22 23:46:08 +0000254 immap->im_siu_conf.sc_siumcr =
255 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
256 | SIUMCR_LBPC01;
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200257#elif defined CONFIG_MPC8272
Wolfgang Denk716c1dc2005-09-25 18:49:35 +0200258 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
259 ~SIUMCR_BBD &
260 ~SIUMCR_ESE &
261 ~SIUMCR_PBSE &
262 ~SIUMCR_CDIS &
263 ~SIUMCR_DPPC11 &
264 ~SIUMCR_L2CPC11 &
265 ~SIUMCR_LBPC11 &
266 ~SIUMCR_APPC11 &
267 ~SIUMCR_CS10PC11 &
268 ~SIUMCR_BCTLC11 &
269 ~SIUMCR_MMR11)
270 | SIUMCR_DPPC11
271 | SIUMCR_L2CPC01
272 | SIUMCR_LBPC00
273 | SIUMCR_APPC10
274 | SIUMCR_CS10PC00
275 | SIUMCR_BCTLC00
276 | SIUMCR_MMR11;
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200277
wdenk5d232d02003-05-22 22:52:13 +0000278#else
wdenk3c74e322004-02-22 23:46:08 +0000279 /*
280 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
281 * and local bus for PCI (SIUMCR [LBPC]).
282 */
283 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
284 ~SIUMCR_LBPC11 &
wdenk8bde7f72003-06-27 21:31:46 +0000285 ~SIUMCR_CS10PC11 &
wdenk3c74e322004-02-22 23:46:08 +0000286 ~SIUMCR_LBPC11) |
287 SIUMCR_LBPC01 |
288 SIUMCR_CS10PC01 |
289 SIUMCR_APPC10;
wdenk5d232d02003-05-22 22:52:13 +0000290#endif
wdenk4d75a502003-03-25 16:50:56 +0000291
wdenk3c74e322004-02-22 23:46:08 +0000292 /* Make PCI lowest priority */
293 /* Each 4 bits is a device bus request and the MS 4bits
294 is highest priority */
295 /* Bus 4bit value
296 --- ----------
297 CPM high 0b0000
298 CPM middle 0b0001
299 CPM low 0b0010
300 PCI reguest 0b0011
301 Reserved 0b0100
302 Reserved 0b0101
303 Internal Core 0b0110
304 External Master 1 0b0111
305 External Master 2 0b1000
306 External Master 3 0b1001
307 The rest are reserved */
308 immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
wdenk4d75a502003-03-25 16:50:56 +0000309
wdenk3c74e322004-02-22 23:46:08 +0000310 /* Park bus on core while modifying PCI Bus accesses */
311 immap->im_siu_conf.sc_ppc_acr = 0x6;
wdenk4d75a502003-03-25 16:50:56 +0000312
wdenk3c74e322004-02-22 23:46:08 +0000313 /*
314 * Set up master windows that allow the CPU to access PCI space. These
315 * windows are set up using the two SIU PCIBR registers.
316 */
317 immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
318 immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
wdenk5d232d02003-05-22 22:52:13 +0000319
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200320#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
wdenkd4326ac2004-04-18 21:17:30 +0000321 immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
322 immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
wdenk8bde7f72003-06-27 21:31:46 +0000323#endif
wdenk4d75a502003-03-25 16:50:56 +0000324
wdenk3c74e322004-02-22 23:46:08 +0000325 /* Release PCI RST (by default the PCI RST signal is held low) */
326 immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
wdenk4d75a502003-03-25 16:50:56 +0000327
wdenk3c74e322004-02-22 23:46:08 +0000328 /* give it some time */
329 {
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200330#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
wdenk8bde7f72003-06-27 21:31:46 +0000331 /* Give the PCI cards more time to initialize before query
wdenk3c74e322004-02-22 23:46:08 +0000332 This might be good for other boards also
333 */
334 int i;
335
336 for (i = 0; i < 1000; ++i)
wdenk5d232d02003-05-22 22:52:13 +0000337#endif
wdenk3c74e322004-02-22 23:46:08 +0000338 udelay (1000);
339 }
wdenk4d75a502003-03-25 16:50:56 +0000340
wdenk3c74e322004-02-22 23:46:08 +0000341 /*
342 * Set up master window that allows the CPU to access PCI Memory (prefetch)
343 * space. This window is set up using the first set of Outbound ATU registers.
344 */
345 immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */
346 immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
347 immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */
wdenk4d75a502003-03-25 16:50:56 +0000348
wdenk3c74e322004-02-22 23:46:08 +0000349 /*
350 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
351 * space. This window is set up using the second set of Outbound ATU registers.
352 */
353 immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
354 immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
355 immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */
wdenk8bde7f72003-06-27 21:31:46 +0000356
wdenk3c74e322004-02-22 23:46:08 +0000357 /*
358 * Set up master window that allows the CPU to access PCI IO space. This window
359 * is set up using the third set of Outbound ATU registers.
360 */
361 immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
362 immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */
363 immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */
wdenk4d75a502003-03-25 16:50:56 +0000364
wdenk3c74e322004-02-22 23:46:08 +0000365 /*
366 * Set up slave window that allows PCI masters to access MPC826x local memory.
367 * This window is set up using the first set of Inbound ATU registers
368 */
369 immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */
370 immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
371 immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */
wdenk4d75a502003-03-25 16:50:56 +0000372
wdenk3c74e322004-02-22 23:46:08 +0000373 /* See above for description - puts PCI request as highest priority */
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200374#ifdef CONFIG_MPC8272
375 immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
376#else
wdenk3c74e322004-02-22 23:46:08 +0000377 immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200378#endif
wdenk4d75a502003-03-25 16:50:56 +0000379
wdenk3c74e322004-02-22 23:46:08 +0000380 /* Park the bus on the PCI */
381 immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
wdenk4d75a502003-03-25 16:50:56 +0000382
wdenk3c74e322004-02-22 23:46:08 +0000383 /* Host mode - specify the bridge as a host-PCI bridge */
wdenk4d75a502003-03-25 16:50:56 +0000384
wdenk3c74e322004-02-22 23:46:08 +0000385 pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
386 PCI_CLASS_BRIDGE_CTLR);
wdenk4d75a502003-03-25 16:50:56 +0000387
wdenk3c74e322004-02-22 23:46:08 +0000388 /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
389 pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
390 pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
391 tempShort | PCI_COMMAND_MASTER |
392 PCI_COMMAND_MEMORY);
wdenk4d75a502003-03-25 16:50:56 +0000393
wdenk7a8e9bed2003-05-31 18:35:21 +0000394 /* do some bridge init, should be done on all 8260 based bridges */
wdenk3c74e322004-02-22 23:46:08 +0000395 pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
396 0x08);
397 pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
398 0xF8);
wdenk7a8e9bed2003-05-31 18:35:21 +0000399
wdenk3c74e322004-02-22 23:46:08 +0000400 hose->first_busno = 0;
401 hose->last_busno = 0xff;
wdenk4d75a502003-03-25 16:50:56 +0000402
wdenk3c74e322004-02-22 23:46:08 +0000403 /* System memory space */
Wolfgang Denk716c1dc2005-09-25 18:49:35 +0200404#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
wdenk3c74e322004-02-22 23:46:08 +0000405 pci_set_region (hose->regions + 0,
406 PCI_SLV_MEM_BUS,
407 PCI_SLV_MEM_LOCAL,
408 gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
wdenk5d232d02003-05-22 22:52:13 +0000409#else
wdenk3c74e322004-02-22 23:46:08 +0000410 pci_set_region (hose->regions + 0,
411 CFG_SDRAM_BASE,
412 CFG_SDRAM_BASE,
413 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
wdenk5d232d02003-05-22 22:52:13 +0000414#endif
wdenk4d75a502003-03-25 16:50:56 +0000415
wdenk3c74e322004-02-22 23:46:08 +0000416 /* PCI memory space */
Wolfgang Denk716c1dc2005-09-25 18:49:35 +0200417#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
wdenk3c74e322004-02-22 23:46:08 +0000418 pci_set_region (hose->regions + 1,
419 PCI_MSTR_MEMIO_BUS,
420 PCI_MSTR_MEMIO_LOCAL,
421 PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
wdenk5d232d02003-05-22 22:52:13 +0000422#else
wdenk3c74e322004-02-22 23:46:08 +0000423 pci_set_region (hose->regions + 1,
424 PCI_MSTR_MEM_BUS,
425 PCI_MSTR_MEM_LOCAL,
426 PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
wdenk5d232d02003-05-22 22:52:13 +0000427#endif
wdenk4d75a502003-03-25 16:50:56 +0000428
wdenk3c74e322004-02-22 23:46:08 +0000429 /* PCI I/O space */
430 pci_set_region (hose->regions + 2,
431 PCI_MSTR_IO_BUS,
432 PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
wdenk4d75a502003-03-25 16:50:56 +0000433
wdenk3c74e322004-02-22 23:46:08 +0000434 hose->region_count = 3;
wdenk4d75a502003-03-25 16:50:56 +0000435
wdenk3c74e322004-02-22 23:46:08 +0000436 pci_register_hose (hose);
437 /* Mask off master abort machine checks */
438 immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
439 eieio ();
wdenk4d75a502003-03-25 16:50:56 +0000440
wdenk3c74e322004-02-22 23:46:08 +0000441 hose->last_busno = pci_hose_scan (hose);
442
443
444 /* clear the error in the error status register */
445 immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
446
447 /* unmask master abort machine checks */
448 immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
wdenk4d75a502003-03-25 16:50:56 +0000449}
450
wdenk3c74e322004-02-22 23:46:08 +0000451#endif /* CONFIG_PCI */