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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
3 *
4 * This driver for AMD PCnet network controllers is derived from the
5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00008 */
9
10#include <common.h>
11#include <malloc.h>
12#include <net.h>
Ben Warrene3090532008-08-31 10:08:43 -070013#include <netdev.h>
wdenkc6097192002-11-03 00:24:07 +000014#include <asm/io.h>
15#include <pci.h>
16
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020017#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
wdenkc6097192002-11-03 00:24:07 +000018
Wolfgang Denk138b6082011-11-05 05:12:58 +000019#define PCNET_DEBUG1(fmt,args...) \
20 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
21#define PCNET_DEBUG2(fmt,args...) \
22 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
wdenkc6097192002-11-03 00:24:07 +000023
wdenkc6097192002-11-03 00:24:07 +000024#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
25#error "Macro for PCnet chip version is not defined!"
26#endif
27
28/*
29 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
30 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
31 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
32 */
33#define PCNET_LOG_TX_BUFFERS 0
34#define PCNET_LOG_RX_BUFFERS 2
35
36#define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
37#define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
38
39#define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
40#define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
41
42#define PKT_BUF_SZ 1544
43
44/* The PCNET Rx and Tx ring descriptors. */
45struct pcnet_rx_head {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020046 u32 base;
47 s16 buf_length;
48 s16 status;
49 u32 msg_length;
50 u32 reserved;
wdenkc6097192002-11-03 00:24:07 +000051};
52
53struct pcnet_tx_head {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020054 u32 base;
55 s16 length;
56 s16 status;
57 u32 misc;
58 u32 reserved;
wdenkc6097192002-11-03 00:24:07 +000059};
60
61/* The PCNET 32-Bit initialization block, described in databook. */
62struct pcnet_init_block {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020063 u16 mode;
64 u16 tlen_rlen;
65 u8 phys_addr[6];
66 u16 reserved;
67 u32 filter[2];
68 /* Receive and transmit ring base, along with extra bits. */
69 u32 rx_ring;
70 u32 tx_ring;
71 u32 reserved2;
wdenkc6097192002-11-03 00:24:07 +000072};
73
Paul Burtonf1ae3822014-04-07 16:41:46 +010074struct pcnet_uncached_priv {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020075 struct pcnet_rx_head rx_ring[RX_RING_SIZE];
76 struct pcnet_tx_head tx_ring[TX_RING_SIZE];
77 struct pcnet_init_block init_block;
Paul Burtonf1ae3822014-04-07 16:41:46 +010078};
79
80typedef struct pcnet_priv {
81 struct pcnet_uncached_priv *uc;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020082 /* Receive Buffer space */
Paul Burtona354ddc2014-04-07 16:41:47 +010083 unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4];
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020084 int cur_rx;
85 int cur_tx;
wdenkc6097192002-11-03 00:24:07 +000086} pcnet_priv_t;
87
88static pcnet_priv_t *lp;
89
90/* Offsets from base I/O address for WIO mode */
91#define PCNET_RDP 0x10
92#define PCNET_RAP 0x12
93#define PCNET_RESET 0x14
94#define PCNET_BDP 0x16
95
Paul Burton6011dab2013-11-08 11:18:43 +000096static u16 pcnet_read_csr(struct eth_device *dev, int index)
wdenkc6097192002-11-03 00:24:07 +000097{
Paul Burton6011dab2013-11-08 11:18:43 +000098 outw(index, dev->iobase + PCNET_RAP);
99 return inw(dev->iobase + PCNET_RDP);
wdenkc6097192002-11-03 00:24:07 +0000100}
101
Paul Burton6011dab2013-11-08 11:18:43 +0000102static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
wdenkc6097192002-11-03 00:24:07 +0000103{
Paul Burton6011dab2013-11-08 11:18:43 +0000104 outw(index, dev->iobase + PCNET_RAP);
105 outw(val, dev->iobase + PCNET_RDP);
wdenkc6097192002-11-03 00:24:07 +0000106}
107
Paul Burton6011dab2013-11-08 11:18:43 +0000108static u16 pcnet_read_bcr(struct eth_device *dev, int index)
wdenkc6097192002-11-03 00:24:07 +0000109{
Paul Burton6011dab2013-11-08 11:18:43 +0000110 outw(index, dev->iobase + PCNET_RAP);
111 return inw(dev->iobase + PCNET_BDP);
wdenkc6097192002-11-03 00:24:07 +0000112}
113
Paul Burton6011dab2013-11-08 11:18:43 +0000114static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
wdenkc6097192002-11-03 00:24:07 +0000115{
Paul Burton6011dab2013-11-08 11:18:43 +0000116 outw(index, dev->iobase + PCNET_RAP);
117 outw(val, dev->iobase + PCNET_BDP);
wdenkc6097192002-11-03 00:24:07 +0000118}
119
Paul Burton6011dab2013-11-08 11:18:43 +0000120static void pcnet_reset(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000121{
Paul Burton6011dab2013-11-08 11:18:43 +0000122 inw(dev->iobase + PCNET_RESET);
wdenkc6097192002-11-03 00:24:07 +0000123}
124
Paul Burton6011dab2013-11-08 11:18:43 +0000125static int pcnet_check(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000126{
Paul Burton6011dab2013-11-08 11:18:43 +0000127 outw(88, dev->iobase + PCNET_RAP);
128 return inw(dev->iobase + PCNET_RAP) == 88;
wdenkc6097192002-11-03 00:24:07 +0000129}
130
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200131static int pcnet_init (struct eth_device *dev, bd_t * bis);
Joe Hershbergerf92a1512012-05-22 18:09:56 +0000132static int pcnet_send(struct eth_device *dev, void *packet, int length);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200133static int pcnet_recv (struct eth_device *dev);
134static void pcnet_halt (struct eth_device *dev);
135static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
wdenkc6097192002-11-03 00:24:07 +0000136
Gabor Juhos54fbcb02013-05-22 03:57:43 +0000137#define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a))
wdenkc6097192002-11-03 00:24:07 +0000138#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
139
140static struct pci_device_id supported[] = {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200141 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
142 {}
wdenkc6097192002-11-03 00:24:07 +0000143};
144
145
Paul Burton6011dab2013-11-08 11:18:43 +0000146int pcnet_initialize(bd_t *bis)
wdenkc6097192002-11-03 00:24:07 +0000147{
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200148 pci_dev_t devbusfn;
149 struct eth_device *dev;
150 u16 command, status;
151 int dev_nr = 0;
wdenkc6097192002-11-03 00:24:07 +0000152
Paul Burton6011dab2013-11-08 11:18:43 +0000153 PCNET_DEBUG1("\npcnet_initialize...\n");
wdenkc6097192002-11-03 00:24:07 +0000154
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200155 for (dev_nr = 0;; dev_nr++) {
wdenkc6097192002-11-03 00:24:07 +0000156
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200157 /*
158 * Find the PCnet PCI device(s).
159 */
Paul Burton6011dab2013-11-08 11:18:43 +0000160 devbusfn = pci_find_devices(supported, dev_nr);
161 if (devbusfn < 0)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200162 break;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200163
164 /*
165 * Allocate and pre-fill the device structure.
166 */
Paul Burton6011dab2013-11-08 11:18:43 +0000167 dev = (struct eth_device *)malloc(sizeof(*dev));
Nobuhiro Iwamatsu5ed0eec2010-10-19 14:03:45 +0900168 if (!dev) {
169 printf("pcnet: Can not allocate memory\n");
170 break;
171 }
172 memset(dev, 0, sizeof(*dev));
Paul Burton6011dab2013-11-08 11:18:43 +0000173 dev->priv = (void *)devbusfn;
174 sprintf(dev->name, "pcnet#%d", dev_nr);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200175
176 /*
177 * Setup the PCI device.
178 */
Paul Burton6011dab2013-11-08 11:18:43 +0000179 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
180 (unsigned int *)&dev->iobase);
181 dev->iobase = pci_io_to_phys(devbusfn, dev->iobase);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200182 dev->iobase &= ~0xf;
183
Paul Burton6011dab2013-11-08 11:18:43 +0000184 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
185 dev->name, devbusfn, dev->iobase);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200186
187 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
Paul Burton6011dab2013-11-08 11:18:43 +0000188 pci_write_config_word(devbusfn, PCI_COMMAND, command);
189 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200190 if ((status & command) != command) {
Paul Burton6011dab2013-11-08 11:18:43 +0000191 printf("%s: Couldn't enable IO access or Bus Mastering\n",
192 dev->name);
193 free(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200194 continue;
195 }
196
Paul Burton6011dab2013-11-08 11:18:43 +0000197 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200198
199 /*
200 * Probe the PCnet chip.
201 */
Paul Burton6011dab2013-11-08 11:18:43 +0000202 if (pcnet_probe(dev, bis, dev_nr) < 0) {
203 free(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200204 continue;
205 }
206
207 /*
208 * Setup device structure and register the driver.
209 */
210 dev->init = pcnet_init;
211 dev->halt = pcnet_halt;
212 dev->send = pcnet_send;
213 dev->recv = pcnet_recv;
214
Paul Burton6011dab2013-11-08 11:18:43 +0000215 eth_register(dev);
wdenkc6097192002-11-03 00:24:07 +0000216 }
217
Paul Burton6011dab2013-11-08 11:18:43 +0000218 udelay(10 * 1000);
wdenkc6097192002-11-03 00:24:07 +0000219
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200220 return dev_nr;
wdenkc6097192002-11-03 00:24:07 +0000221}
222
Paul Burton6011dab2013-11-08 11:18:43 +0000223static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
wdenkc6097192002-11-03 00:24:07 +0000224{
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200225 int chip_version;
226 char *chipname;
227
wdenkc6097192002-11-03 00:24:07 +0000228#ifdef PCNET_HAS_PROM
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200229 int i;
wdenkc6097192002-11-03 00:24:07 +0000230#endif
231
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200232 /* Reset the PCnet controller */
Paul Burton6011dab2013-11-08 11:18:43 +0000233 pcnet_reset(dev);
wdenkc6097192002-11-03 00:24:07 +0000234
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200235 /* Check if register access is working */
Paul Burton6011dab2013-11-08 11:18:43 +0000236 if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
237 printf("%s: CSR register access check failed\n", dev->name);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200238 return -1;
239 }
wdenkc6097192002-11-03 00:24:07 +0000240
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200241 /* Identify the chip */
242 chip_version =
Paul Burton6011dab2013-11-08 11:18:43 +0000243 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200244 if ((chip_version & 0xfff) != 0x003)
245 return -1;
246 chip_version = (chip_version >> 12) & 0xffff;
247 switch (chip_version) {
248 case 0x2621:
249 chipname = "PCnet/PCI II 79C970A"; /* PCI */
250 break;
wdenkc6097192002-11-03 00:24:07 +0000251#ifdef CONFIG_PCNET_79C973
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200252 case 0x2625:
253 chipname = "PCnet/FAST III 79C973"; /* PCI */
254 break;
wdenkc6097192002-11-03 00:24:07 +0000255#endif
256#ifdef CONFIG_PCNET_79C975
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200257 case 0x2627:
258 chipname = "PCnet/FAST III 79C975"; /* PCI */
259 break;
wdenkc6097192002-11-03 00:24:07 +0000260#endif
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200261 default:
Paul Burton6011dab2013-11-08 11:18:43 +0000262 printf("%s: PCnet version %#x not supported\n",
263 dev->name, chip_version);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200264 return -1;
265 }
wdenkc6097192002-11-03 00:24:07 +0000266
Paul Burton6011dab2013-11-08 11:18:43 +0000267 PCNET_DEBUG1("AMD %s\n", chipname);
wdenkc6097192002-11-03 00:24:07 +0000268
269#ifdef PCNET_HAS_PROM
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200270 /*
271 * In most chips, after a chip reset, the ethernet address is read from
272 * the station address PROM at the base address and programmed into the
273 * "Physical Address Registers" CSR12-14.
274 */
275 for (i = 0; i < 3; i++) {
276 unsigned int val;
277
Paul Burton6011dab2013-11-08 11:18:43 +0000278 val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200279 /* There may be endianness issues here. */
280 dev->enetaddr[2 * i] = val & 0x0ff;
281 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
282 }
wdenkc6097192002-11-03 00:24:07 +0000283#endif /* PCNET_HAS_PROM */
284
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200285 return 0;
wdenkc6097192002-11-03 00:24:07 +0000286}
287
Paul Burton6011dab2013-11-08 11:18:43 +0000288static int pcnet_init(struct eth_device *dev, bd_t *bis)
wdenkc6097192002-11-03 00:24:07 +0000289{
Paul Burtonf1ae3822014-04-07 16:41:46 +0100290 struct pcnet_uncached_priv *uc;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200291 int i, val;
292 u32 addr;
wdenkc6097192002-11-03 00:24:07 +0000293
Paul Burton6011dab2013-11-08 11:18:43 +0000294 PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
wdenkc6097192002-11-03 00:24:07 +0000295
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200296 /* Switch pcnet to 32bit mode */
Paul Burton6011dab2013-11-08 11:18:43 +0000297 pcnet_write_bcr(dev, 20, 2);
wdenkc6097192002-11-03 00:24:07 +0000298
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200299 /* Set/reset autoselect bit */
Paul Burton6011dab2013-11-08 11:18:43 +0000300 val = pcnet_read_bcr(dev, 2) & ~2;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200301 val |= 2;
Paul Burton6011dab2013-11-08 11:18:43 +0000302 pcnet_write_bcr(dev, 2, val);
wdenkc6097192002-11-03 00:24:07 +0000303
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200304 /* Enable auto negotiate, setup, disable fd */
Paul Burton6011dab2013-11-08 11:18:43 +0000305 val = pcnet_read_bcr(dev, 32) & ~0x98;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200306 val |= 0x20;
Paul Burton6011dab2013-11-08 11:18:43 +0000307 pcnet_write_bcr(dev, 32, val);
wdenkc6097192002-11-03 00:24:07 +0000308
wdenkc6097192002-11-03 00:24:07 +0000309 /*
Paul Burton62715a22013-11-08 11:18:46 +0000310 * Enable NOUFLO on supported controllers, with the transmit
311 * start point set to the full packet. This will cause entire
312 * packets to be buffered by the ethernet controller before
313 * transmission, eliminating underflows which are common on
314 * slower devices. Controllers which do not support NOUFLO will
315 * simply be left with a larger transmit FIFO threshold.
316 */
317 val = pcnet_read_bcr(dev, 18);
318 val |= 1 << 11;
319 pcnet_write_bcr(dev, 18, val);
320 val = pcnet_read_csr(dev, 80);
321 val |= 0x3 << 10;
322 pcnet_write_csr(dev, 80, val);
323
324 /*
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200325 * We only maintain one structure because the drivers will never
326 * be used concurrently. In 32bit mode the RX and TX ring entries
327 * must be aligned on 16-byte boundaries.
wdenkc6097192002-11-03 00:24:07 +0000328 */
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200329 if (lp == NULL) {
Paul Burton6011dab2013-11-08 11:18:43 +0000330 addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200331 addr = (addr + 0xf) & ~0xf;
Paul Burton6011dab2013-11-08 11:18:43 +0000332 lp = (pcnet_priv_t *)addr;
Paul Burtonf1ae3822014-04-07 16:41:46 +0100333
334 addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc));
335 flush_dcache_range(addr, addr + sizeof(*lp->uc));
336 addr = UNCACHED_SDRAM(addr);
337 lp->uc = (struct pcnet_uncached_priv *)addr;
Paul Burtona354ddc2014-04-07 16:41:47 +0100338
339 addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->rx_buf));
340 flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
341 lp->rx_buf = (void *)addr;
wdenkc6097192002-11-03 00:24:07 +0000342 }
wdenkc6097192002-11-03 00:24:07 +0000343
Paul Burtonf1ae3822014-04-07 16:41:46 +0100344 uc = lp->uc;
345
346 uc->init_block.mode = cpu_to_le16(0x0000);
347 uc->init_block.filter[0] = 0x00000000;
348 uc->init_block.filter[1] = 0x00000000;
wdenkc6097192002-11-03 00:24:07 +0000349
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200350 /*
351 * Initialize the Rx ring.
352 */
353 lp->cur_rx = 0;
354 for (i = 0; i < RX_RING_SIZE; i++) {
Paul Burtona354ddc2014-04-07 16:41:47 +0100355 uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, (*lp->rx_buf)[i]);
Paul Burtonf1ae3822014-04-07 16:41:46 +0100356 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
357 uc->rx_ring[i].status = cpu_to_le16(0x8000);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200358 PCNET_DEBUG1
359 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
Paul Burtonf1ae3822014-04-07 16:41:46 +0100360 uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
361 uc->rx_ring[i].status);
wdenkc6097192002-11-03 00:24:07 +0000362 }
wdenkc6097192002-11-03 00:24:07 +0000363
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200364 /*
365 * Initialize the Tx ring. The Tx buffer address is filled in as
366 * needed, but we do need to clear the upper ownership bit.
367 */
368 lp->cur_tx = 0;
369 for (i = 0; i < TX_RING_SIZE; i++) {
Paul Burtonf1ae3822014-04-07 16:41:46 +0100370 uc->tx_ring[i].base = 0;
371 uc->tx_ring[i].status = 0;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200372 }
373
374 /*
375 * Setup Init Block.
376 */
Paul Burtonf1ae3822014-04-07 16:41:46 +0100377 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200378
379 for (i = 0; i < 6; i++) {
Paul Burtonf1ae3822014-04-07 16:41:46 +0100380 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
381 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200382 }
383
Paul Burtonf1ae3822014-04-07 16:41:46 +0100384 uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
Paul Burton6011dab2013-11-08 11:18:43 +0000385 RX_RING_LEN_BITS);
Paul Burtonf1ae3822014-04-07 16:41:46 +0100386 uc->init_block.rx_ring = PCI_TO_MEM_LE(dev, uc->rx_ring);
387 uc->init_block.tx_ring = PCI_TO_MEM_LE(dev, uc->tx_ring);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200388
Paul Burton6011dab2013-11-08 11:18:43 +0000389 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
Paul Burtonf1ae3822014-04-07 16:41:46 +0100390 uc->init_block.tlen_rlen,
391 uc->init_block.rx_ring, uc->init_block.tx_ring);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200392
393 /*
394 * Tell the controller where the Init Block is located.
395 */
Paul Burtonf1ae3822014-04-07 16:41:46 +0100396 barrier();
397 addr = PCI_TO_MEM(dev, &lp->uc->init_block);
Paul Burton6011dab2013-11-08 11:18:43 +0000398 pcnet_write_csr(dev, 1, addr & 0xffff);
399 pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200400
Paul Burton6011dab2013-11-08 11:18:43 +0000401 pcnet_write_csr(dev, 4, 0x0915);
402 pcnet_write_csr(dev, 0, 0x0001); /* start */
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200403
404 /* Wait for Init Done bit */
405 for (i = 10000; i > 0; i--) {
Paul Burton6011dab2013-11-08 11:18:43 +0000406 if (pcnet_read_csr(dev, 0) & 0x0100)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200407 break;
Paul Burton6011dab2013-11-08 11:18:43 +0000408 udelay(10);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200409 }
410 if (i <= 0) {
Paul Burton6011dab2013-11-08 11:18:43 +0000411 printf("%s: TIMEOUT: controller init failed\n", dev->name);
412 pcnet_reset(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200413 return -1;
414 }
415
416 /*
417 * Finally start network controller operation.
418 */
Paul Burton6011dab2013-11-08 11:18:43 +0000419 pcnet_write_csr(dev, 0, 0x0002);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200420
421 return 0;
wdenkc6097192002-11-03 00:24:07 +0000422}
423
Joe Hershbergerf92a1512012-05-22 18:09:56 +0000424static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
wdenkc6097192002-11-03 00:24:07 +0000425{
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200426 int i, status;
Paul Burtonf1ae3822014-04-07 16:41:46 +0100427 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
wdenkc6097192002-11-03 00:24:07 +0000428
Paul Burton6011dab2013-11-08 11:18:43 +0000429 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
430 packet);
wdenkc6097192002-11-03 00:24:07 +0000431
Paul Burtonf3ac8662013-11-08 11:18:45 +0000432 flush_dcache_range((unsigned long)packet,
433 (unsigned long)packet + pkt_len);
434
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200435 /* Wait for completion by testing the OWN bit */
436 for (i = 1000; i > 0; i--) {
Paul Burton6fb49e42014-04-07 16:41:48 +0100437 status = readw(&entry->status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200438 if ((status & 0x8000) == 0)
439 break;
Paul Burton6011dab2013-11-08 11:18:43 +0000440 udelay(100);
441 PCNET_DEBUG2(".");
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200442 }
443 if (i <= 0) {
Paul Burton6011dab2013-11-08 11:18:43 +0000444 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
445 dev->name, lp->cur_tx, status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200446 pkt_len = 0;
447 goto failure;
448 }
wdenkc6097192002-11-03 00:24:07 +0000449
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200450 /*
451 * Setup Tx ring. Caution: the write order is important here,
452 * set the status with the "ownership" bits last.
453 */
Paul Burton6fb49e42014-04-07 16:41:48 +0100454 writew(-pkt_len, &entry->length);
455 writel(0, &entry->misc);
456 writel(PCI_TO_MEM(dev, packet), &entry->base);
457 writew(0x8300, &entry->status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200458
459 /* Trigger an immediate send poll. */
Paul Burton6011dab2013-11-08 11:18:43 +0000460 pcnet_write_csr(dev, 0, 0x0008);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200461
462 failure:
463 if (++lp->cur_tx >= TX_RING_SIZE)
464 lp->cur_tx = 0;
465
Paul Burton6011dab2013-11-08 11:18:43 +0000466 PCNET_DEBUG2("done\n");
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200467 return pkt_len;
wdenkc6097192002-11-03 00:24:07 +0000468}
469
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200470static int pcnet_recv (struct eth_device *dev)
471{
472 struct pcnet_rx_head *entry;
Paul Burtona354ddc2014-04-07 16:41:47 +0100473 unsigned char *buf;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200474 int pkt_len = 0;
Paul Burton6fb49e42014-04-07 16:41:48 +0100475 u16 status, err_status;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200476
477 while (1) {
Paul Burtonf1ae3822014-04-07 16:41:46 +0100478 entry = &lp->uc->rx_ring[lp->cur_rx];
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200479 /*
480 * If we own the next entry, it's a new packet. Send it up.
481 */
Paul Burton6fb49e42014-04-07 16:41:48 +0100482 status = readw(&entry->status);
Paul Burton6011dab2013-11-08 11:18:43 +0000483 if ((status & 0x8000) != 0)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200484 break;
Paul Burton6fb49e42014-04-07 16:41:48 +0100485 err_status = status >> 8;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200486
Paul Burton6fb49e42014-04-07 16:41:48 +0100487 if (err_status != 0x03) { /* There was an error. */
Paul Burton6011dab2013-11-08 11:18:43 +0000488 printf("%s: Rx%d", dev->name, lp->cur_rx);
Paul Burton6fb49e42014-04-07 16:41:48 +0100489 PCNET_DEBUG1(" (status=0x%x)", err_status);
490 if (err_status & 0x20)
Paul Burton6011dab2013-11-08 11:18:43 +0000491 printf(" Frame");
Paul Burton6fb49e42014-04-07 16:41:48 +0100492 if (err_status & 0x10)
Paul Burton6011dab2013-11-08 11:18:43 +0000493 printf(" Overflow");
Paul Burton6fb49e42014-04-07 16:41:48 +0100494 if (err_status & 0x08)
Paul Burton6011dab2013-11-08 11:18:43 +0000495 printf(" CRC");
Paul Burton6fb49e42014-04-07 16:41:48 +0100496 if (err_status & 0x04)
Paul Burton6011dab2013-11-08 11:18:43 +0000497 printf(" Fifo");
498 printf(" Error\n");
Paul Burton6fb49e42014-04-07 16:41:48 +0100499 status &= 0x03ff;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200500
501 } else {
Paul Burton6fb49e42014-04-07 16:41:48 +0100502 pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200503 if (pkt_len < 60) {
Paul Burton6011dab2013-11-08 11:18:43 +0000504 printf("%s: Rx%d: invalid packet length %d\n",
505 dev->name, lp->cur_rx, pkt_len);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200506 } else {
Paul Burtona354ddc2014-04-07 16:41:47 +0100507 buf = (*lp->rx_buf)[lp->cur_rx];
508 invalidate_dcache_range((unsigned long)buf,
509 (unsigned long)buf + pkt_len);
510 NetReceive(buf, pkt_len);
Paul Burton6011dab2013-11-08 11:18:43 +0000511 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
Paul Burtona354ddc2014-04-07 16:41:47 +0100512 lp->cur_rx, pkt_len, buf);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200513 }
514 }
Paul Burton6fb49e42014-04-07 16:41:48 +0100515
516 status |= 0x8000;
517 writew(status, &entry->status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200518
519 if (++lp->cur_rx >= RX_RING_SIZE)
520 lp->cur_rx = 0;
521 }
522 return pkt_len;
523}
524
Paul Burton6011dab2013-11-08 11:18:43 +0000525static void pcnet_halt(struct eth_device *dev)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200526{
527 int i;
528
Paul Burton6011dab2013-11-08 11:18:43 +0000529 PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200530
531 /* Reset the PCnet controller */
Paul Burton6011dab2013-11-08 11:18:43 +0000532 pcnet_reset(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200533
534 /* Wait for Stop bit */
535 for (i = 1000; i > 0; i--) {
Paul Burton6011dab2013-11-08 11:18:43 +0000536 if (pcnet_read_csr(dev, 0) & 0x4)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200537 break;
Paul Burton6011dab2013-11-08 11:18:43 +0000538 udelay(10);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200539 }
Paul Burton6011dab2013-11-08 11:18:43 +0000540 if (i <= 0)
541 printf("%s: TIMEOUT: controller reset failed\n", dev->name);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200542}