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wdenkf8cac652002-08-26 22:36:39 +00001/*
Wolfgang Denk7c803be2008-09-16 18:02:19 +02002 * (C) Copyright 2000-2008
wdenkf8cac652002-08-26 22:36:39 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf8cac652002-08-26 22:36:39 +00006 */
7
8#include <common.h>
Heiko Schocher6ed3b9d2010-02-09 15:50:21 +01009#include <hwconfig.h>
wdenkf8cac652002-08-26 22:36:39 +000010#include <mpc8xx.h>
wdenk1c437712004-01-16 00:30:56 +000011#ifdef CONFIG_PS2MULT
12#include <ps2mult.h>
13#endif
wdenkf8cac652002-08-26 22:36:39 +000014
Heiko Schocher6ed3b9d2010-02-09 15:50:21 +010015#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
16#include <libfdt.h>
17#endif
18
Wolfgang Denk7c803be2008-09-16 18:02:19 +020019extern flash_info_t flash_info[]; /* FLASH chips info */
20
Wolfgang Denkd87080b2006-03-31 18:32:53 +020021DECLARE_GLOBAL_DATA_PTR;
wdenkf8cac652002-08-26 22:36:39 +000022
23static long int dram_size (long int, long int *, long int);
24
wdenkf8cac652002-08-26 22:36:39 +000025#define _NOT_USED_ 0xFFFFFFFF
26
Jens Gehrlein22d1a562007-09-26 17:55:54 +020027/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
wdenkf8cac652002-08-26 22:36:39 +000028const uint sdram_table[] =
29{
30 /*
31 * Single Read. (Offset 0 in UPMA RAM)
32 */
33 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
34 0x1FF5FC47, /* last */
35 /*
36 * SDRAM Initialization (offset 5 in UPMA RAM)
37 *
38 * This is no UPM entry point. The following definition uses
39 * the remaining space to establish an initialization
40 * sequence, which is executed by a RUN command.
41 *
42 */
43 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
44 /*
45 * Burst Read. (Offset 8 in UPMA RAM)
46 */
47 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
48 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
49 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
50 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
51 /*
52 * Single Write. (Offset 18 in UPMA RAM)
53 */
Jens Gehrlein22d1a562007-09-26 17:55:54 +020054 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
55 0x1FF5FC47, /* last */
56 _NOT_USED_, _NOT_USED_, _NOT_USED_,
wdenkf8cac652002-08-26 22:36:39 +000057 /*
58 * Burst Write. (Offset 20 in UPMA RAM)
59 */
60 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
Jens Gehrlein22d1a562007-09-26 17:55:54 +020061 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
wdenkf8cac652002-08-26 22:36:39 +000062 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
63 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
64 /*
65 * Refresh (Offset 30 in UPMA RAM)
66 */
67 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
68 0xFFFFFC84, 0xFFFFFC07, /* last */
69 _NOT_USED_, _NOT_USED_,
70 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
71 /*
72 * Exception. (Offset 3c in UPMA RAM)
73 */
Jens Gehrlein22d1a562007-09-26 17:55:54 +020074 0xFFFFFC07, /* last */
wdenkf8cac652002-08-26 22:36:39 +000075 _NOT_USED_, _NOT_USED_, _NOT_USED_,
76};
77
78/* ------------------------------------------------------------------------- */
79
80
81/*
82 * Check Board Identity:
83 *
84 * Test TQ ID string (TQM8xx...)
85 * If present, check for "L" type (no second DRAM bank),
86 * otherwise "L" type is assumed as default.
87 *
wdenkd4ca31c2004-01-02 14:00:00 +000088 * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
wdenkf8cac652002-08-26 22:36:39 +000089 */
90
91int checkboard (void)
92{
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000093 char buf[64];
94 int i;
95 int l = getenv_f("serial#", buf, sizeof(buf));
wdenkf8cac652002-08-26 22:36:39 +000096
97 puts ("Board: ");
98
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000099 if (l < 0 || strncmp(buf, "TQM8", 4)) {
wdenkf8cac652002-08-26 22:36:39 +0000100 puts ("### No HW ID - assuming TQM8xxL\n");
101 return (0);
102 }
103
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000104 if ((buf[6] == 'L')) { /* a TQM8xxL type */
wdenkf8cac652002-08-26 22:36:39 +0000105 gd->board_type = 'L';
106 }
107
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000108 if ((buf[6] == 'M')) { /* a TQM8xxM type */
wdenkd4ca31c2004-01-02 14:00:00 +0000109 gd->board_type = 'M';
110 }
111
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000112 if ((buf[6] == 'D')) { /* a TQM885D type */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200113 gd->board_type = 'D';
114 }
115
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000116 for (i = 0; i < l; ++i) {
117 if (buf[i] == ' ')
wdenkf8cac652002-08-26 22:36:39 +0000118 break;
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000119 putc (buf[i]);
wdenkf8cac652002-08-26 22:36:39 +0000120 }
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200121#ifdef CONFIG_VIRTLAB2
122 puts (" (Virtlab2)");
123#endif
wdenkf8cac652002-08-26 22:36:39 +0000124 putc ('\n');
125
126 return (0);
127}
128
129/* ------------------------------------------------------------------------- */
130
Becky Bruce9973e3c2008-06-09 16:03:40 -0500131phys_size_t initdram (int board_type)
wdenkf8cac652002-08-26 22:36:39 +0000132{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkf8cac652002-08-26 22:36:39 +0000134 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenkc178d3d2004-01-24 20:25:54 +0000135 long int size8, size9, size10;
wdenkf8cac652002-08-26 22:36:39 +0000136 long int size_b0 = 0;
137 long int size_b1 = 0;
138
139 upmconfig (UPMA, (uint *) sdram_table,
140 sizeof (sdram_table) / sizeof (uint));
141
142 /*
143 * Preliminary prescaler for refresh (depends on number of
144 * banks): This value is selected for four cycles every 62.4 us
145 * with two SDRAM banks or four cycles every 31.2 us with one
146 * bank. It will be adjusted after memory sizing.
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
wdenkf8cac652002-08-26 22:36:39 +0000149
150 /*
151 * The following value is used as an address (i.e. opcode) for
152 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
153 * the port size is 32bit the SDRAM does NOT "see" the lower two
154 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
155 * MICRON SDRAMs:
156 * -> 0 00 010 0 010
157 * | | | | +- Burst Length = 4
158 * | | | +----- Burst Type = Sequential
159 * | | +------- CAS Latency = 2
160 * | +----------- Operating Mode = Standard
161 * +-------------- Write Burst Mode = Programmed Burst Length
162 */
163 memctl->memc_mar = 0x00000088;
164
165 /*
166 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
167 * preliminary addresses - these have to be modified after the
168 * SDRAM size has been determined.
169 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170 memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
171 memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
wdenkf8cac652002-08-26 22:36:39 +0000172
173#ifndef CONFIG_CAN_DRIVER
wdenkd4ca31c2004-01-02 14:00:00 +0000174 if ((board_type != 'L') &&
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200175 (board_type != 'M') &&
Martin Krause11d9eec2007-09-26 17:55:56 +0200176 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
178 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
wdenkf8cac652002-08-26 22:36:39 +0000179 }
180#endif /* CONFIG_CAN_DRIVER */
181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
wdenkf8cac652002-08-26 22:36:39 +0000183
184 udelay (200);
185
186 /* perform SDRAM initializsation sequence */
187
188 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
189 udelay (1);
190 memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
191 udelay (1);
192
193#ifndef CONFIG_CAN_DRIVER
wdenkd4ca31c2004-01-02 14:00:00 +0000194 if ((board_type != 'L') &&
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200195 (board_type != 'M') &&
Wolfgang Denkfc1840e2006-07-21 18:51:56 +0200196 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
wdenkf8cac652002-08-26 22:36:39 +0000197 memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
198 udelay (1);
199 memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
200 udelay (1);
201 }
202#endif /* CONFIG_CAN_DRIVER */
203
204 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
205
206 udelay (1000);
207
208 /*
209 * Check Bank 0 Memory Size for re-configuration
210 *
211 * try 8 column mode
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213 size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
wdenkd4ca31c2004-01-02 14:00:00 +0000214 debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000215
216 udelay (1000);
217
218 /*
219 * try 9 column mode
220 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221 size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
wdenkd4ca31c2004-01-02 14:00:00 +0000222 debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000223
wdenkc178d3d2004-01-24 20:25:54 +0000224 udelay(1000);
225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#if defined(CONFIG_SYS_MAMR_10COL)
wdenkc178d3d2004-01-24 20:25:54 +0000227 /*
228 * try 10 column mode
229 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230 size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
wdenkc178d3d2004-01-24 20:25:54 +0000231 debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
232#else
233 size10 = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#endif /* CONFIG_SYS_MAMR_10COL */
wdenkc178d3d2004-01-24 20:25:54 +0000235
236 if ((size8 < size10) && (size9 < size10)) {
237 size_b0 = size10;
238 } else if ((size8 < size9) && (size10 < size9)) {
wdenkf8cac652002-08-26 22:36:39 +0000239 size_b0 = size9;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240 memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
wdenkc178d3d2004-01-24 20:25:54 +0000241 udelay (500);
242 } else {
wdenkf8cac652002-08-26 22:36:39 +0000243 size_b0 = size8;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
wdenkf8cac652002-08-26 22:36:39 +0000245 udelay (500);
wdenkf8cac652002-08-26 22:36:39 +0000246 }
wdenkd4ca31c2004-01-02 14:00:00 +0000247 debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000248
249#ifndef CONFIG_CAN_DRIVER
wdenkd4ca31c2004-01-02 14:00:00 +0000250 if ((board_type != 'L') &&
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200251 (board_type != 'M') &&
Martin Krause11d9eec2007-09-26 17:55:56 +0200252 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
wdenkf8cac652002-08-26 22:36:39 +0000253 /*
254 * Check Bank 1 Memory Size
255 * use current column settings
256 * [9 column SDRAM may also be used in 8 column mode,
257 * but then only half the real size will be used.]
258 */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200259 size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
wdenkd4ca31c2004-01-02 14:00:00 +0000260 SDRAM_MAX_SIZE);
261 debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000262 } else {
263 size_b1 = 0;
264 }
wdenkd4ca31c2004-01-02 14:00:00 +0000265#endif /* CONFIG_CAN_DRIVER */
wdenkf8cac652002-08-26 22:36:39 +0000266
267 udelay (1000);
268
269 /*
270 * Adjust refresh rate depending on SDRAM type, both banks
271 * For types > 128 MBit leave it at the current (fast) rate
272 */
273 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
274 /* reduce to 15.6 us (62.4 us / quad) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
wdenkf8cac652002-08-26 22:36:39 +0000276 udelay (1000);
277 }
278
279 /*
280 * Final mapping: map bigger bank first
281 */
282 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
283
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284 memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
285 memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
wdenkf8cac652002-08-26 22:36:39 +0000286
287 if (size_b0 > 0) {
288 /*
289 * Position Bank 0 immediately above Bank 1
290 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
292 memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
wdenkc178d3d2004-01-24 20:25:54 +0000293 + size_b1;
wdenkf8cac652002-08-26 22:36:39 +0000294 } else {
295 unsigned long reg;
296
297 /*
298 * No bank 0
299 *
300 * invalidate bank
301 */
302 memctl->memc_br2 = 0;
303
304 /* adjust refresh rate depending on SDRAM type, one bank */
305 reg = memctl->memc_mptpr;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306 reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
wdenkf8cac652002-08-26 22:36:39 +0000307 memctl->memc_mptpr = reg;
308 }
309
310 } else { /* SDRAM Bank 0 is bigger - map first */
311
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
wdenkf8cac652002-08-26 22:36:39 +0000313 memctl->memc_br2 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314 (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
wdenkf8cac652002-08-26 22:36:39 +0000315
316 if (size_b1 > 0) {
317 /*
318 * Position Bank 1 immediately above Bank 0
319 */
320 memctl->memc_or3 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321 ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
wdenkf8cac652002-08-26 22:36:39 +0000322 memctl->memc_br3 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323 ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
wdenkf8cac652002-08-26 22:36:39 +0000324 + size_b0;
325 } else {
326 unsigned long reg;
327
328#ifndef CONFIG_CAN_DRIVER
329 /*
330 * No bank 1
331 *
332 * invalidate bank
333 */
334 memctl->memc_br3 = 0;
335#endif /* CONFIG_CAN_DRIVER */
336
337 /* adjust refresh rate depending on SDRAM type, one bank */
338 reg = memctl->memc_mptpr;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339 reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
wdenkf8cac652002-08-26 22:36:39 +0000340 memctl->memc_mptpr = reg;
341 }
342 }
343
344 udelay (10000);
345
346#ifdef CONFIG_CAN_DRIVER
Jens Gehrlein9d292502007-09-26 17:55:54 +0200347 /* UPM initialization for CAN @ CLKOUT <= 66 MHz */
348
wdenkf8cac652002-08-26 22:36:39 +0000349 /* Initialize OR3 / BR3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350 memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
351 memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
wdenkf8cac652002-08-26 22:36:39 +0000352
353 /* Initialize MBMR */
wdenkfd3103b2003-11-25 16:55:19 +0000354 memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
wdenkf8cac652002-08-26 22:36:39 +0000355
356 /* Initialize UPMB for CAN: single read */
Jens Gehrlein9d292502007-09-26 17:55:54 +0200357 memctl->memc_mdr = 0xFFFFCC04;
wdenkf8cac652002-08-26 22:36:39 +0000358 memctl->memc_mcr = 0x0100 | UPMB;
359
360 memctl->memc_mdr = 0x0FFFD004;
361 memctl->memc_mcr = 0x0101 | UPMB;
362
363 memctl->memc_mdr = 0x0FFFC000;
364 memctl->memc_mcr = 0x0102 | UPMB;
365
366 memctl->memc_mdr = 0x3FFFC004;
367 memctl->memc_mcr = 0x0103 | UPMB;
368
Jens Gehrlein9d292502007-09-26 17:55:54 +0200369 memctl->memc_mdr = 0xFFFFDC07;
wdenkf8cac652002-08-26 22:36:39 +0000370 memctl->memc_mcr = 0x0104 | UPMB;
371
372 /* Initialize UPMB for CAN: single write */
Jens Gehrlein9d292502007-09-26 17:55:54 +0200373 memctl->memc_mdr = 0xFFFCCC04;
wdenkf8cac652002-08-26 22:36:39 +0000374 memctl->memc_mcr = 0x0118 | UPMB;
375
Jens Gehrlein9d292502007-09-26 17:55:54 +0200376 memctl->memc_mdr = 0xCFFCDC04;
wdenkf8cac652002-08-26 22:36:39 +0000377 memctl->memc_mcr = 0x0119 | UPMB;
378
Jens Gehrlein9d292502007-09-26 17:55:54 +0200379 memctl->memc_mdr = 0x3FFCC000;
wdenkf8cac652002-08-26 22:36:39 +0000380 memctl->memc_mcr = 0x011A | UPMB;
381
Jens Gehrlein9d292502007-09-26 17:55:54 +0200382 memctl->memc_mdr = 0xFFFCC004;
wdenkf8cac652002-08-26 22:36:39 +0000383 memctl->memc_mcr = 0x011B | UPMB;
384
Jens Gehrlein9d292502007-09-26 17:55:54 +0200385 memctl->memc_mdr = 0xFFFDC405;
wdenkf8cac652002-08-26 22:36:39 +0000386 memctl->memc_mcr = 0x011C | UPMB;
387#endif /* CONFIG_CAN_DRIVER */
388
wdenkbdccc4f2003-08-05 17:43:17 +0000389#ifdef CONFIG_ISP1362_USB
390 /* Initialize OR5 / BR5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391 memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362;
392 memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362;
wdenkbdccc4f2003-08-05 17:43:17 +0000393#endif /* CONFIG_ISP1362_USB */
wdenkf8cac652002-08-26 22:36:39 +0000394 return (size_b0 + size_b1);
395}
396
397/* ------------------------------------------------------------------------- */
398
399/*
400 * Check memory range for valid RAM. A simple memory test determines
401 * the actually available RAM size between addresses `base' and
402 * `base + maxsize'. Some (not all) hardware errors are detected:
403 * - short between address lines
404 * - short between data lines
405 */
406
wdenkd4ca31c2004-01-02 14:00:00 +0000407static long int dram_size (long int mamr_value, long int *base, long int maxsize)
wdenkf8cac652002-08-26 22:36:39 +0000408{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkf8cac652002-08-26 22:36:39 +0000410 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenkf8cac652002-08-26 22:36:39 +0000411
412 memctl->memc_mamr = mamr_value;
413
wdenkc83bf6a2004-01-06 22:38:14 +0000414 return (get_ram_size(base, maxsize));
wdenkf8cac652002-08-26 22:36:39 +0000415}
416
417/* ------------------------------------------------------------------------- */
wdenk1c437712004-01-16 00:30:56 +0000418
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200419#ifdef CONFIG_MISC_INIT_R
Mike Frysinger9c150102009-02-11 20:09:52 -0500420extern void load_sernum_ethaddr(void);
wdenk1c437712004-01-16 00:30:56 +0000421int misc_init_r (void)
422{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200424 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenk1c437712004-01-16 00:30:56 +0000425
Mike Frysinger9c150102009-02-11 20:09:52 -0500426 load_sernum_ethaddr();
427
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200429 int scy, trlx, flash_or_timing, clk_diff;
430
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431 scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
432 if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200433 trlx = OR_TRLX;
434 scy *= 2;
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200435 } else {
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200436 trlx = 0;
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200437 }
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200438
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200439 /*
440 * We assume that each 10MHz of bus clock require 1-clk SCY
441 * adjustment.
442 */
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200443 clk_diff = (gd->bus_clk / 1000000) - 50;
444
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200445 /*
446 * We need proper rounding here. This is what the "+5" and "-5"
447 * are here for.
448 */
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200449 if (clk_diff >= 0)
450 scy += (clk_diff + 5) / 10;
451 else
452 scy += (clk_diff - 5) / 10;
453
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200454 /*
455 * For bus frequencies above 50MHz, we want to use relaxed timing
456 * (OR_TRLX).
457 */
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200458 if (gd->bus_clk >= 50000000)
459 trlx = OR_TRLX;
460 else
461 trlx = 0;
462
463 if (trlx)
464 scy /= 2;
465
466 if (scy > 0xf)
467 scy = 0xf;
468 if (scy < 1)
469 scy = 1;
470
471 flash_or_timing = (scy << 4) | trlx |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472 (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200473
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200474 memctl->memc_or0 =
475 flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200476#else
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200477 memctl->memc_or0 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478 CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200479#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480 memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200481
482 debug ("## BR0: 0x%08x OR0: 0x%08x\n",
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200483 memctl->memc_br0, memctl->memc_or0);
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200484
485 if (flash_info[1].size) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200487 memctl->memc_or1 = flash_or_timing |
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200488 (-flash_info[1].size & 0xFFFF8000);
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200489#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490 memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200491 (-flash_info[1].size & 0xFFFF8000);
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200492#endif
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200493 memctl->memc_br1 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494 ((CONFIG_SYS_FLASH_BASE +
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200495 flash_info[0].
496 size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200497
498 debug ("## BR1: 0x%08x OR1: 0x%08x\n",
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200499 memctl->memc_br1, memctl->memc_or1);
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200500 } else {
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200501 memctl->memc_br1 = 0; /* invalidate bank */
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200502
503 debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n",
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200504 memctl->memc_br1, memctl->memc_or1);
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200505 }
506
507# ifdef CONFIG_IDE_LED
wdenk1c437712004-01-16 00:30:56 +0000508 /* Configure PA15 as output port */
509 immap->im_ioport.iop_padir |= 0x0001;
510 immap->im_ioport.iop_paodr |= 0x0001;
511 immap->im_ioport.iop_papar &= ~0x0001;
512 immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
wdenkcfca5e62004-08-01 13:09:47 +0000513# endif
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200514
515#ifdef CONFIG_NSCU
516 /* wake up ethernet module */
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200517 immap->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */
518 immap->im_ioport.iop_pcdir |= 0x0004; /* output */
519 immap->im_ioport.iop_pcso &= ~0x0004; /* for clarity */
520 immap->im_ioport.iop_pcdat |= 0x0004; /* enable */
521#endif /* CONFIG_NSCU */
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200522
wdenk1c437712004-01-16 00:30:56 +0000523 return (0);
524}
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200525#endif /* CONFIG_MISC_INIT_R */
526
wdenk1c437712004-01-16 00:30:56 +0000527
wdenkcfca5e62004-08-01 13:09:47 +0000528# ifdef CONFIG_IDE_LED
wdenk1c437712004-01-16 00:30:56 +0000529void ide_led (uchar led, uchar status)
530{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200531 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk1c437712004-01-16 00:30:56 +0000532
533 /* We have one led for both pcmcia slots */
534 if (status) { /* led on */
535 immap->im_ioport.iop_padat |= 0x0001;
536 } else {
537 immap->im_ioport.iop_padat &= ~0x0001;
538 }
539}
wdenkcfca5e62004-08-01 13:09:47 +0000540# endif
wdenkcfca5e62004-08-01 13:09:47 +0000541
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200542#ifdef CONFIG_LCD_INFO
543#include <lcd.h>
Anatolij Gustschin1450c4a2008-11-03 15:30:34 +0100544#include <version.h>
Peter Tyser561858e2008-11-03 09:30:59 -0600545#include <timestamp.h>
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200546
547void lcd_show_board_info(void)
548{
Anatolij Gustschin1450c4a2008-11-03 15:30:34 +0100549 char temp[32];
550
Peter Tyser561858e2008-11-03 09:30:59 -0600551 lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200552 lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
553 lcd_printf (" Wolfgang DENK, wd@denx.de\n");
554#ifdef CONFIG_LCD_INFO_BELOW_LOGO
555 lcd_printf ("MPC823 CPU at %s MHz\n",
556 strmhz(temp, gd->cpu_clk));
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200557 lcd_printf (" %ld MB RAM, %ld MB Flash\n",
558 gd->ram_size >> 20,
559 gd->bd->bi_flashsize >> 20 );
560#else
561 /* leave one blank line */
562 lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n",
563 strmhz(temp, gd->cpu_clk),
564 gd->ram_size >> 20,
565 gd->bd->bi_flashsize >> 20 );
566#endif /* CONFIG_LCD_INFO_BELOW_LOGO */
567}
568#endif /* CONFIG_LCD_INFO */
569
Heiko Schocher6ed3b9d2010-02-09 15:50:21 +0100570/*
571 * Device Tree Support
572 */
573#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
574int fdt_set_node_and_value (void *blob,
575 char *nodename,
576 char *regname,
577 void *var,
578 int size)
579{
580 int ret = 0;
581 int nodeoffset = 0;
582
583 nodeoffset = fdt_path_offset (blob, nodename);
584 if (nodeoffset >= 0) {
585 ret = fdt_setprop (blob, nodeoffset, regname, var,
586 size);
587 if (ret < 0) {
588 printf("ft_blob_update(): "
589 "cannot set %s/%s property; err: %s\n",
590 nodename, regname, fdt_strerror (ret));
591 }
592 } else {
593 printf("ft_blob_update(): "
594 "cannot find %s node err:%s\n",
595 nodename, fdt_strerror (nodeoffset));
596 }
597 return ret;
598}
599
600int fdt_del_node_name (void *blob, char *nodename)
601{
602 int ret = 0;
603 int nodeoffset = 0;
604
605 nodeoffset = fdt_path_offset (blob, nodename);
606 if (nodeoffset >= 0) {
607 ret = fdt_del_node (blob, nodeoffset);
608 if (ret < 0) {
609 printf("%s: cannot delete %s; err: %s\n",
610 __func__, nodename, fdt_strerror (ret));
611 }
612 } else {
613 printf("%s: cannot find %s node err:%s\n",
614 __func__, nodename, fdt_strerror (nodeoffset));
615 }
616 return ret;
617}
618
619int fdt_del_prop_name (void *blob, char *nodename, char *propname)
620{
621 int ret = 0;
622 int nodeoffset = 0;
623
624 nodeoffset = fdt_path_offset (blob, nodename);
625 if (nodeoffset >= 0) {
626 ret = fdt_delprop (blob, nodeoffset, propname);
627 if (ret < 0) {
628 printf("%s: cannot delete %s %s; err: %s\n",
629 __func__, nodename, propname,
630 fdt_strerror (ret));
631 }
632 } else {
633 printf("%s: cannot find %s node err:%s\n",
634 __func__, nodename, fdt_strerror (nodeoffset));
635 }
636 return ret;
637}
638
639/*
640 * update "brg" property in the blob
641 */
642void ft_blob_update (void *blob, bd_t *bd)
643{
644 uchar enetaddr[6];
645 ulong brg_data = 0;
646
647 /* BRG */
648 brg_data = cpu_to_be32(bd->bi_busfreq);
649 fdt_set_node_and_value(blob,
650 "/soc/cpm", "brg-frequency",
651 &brg_data, sizeof(brg_data));
652
653 /* MAC addr */
654 if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
655 fdt_set_node_and_value(blob,
656 "ethernet0", "local-mac-address",
657 enetaddr, sizeof(u8) * 6);
658 }
659
660 if (hwconfig_arg_cmp("fec", "off")) {
661 /* no FEC on this plattform, delete DTS nodes */
662 fdt_del_node_name (blob, "ethernet1");
663 fdt_del_node_name (blob, "mdio1");
664 /* also the aliases entries */
665 fdt_del_prop_name (blob, "/aliases", "ethernet1");
666 fdt_del_prop_name (blob, "/aliases", "mdio1");
667 } else {
668 /* adjust local-mac-address for FEC ethernet */
669 if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
670 fdt_set_node_and_value(blob,
671 "ethernet1", "local-mac-address",
672 enetaddr, sizeof(u8) * 6);
673 }
674 }
675}
676
677void ft_board_setup(void *blob, bd_t *bd)
678{
679 ft_cpu_setup(blob, bd);
680 ft_blob_update(blob, bd);
681}
682#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
683
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100684/* ---------------------------------------------------------------------------- */
685/* TK885D specific initializaion */
686/* ---------------------------------------------------------------------------- */
687#ifdef CONFIG_TK885D
688#include <miiphy.h>
689int last_stage_init(void)
690{
691 const unsigned char phy[] = {CONFIG_FEC1_PHY, CONFIG_FEC2_PHY};
692 unsigned short reg;
693 int ret, i = 100;
694 char *s;
695
696 mii_init();
697 /* Without this delay 0xff is read from the UART buffer later in
698 * abortboot() and autoboot is aborted */
699 udelay(10000);
700 while (tstc() && i--)
701 (void)getc();
702
703 /* Check if auto-negotiation is prohibited */
704 s = getenv("phy_auto_nego");
705
706 if (!s || !strcmp(s, "on"))
707 /* Nothing to do - autonegotiation by default */
708 return 0;
709
710 for (i = 0; i < 2; i++) {
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500711 ret = miiphy_read("FEC", phy[i], MII_BMCR, &reg);
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100712 if (ret) {
713 printf("Cannot read BMCR on PHY %d\n", phy[i]);
714 return 0;
715 }
716 /* Auto-negotiation off, hard set full duplex, 100Mbps */
Heiko Schocher48690d82010-07-20 17:45:02 +0200717 ret = miiphy_write("FEC", phy[i],
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500718 MII_BMCR, (reg | BMCR_SPEED100 |
719 BMCR_FULLDPLX) & ~BMCR_ANENABLE);
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100720 if (ret) {
721 printf("Cannot write BMCR on PHY %d\n", phy[i]);
722 return 0;
723 }
724 }
725
726 return 0;
727}
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100728#endif