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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 3ba6a0f4f6a2381ad32930df6277930a3de577bc / . / arch / x86 / Kconfig
blob: ffcb4cb665968463746073f5c353702be42f55c5 [file] [log] [blame]
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]1menu "x86 architecture"
2 depends on X86
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]5 default "x86"
6
Masahiro Yamada45ccec82014-10-24 01:30:43 +0900[diff] [blame]7config USE_PRIVATE_LIBGCC
8 default y
9
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]10choice
11 prompt "Target select"
12
13config TARGET_COREBOOT
14 bool "Support coreboot"
Simon Glass8ef07572014-11-12 22:42:07 -0700[diff] [blame]15 help
16 This target is used for running U-Boot on top of Coreboot. In
17 this case Coreboot does the early inititalisation, and U-Boot
18 takes over once the RAM, video and CPU are fully running.
19 U-Boot is loaded as a fallback payload from Coreboot, in
20 Coreboot terminology. This method was used for the Chromebook
21 Pixel when launched.
22
23config TARGET_CHROMEBOOK_LINK
24 bool "Support Chromebook link"
25 help
26 This is the Chromebook Pixel released in 2013. It uses an Intel
27 i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
28 SDRAM. It has a Panther Point platform controller hub, PCIe
29 WiFi and Bluetooth. It also includes a 720p webcam, USB SD
30 reader, microphone and speakers, display port and 32GB SATA
31 solid state drive. There is a Chrome OS EC connected on LPC,
32 and it provides a 2560x1700 high resolution touch-enabled LCD
33 display.
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]34
Bin Meng58f542d2014-12-17 15:50:40 +0800[diff] [blame]35config TARGET_CROWNBAY
36 bool "Support Intel Crown Bay CRB"
37 help
38 This is the Intel Crown Bay Customer Reference Board. It contains
39 the Intel Atom Processor E6xx populated on the COM Express module
40 with 1GB DDR2 soldered down memory and a carrier board with the
41 Intel Platform Controller Hub EG20T, other system components and
42 peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
43
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]44endchoice
45
Simon Glass70a09c62014-11-12 22:42:10 -0700[diff] [blame]46config RAMBASE
47 hex
48 default 0x100000
49
Simon Glass70a09c62014-11-12 22:42:10 -0700[diff] [blame]50config XIP_ROM_SIZE
51 hex
Simon Glassbbd43d62015-01-01 16:17:54 -0700[diff] [blame]52 default ROM_SIZE
Simon Glass70a09c62014-11-12 22:42:10 -0700[diff] [blame]53
54config CPU_ADDR_BITS
55 int
56 default 36
57
Simon Glass65dd74a2014-11-12 22:42:28 -0700[diff] [blame]58config HPET_ADDRESS
59 hex
60 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
61
62config SMM_TSEG
63 bool
64 default n
65
66config SMM_TSEG_SIZE
67 hex
68
Bin Meng64542f42014-12-12 21:05:19 +0800[diff] [blame]69config BOARD_ROMSIZE_KB_512
70 bool
71config BOARD_ROMSIZE_KB_1024
72 bool
73config BOARD_ROMSIZE_KB_2048
74 bool
75config BOARD_ROMSIZE_KB_4096
76 bool
77config BOARD_ROMSIZE_KB_8192
78 bool
79config BOARD_ROMSIZE_KB_16384
80 bool
81
82choice
83 prompt "ROM chip size"
84 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
85 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
86 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
87 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
88 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
89 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
90 help
91 Select the size of the ROM chip you intend to flash U-Boot on.
92
93 The build system will take care of creating a u-boot.rom file
94 of the matching size.
95
96config UBOOT_ROMSIZE_KB_512
97 bool "512 KB"
98 help
99 Choose this option if you have a 512 KB ROM chip.
100
101config UBOOT_ROMSIZE_KB_1024
102 bool "1024 KB (1 MB)"
103 help
104 Choose this option if you have a 1024 KB (1 MB) ROM chip.
105
106config UBOOT_ROMSIZE_KB_2048
107 bool "2048 KB (2 MB)"
108 help
109 Choose this option if you have a 2048 KB (2 MB) ROM chip.
110
111config UBOOT_ROMSIZE_KB_4096
112 bool "4096 KB (4 MB)"
113 help
114 Choose this option if you have a 4096 KB (4 MB) ROM chip.
115
116config UBOOT_ROMSIZE_KB_8192
117 bool "8192 KB (8 MB)"
118 help
119 Choose this option if you have a 8192 KB (8 MB) ROM chip.
120
121config UBOOT_ROMSIZE_KB_16384
122 bool "16384 KB (16 MB)"
123 help
124 Choose this option if you have a 16384 KB (16 MB) ROM chip.
125
126endchoice
127
128# Map the config names to an integer (KB).
129config UBOOT_ROMSIZE_KB
130 int
131 default 512 if UBOOT_ROMSIZE_KB_512
132 default 1024 if UBOOT_ROMSIZE_KB_1024
133 default 2048 if UBOOT_ROMSIZE_KB_2048
134 default 4096 if UBOOT_ROMSIZE_KB_4096
135 default 8192 if UBOOT_ROMSIZE_KB_8192
136 default 16384 if UBOOT_ROMSIZE_KB_16384
137
138# Map the config names to a hex value (bytes).
Simon Glassfce7b272014-11-12 22:42:08 -0700[diff] [blame]139config ROM_SIZE
140 hex
Bin Meng64542f42014-12-12 21:05:19 +0800[diff] [blame]141 default 0x80000 if UBOOT_ROMSIZE_KB_512
142 default 0x100000 if UBOOT_ROMSIZE_KB_1024
143 default 0x200000 if UBOOT_ROMSIZE_KB_2048
144 default 0x400000 if UBOOT_ROMSIZE_KB_4096
145 default 0x800000 if UBOOT_ROMSIZE_KB_8192
146 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
147 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
Simon Glassfce7b272014-11-12 22:42:08 -0700[diff] [blame]148
149config HAVE_INTEL_ME
150 bool "Platform requires Intel Management Engine"
151 help
152 Newer higher-end devices have an Intel Management Engine (ME)
153 which is a very large binary blob (typically 1.5MB) which is
154 required for the platform to work. This enforces a particular
155 SPI flash format. You will need to supply the me.bin file in
156 your board directory.
157
Simon Glass65dd74a2014-11-12 22:42:28 -0700[diff] [blame]158config X86_RAMTEST
159 bool "Perform a simple RAM test after SDRAM initialisation"
160 help
161 If there is something wrong with SDRAM then the platform will
162 often crash within U-Boot or the kernel. This option enables a
163 very simple RAM test that quickly checks whether the SDRAM seems
164 to work correctly. It is not exhaustive but can save time by
165 detecting obvious failures.
166
Simon Glass22465fc2014-11-14 20:56:30 -0700[diff] [blame]167config MARK_GRAPHICS_MEM_WRCOMB
168 bool "Mark graphics memory as write-combining."
169 default n
170 help
171 The graphics performance may increase if the graphics
172 memory is set as write-combining cache type. This option
173 enables marking the graphics memory as write-combining.
174
175menu "Display"
176
177config FRAMEBUFFER_SET_VESA_MODE
178 prompt "Set framebuffer graphics resolution"
179 bool
180 help
181 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
182
183choice
184 prompt "framebuffer graphics resolution"
185 default FRAMEBUFFER_VESA_MODE_117
186 depends on FRAMEBUFFER_SET_VESA_MODE
187 help
188 This option sets the resolution used for the coreboot framebuffer (and
189 bootsplash screen).
190
191config FRAMEBUFFER_VESA_MODE_100
192 bool "640x400 256-color"
193
194config FRAMEBUFFER_VESA_MODE_101
195 bool "640x480 256-color"
196
197config FRAMEBUFFER_VESA_MODE_102
198 bool "800x600 16-color"
199
200config FRAMEBUFFER_VESA_MODE_103
201 bool "800x600 256-color"
202
203config FRAMEBUFFER_VESA_MODE_104
204 bool "1024x768 16-color"
205
206config FRAMEBUFFER_VESA_MODE_105
207 bool "1024x7686 256-color"
208
209config FRAMEBUFFER_VESA_MODE_106
210 bool "1280x1024 16-color"
211
212config FRAMEBUFFER_VESA_MODE_107
213 bool "1280x1024 256-color"
214
215config FRAMEBUFFER_VESA_MODE_108
216 bool "80x60 text"
217
218config FRAMEBUFFER_VESA_MODE_109
219 bool "132x25 text"
220
221config FRAMEBUFFER_VESA_MODE_10A
222 bool "132x43 text"
223
224config FRAMEBUFFER_VESA_MODE_10B
225 bool "132x50 text"
226
227config FRAMEBUFFER_VESA_MODE_10C
228 bool "132x60 text"
229
230config FRAMEBUFFER_VESA_MODE_10D
231 bool "320x200 32k-color (1:5:5:5)"
232
233config FRAMEBUFFER_VESA_MODE_10E
234 bool "320x200 64k-color (5:6:5)"
235
236config FRAMEBUFFER_VESA_MODE_10F
237 bool "320x200 16.8M-color (8:8:8)"
238
239config FRAMEBUFFER_VESA_MODE_110
240 bool "640x480 32k-color (1:5:5:5)"
241
242config FRAMEBUFFER_VESA_MODE_111
243 bool "640x480 64k-color (5:6:5)"
244
245config FRAMEBUFFER_VESA_MODE_112
246 bool "640x480 16.8M-color (8:8:8)"
247
248config FRAMEBUFFER_VESA_MODE_113
249 bool "800x600 32k-color (1:5:5:5)"
250
251config FRAMEBUFFER_VESA_MODE_114
252 bool "800x600 64k-color (5:6:5)"
253
254config FRAMEBUFFER_VESA_MODE_115
255 bool "800x600 16.8M-color (8:8:8)"
256
257config FRAMEBUFFER_VESA_MODE_116
258 bool "1024x768 32k-color (1:5:5:5)"
259
260config FRAMEBUFFER_VESA_MODE_117
261 bool "1024x768 64k-color (5:6:5)"
262
263config FRAMEBUFFER_VESA_MODE_118
264 bool "1024x768 16.8M-color (8:8:8)"
265
266config FRAMEBUFFER_VESA_MODE_119
267 bool "1280x1024 32k-color (1:5:5:5)"
268
269config FRAMEBUFFER_VESA_MODE_11A
270 bool "1280x1024 64k-color (5:6:5)"
271
272config FRAMEBUFFER_VESA_MODE_11B
273 bool "1280x1024 16.8M-color (8:8:8)"
274
275config FRAMEBUFFER_VESA_MODE_USER
276 bool "Manually select VESA mode"
277
278endchoice
279
280# Map the config names to an integer (KB).
281config FRAMEBUFFER_VESA_MODE
282 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
283 hex
284 default 0x100 if FRAMEBUFFER_VESA_MODE_100
285 default 0x101 if FRAMEBUFFER_VESA_MODE_101
286 default 0x102 if FRAMEBUFFER_VESA_MODE_102
287 default 0x103 if FRAMEBUFFER_VESA_MODE_103
288 default 0x104 if FRAMEBUFFER_VESA_MODE_104
289 default 0x105 if FRAMEBUFFER_VESA_MODE_105
290 default 0x106 if FRAMEBUFFER_VESA_MODE_106
291 default 0x107 if FRAMEBUFFER_VESA_MODE_107
292 default 0x108 if FRAMEBUFFER_VESA_MODE_108
293 default 0x109 if FRAMEBUFFER_VESA_MODE_109
294 default 0x10A if FRAMEBUFFER_VESA_MODE_10A
295 default 0x10B if FRAMEBUFFER_VESA_MODE_10B
296 default 0x10C if FRAMEBUFFER_VESA_MODE_10C
297 default 0x10D if FRAMEBUFFER_VESA_MODE_10D
298 default 0x10E if FRAMEBUFFER_VESA_MODE_10E
299 default 0x10F if FRAMEBUFFER_VESA_MODE_10F
300 default 0x110 if FRAMEBUFFER_VESA_MODE_110
301 default 0x111 if FRAMEBUFFER_VESA_MODE_111
302 default 0x112 if FRAMEBUFFER_VESA_MODE_112
303 default 0x113 if FRAMEBUFFER_VESA_MODE_113
304 default 0x114 if FRAMEBUFFER_VESA_MODE_114
305 default 0x115 if FRAMEBUFFER_VESA_MODE_115
306 default 0x116 if FRAMEBUFFER_VESA_MODE_116
307 default 0x117 if FRAMEBUFFER_VESA_MODE_117
308 default 0x118 if FRAMEBUFFER_VESA_MODE_118
309 default 0x119 if FRAMEBUFFER_VESA_MODE_119
310 default 0x11A if FRAMEBUFFER_VESA_MODE_11A
311 default 0x11B if FRAMEBUFFER_VESA_MODE_11B
312 default 0x117 if FRAMEBUFFER_VESA_MODE_USER
313
314endmenu
315
Bin Meng3ba6a0f2015-01-06 22:14:14 +0800[diff] [blame^]316config TSC_CALIBRATION_BYPASS
317 bool "Bypass Time-Stamp Counter (TSC) calibration"
318 default n
319 help
320 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
321 running frequency via Model-Specific Register (MSR) and Programmable
322 Interval Timer (PIT). If the calibration does not work on your board,
323 select this option and provide a hardcoded TSC running frequency with
324 CONFIG_TSC_FREQ_IN_MHZ below.
325
326 Normally this option should be turned on in a simulation environment
327 like qemu.
328
329config TSC_FREQ_IN_MHZ
330 int "Time-Stamp Counter (TSC) running frequency in MHz"
331 depends on TSC_CALIBRATION_BYPASS
332 default 1000
333 help
334 The running frequency in MHz of Time-Stamp Counter (TSC).
335
Simon Glass8ef07572014-11-12 22:42:07 -0700[diff] [blame]336source "arch/x86/cpu/ivybridge/Kconfig"
337
Bin Meng58f542d2014-12-17 15:50:40 +0800[diff] [blame]338source "arch/x86/cpu/queensbay/Kconfig"
339
Simon Glassfe5b9b42014-11-12 22:42:29 -0700[diff] [blame]340source "board/coreboot/coreboot/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]341
Simon Glass8ef07572014-11-12 22:42:07 -0700[diff] [blame]342source "board/google/chromebook_link/Kconfig"
343
Bin Meng58f542d2014-12-17 15:50:40 +0800[diff] [blame]344source "board/intel/crownbay/Kconfig"
345
Masahiro Yamadadd840582014-07-30 14:08:14 +0900[diff] [blame]346endmenu