blob: 6e41ea6d01e5e5b5a5a89f4c5f74f806fc216396 [file] [log] [blame]
wdenk3e386912003-04-05 00:53:31 +00001/*
2 * Copyright (C) 2003 ETC s.r.o.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 * Written by Peter Figuli <peposh@etc.sk>, 2003.
20 *
21 */
22
23#include <common.h>
24#include <asm/arch/pxa-regs.h>
Marek Vasut3ba8bf72010-09-09 09:50:39 +020025#include <asm/io.h>
wdenk3e386912003-04-05 00:53:31 +000026
Wolfgang Denkd87080b2006-03-31 18:32:53 +020027DECLARE_GLOBAL_DATA_PTR;
wdenk3e386912003-04-05 00:53:31 +000028
Wolfgang Denkd87080b2006-03-31 18:32:53 +020029int board_init (void)
30{
31 gd->bd->bi_arch_number = MACH_TYPE_WEP_EP250;
32 gd->bd->bi_boot_params = 0xa0000000;
wdenk3e386912003-04-05 00:53:31 +000033/*
34 * Setup GPIO stuff to get serial working
35 */
36#if defined( CONFIG_FFUART )
Marek Vasut3ba8bf72010-09-09 09:50:39 +020037 writel(0x80, GPDR1);
38 writel(0x8010, GAFR1_L);
wdenk3e386912003-04-05 00:53:31 +000039#elif defined( CONFIG_BTUART )
Marek Vasut3ba8bf72010-09-09 09:50:39 +020040 writel(0x800, GPDR1);
41 writel(0x900000, GAFR1_L);
wdenk3e386912003-04-05 00:53:31 +000042#endif
Marek Vasut3ba8bf72010-09-09 09:50:39 +020043 writel(0x20, PSSR);
wdenk3e386912003-04-05 00:53:31 +000044
Wolfgang Denkd87080b2006-03-31 18:32:53 +020045 return 0;
wdenk3e386912003-04-05 00:53:31 +000046}
47
Wolfgang Denkd87080b2006-03-31 18:32:53 +020048int dram_init (void)
49{
wdenk3e386912003-04-05 00:53:31 +000050#if ( CONFIG_NR_DRAM_BANKS > 0 )
Wolfgang Denkd87080b2006-03-31 18:32:53 +020051 gd->bd->bi_dram[0].start = WEP_SDRAM_1;
52 gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE;
wdenk3e386912003-04-05 00:53:31 +000053#endif
wdenk8bde7f72003-06-27 21:31:46 +000054#if ( CONFIG_NR_DRAM_BANKS > 1 )
Wolfgang Denkd87080b2006-03-31 18:32:53 +020055 gd->bd->bi_dram[1].start = WEP_SDRAM_2;
56 gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE;
wdenk3e386912003-04-05 00:53:31 +000057#endif
wdenk8bde7f72003-06-27 21:31:46 +000058#if ( CONFIG_NR_DRAM_BANKS > 2 )
Wolfgang Denkd87080b2006-03-31 18:32:53 +020059 gd->bd->bi_dram[2].start = WEP_SDRAM_3;
60 gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE;
wdenk3e386912003-04-05 00:53:31 +000061#endif
62#if ( CONFIG_NR_DRAM_BANKS > 3 )
Wolfgang Denkd87080b2006-03-31 18:32:53 +020063 gd->bd->bi_dram[3].start = WEP_SDRAM_4;
64 gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE;
wdenk3e386912003-04-05 00:53:31 +000065#endif
wdenk8bde7f72003-06-27 21:31:46 +000066
Wolfgang Denkd87080b2006-03-31 18:32:53 +020067 return 0;
wdenk3e386912003-04-05 00:53:31 +000068}