blob: ab1773c3659eb6acd96310a6efe3a8c4f5ed27f6 [file] [log] [blame]
wdenkc1896002003-12-28 11:44:59 +00001/*
2 * (C) Copyright 2003
wdenkd4ca31c2004-01-02 14:00:00 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
6 *
7 * TOP5200 differences from IceCube:
8 * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
9 * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
10 * 1 SDRAM/DDRAM Bank up to 256 MB
11 * local VPD I2C Bus is software driven and uses
12 * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
13 * FLASH is re-located at 0xff000000
14 * Internal regs are at 0xf0000000
wdenkc1896002003-12-28 11:44:59 +000015 * Reset jumps to 0x00000100
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
wdenkcbd8a352004-02-24 02:00:03 +000044#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
wdenkc1896002003-12-28 11:44:59 +000045#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
46#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
47
Wolfgang Denk2ae18242010-10-06 09:05:45 +020048/*
49 * allowed and functional CONFIG_SYS_TEXT_BASE values:
50 * 0xff000000 low boot at 0x00000100 (default board setting)
51 * 0xfff00000 high boot at 0xfff00100 (board needs modification)
52 * 0x00100000 RAM load and test
53 */
54#define CONFIG_SYS_TEXT_BASE 0xff000000
55
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenkc1896002003-12-28 11:44:59 +000057
Becky Bruce31d82672008-05-08 19:02:12 -050058#define CONFIG_HIGH_BATS 1 /* High BATs supported */
59
wdenkc1896002003-12-28 11:44:59 +000060/*
61 * Serial console configuration
62 */
63#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
64#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkc1896002003-12-28 11:44:59 +000066
67
wdenk4d13cba2004-03-14 14:09:05 +000068#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
wdenkc1896002003-12-28 11:44:59 +000069/*
70 * PCI Mapping:
71 * 0x40000000 - 0x4fffffff - PCI Memory
72 * 0x50000000 - 0x50ffffff - PCI IO Space
73 */
74# define CONFIG_PCI 1
75# define CONFIG_PCI_PNP 1
76# define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -050077# define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
wdenkc1896002003-12-28 11:44:59 +000078
79# define CONFIG_PCI_MEM_BUS 0x40000000
80# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
81# define CONFIG_PCI_MEM_SIZE 0x10000000
82
83# define CONFIG_PCI_IO_BUS 0x50000000
84# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
85# define CONFIG_PCI_IO_SIZE 0x01000000
86
wdenkc1896002003-12-28 11:44:59 +000087#endif
88
wdenk4d13cba2004-03-14 14:09:05 +000089/* USB */
90#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
91
92# define CONFIG_USB_OHCI
93# define CONFIG_USB_CLOCK 0x0001bbbb
wdenk498b8db2004-04-18 22:26:17 +000094# if defined (CONFIG_EVAL5200)
95# define CONFIG_USB_CONFIG 0x00005100
96# else
97# define CONFIG_USB_CONFIG 0x00001000
98# endif
wdenk4d13cba2004-03-14 14:09:05 +000099# define CONFIG_DOS_PARTITION
100# define CONFIG_USB_STORAGE
101
wdenk4d13cba2004-03-14 14:09:05 +0000102#endif
103
104/* IDE */
105#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
wdenk4d13cba2004-03-14 14:09:05 +0000106# define CONFIG_DOS_PARTITION
wdenk4d13cba2004-03-14 14:09:05 +0000107#endif
108
wdenkc1896002003-12-28 11:44:59 +0000109
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500110/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500111 * BOOTP options
112 */
113#define CONFIG_BOOTP_BOOTFILESIZE
114#define CONFIG_BOOTP_BOOTPATH
115#define CONFIG_BOOTP_GATEWAY
116#define CONFIG_BOOTP_HOSTNAME
117
118
119/*
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500120 * Command line configuration.
121 */
122#include <config_cmd_default.h>
123
124#define CONFIG_CMD_ASKENV
125#define CONFIG_CMD_BEDBUG
126#define CONFIG_CMD_DATE
127#define CONFIG_CMD_DHCP
128#define CONFIG_CMD_EEPROM
129#define CONFIG_CMD_ELF
130#define CONFIG_CMD_I2C
131#define CONFIG_CMD_IMMAP
132#define CONFIG_CMD_MII
133#define CONFIG_CMD_REGINFO
134
135#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
136#define CONFIG_CMD_FAT
137#define CONFIG_CMD_IDE
138#define CONFIG_CMD_USB
139#define CONFIG_CMD_PCI
140#endif
141
wdenkc1896002003-12-28 11:44:59 +0000142
143/*
wdenk4d13cba2004-03-14 14:09:05 +0000144 * MUST be low boot - HIGHBOOT is not supported anymore
wdenkd4ca31c2004-01-02 14:00:00 +0000145 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200146#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147# define CONFIG_SYS_LOWBOOT 1
148# define CONFIG_SYS_LOWBOOT16 1
wdenk4d13cba2004-03-14 14:09:05 +0000149#else
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200150# error "CONFIG_SYS_TEXT_BASE must be 0xff000000"
wdenkd4ca31c2004-01-02 14:00:00 +0000151#endif
152
153/*
wdenkc1896002003-12-28 11:44:59 +0000154 * Autobooting
155 */
156#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkd4ca31c2004-01-02 14:00:00 +0000157
158#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100159 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkd4ca31c2004-01-02 14:00:00 +0000160 "echo"
161
162#undef CONFIG_BOOTARGS
163
164#define CONFIG_EXTRA_ENV_SETTINGS \
165 "netdev=eth0\0" \
166 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100167 "nfsroot=${serverip}:${rootpath}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000168 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100169 "addip=setenv bootargs ${bootargs} " \
170 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
171 ":${hostname}:${netdev}:off panic=1\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000172 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100173 "bootm ${kernel_addr}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000174 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100175 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
176 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000177 "rootpath=/opt/eldk/ppc_82xx\0" \
178 "bootfile=/tftpboot/MPC5200/uImage\0" \
179 ""
180
181#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkc1896002003-12-28 11:44:59 +0000182
183/*
184 * IPB Bus clocking configuration.
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenkd4ca31c2004-01-02 14:00:00 +0000187
wdenkc1896002003-12-28 11:44:59 +0000188/*
189 * I2C configuration
190 */
191/*
192 * EEPROM configuration
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
195#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
wdenkc1896002003-12-28 11:44:59 +0000196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
198#define CONFIG_SYS_EEPROM_SIZE 0x2000
wdenkd4ca31c2004-01-02 14:00:00 +0000199
wdenkc1896002003-12-28 11:44:59 +0000200#define CONFIG_ENV_OVERWRITE
201#define CONFIG_MISC_INIT_R
wdenkd4ca31c2004-01-02 14:00:00 +0000202
wdenkc1896002003-12-28 11:44:59 +0000203#undef CONFIG_HARD_I2C /* I2C with hardware support */
wdenk4d13cba2004-03-14 14:09:05 +0000204#define CONFIG_SOFT_I2C 1 /* I2C with softwate support */
wdenkd4ca31c2004-01-02 14:00:00 +0000205
wdenkc1896002003-12-28 11:44:59 +0000206#if defined (CONFIG_SOFT_I2C)
207# define SDA0 0x40
208# define SCL0 0x80
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209# define GPIOE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00))
210# define DDR0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08))
211# define DVO0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c))
212# define DVI0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20))
213# define ODE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04))
wdenkc1896002003-12-28 11:44:59 +0000214# define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
215# define I2C_READ ((DVI0&SDA0)?1:0)
216# define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
217# define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
218# define I2C_DELAY {udelay(5);}
219# define I2C_ACTIVE {DDR0|=SDA0;}
220# define I2C_TRISTATE {DDR0&=~SDA0;}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221# define CONFIG_SYS_I2C_SPEED 100000
222# define CONFIG_SYS_I2C_SLAVE 0x7F
223#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
224#define CONFIG_SYS_I2C_FACT_ADDR 0x57
wdenkc1896002003-12-28 11:44:59 +0000225#endif
wdenkd4ca31c2004-01-02 14:00:00 +0000226
227#if defined (CONFIG_HARD_I2C)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228# define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
229# define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
230# define CONFIG_SYS_I2C_SLAVE 0x7F
231#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
232#define CONFIG_SYS_I2C_FACT_ADDR 0x54
wdenkd4ca31c2004-01-02 14:00:00 +0000233#endif
wdenkc1896002003-12-28 11:44:59 +0000234
235/*
236 * Flash configuration, expect one 16 Megabyte Bank at most
237 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_FLASH_BASE 0xff000000
239#define CONFIG_SYS_FLASH_SIZE 0x01000000
240#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
241#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0)
wdenkc1896002003-12-28 11:44:59 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
wdenkc1896002003-12-28 11:44:59 +0000244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
246#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenkc1896002003-12-28 11:44:59 +0000247
248#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
249
wdenkd4ca31c2004-01-02 14:00:00 +0000250/*
251 * DRAM configuration - will be read from VPD later... TODO!
252 */
253#if 0
254/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_DRAM_DDR 0
256#define CONFIG_SYS_DRAM_EMODE 0
257#define CONFIG_SYS_DRAM_MODE 0x008D
258#define CONFIG_SYS_DRAM_CONTROL 0x514F0000
259#define CONFIG_SYS_DRAM_CONFIG1 0xC2233A00
260#define CONFIG_SYS_DRAM_CONFIG2 0x88B70004
261#define CONFIG_SYS_DRAM_TAP_DEL 0x08
262#define CONFIG_SYS_DRAM_RAM_SIZE 0x19
wdenkd4ca31c2004-01-02 14:00:00 +0000263#endif
264#if 1
265/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_DRAM_DDR 0
267#define CONFIG_SYS_DRAM_EMODE 0
268#define CONFIG_SYS_DRAM_MODE 0x00CD
269#define CONFIG_SYS_DRAM_CONTROL 0x514F0000
270#define CONFIG_SYS_DRAM_CONFIG1 0xD2333A00
271#define CONFIG_SYS_DRAM_CONFIG2 0x8AD70004
272#define CONFIG_SYS_DRAM_TAP_DEL 0x08
273#define CONFIG_SYS_DRAM_RAM_SIZE 0x19
wdenkd4ca31c2004-01-02 14:00:00 +0000274#endif
275
wdenkc1896002003-12-28 11:44:59 +0000276/*
277 * Environment settings
278 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200279#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200280#define CONFIG_ENV_OFFSET 0x1000
281#define CONFIG_ENV_SIZE 0x0700
wdenkc1896002003-12-28 11:44:59 +0000282
wdenkd4ca31c2004-01-02 14:00:00 +0000283/*
284 * VPD settings
285 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_FACT_OFFSET 0x1800
287#define CONFIG_SYS_FACT_SIZE 0x0800
wdenkd4ca31c2004-01-02 14:00:00 +0000288
wdenkc1896002003-12-28 11:44:59 +0000289/*
wdenkd4ca31c2004-01-02 14:00:00 +0000290 * Memory map
291 *
292 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
wdenkc1896002003-12-28 11:44:59 +0000293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */
295#define CONFIG_SYS_SDRAM_BASE 0x00000000
296#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
wdenkc1896002003-12-28 11:44:59 +0000297
298/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
300#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
wdenkc1896002003-12-28 11:44:59 +0000301
302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
304#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
305#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc1896002003-12-28 11:44:59 +0000306
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200307#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
309# define CONFIG_SYS_RAMBOOT 1
wdenkc1896002003-12-28 11:44:59 +0000310#endif
311
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
313#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
314#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc1896002003-12-28 11:44:59 +0000315
316/*
317 * Ethernet configuration
318 */
wdenkcbd8a352004-02-24 02:00:03 +0000319#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800320#define CONFIG_MPC5xxx_FEC_MII10 /* Workaround for FEC 100Mbit problem */
wdenkd4ca31c2004-01-02 14:00:00 +0000321#define CONFIG_PHY_ADDR 0x1f
wdenkc1896002003-12-28 11:44:59 +0000322#define CONFIG_PHY_TYPE 0x79c874
323/*
wdenkd4ca31c2004-01-02 14:00:00 +0000324 * GPIO configuration:
325 * PSC1,2,3 predefined as UART
326 * PCI disabled
wdenkc1896002003-12-28 11:44:59 +0000327 * Ethernet 100 with MD
328 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044
wdenkc1896002003-12-28 11:44:59 +0000330
331/*
332 * Miscellaneous configurable options
333 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_LONGHELP /* undef to save memory */
335#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500336#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc1896002003-12-28 11:44:59 +0000338#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc1896002003-12-28 11:44:59 +0000340#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
342#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
343#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc1896002003-12-28 11:44:59 +0000344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
346#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
wdenkc1896002003-12-28 11:44:59 +0000347
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
wdenkc1896002003-12-28 11:44:59 +0000349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc1896002003-12-28 11:44:59 +0000351
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500353#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500355#endif
356
357
wdenk63e73c92004-02-23 22:22:28 +0000358#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */
359 #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */
360 #define RTC(reg) (0xf0010000+reg)
361 /* setup CS2 for M48T08. Must MAP 64kB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362 #define CONFIG_SYS_CS2_START RTC(0)
363 #define CONFIG_SYS_CS2_SIZE 0x10000
wdenk63e73c92004-02-23 22:22:28 +0000364 /* setup CS2 configuration register: */
365 /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
366 /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367 #define CONFIG_SYS_CS2_CFG 0x00047800
wdenk63e73c92004-02-23 22:22:28 +0000368#else
369 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
370#endif
wdenk1c437712004-01-16 00:30:56 +0000371
wdenkc1896002003-12-28 11:44:59 +0000372/*
373 * Various low-level settings
374 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
376#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenkc1896002003-12-28 11:44:59 +0000377
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
379#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
380#define CONFIG_SYS_BOOTCS_CFG 0x00047801
381#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
382#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
wdenkc1896002003-12-28 11:44:59 +0000383
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_CS_BURST 0x00000000
385#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
wdenkc1896002003-12-28 11:44:59 +0000386
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_RESET_ADDRESS 0x7f000000
wdenkc1896002003-12-28 11:44:59 +0000388
wdenk4d13cba2004-03-14 14:09:05 +0000389/*-----------------------------------------------------------------------
390 * IDE/ATA stuff Supports IDE harddisk
391 *-----------------------------------------------------------------------
392 */
393
394#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
395
396#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
397#undef CONFIG_IDE_LED /* LED for ide not supported */
398
399#define CONFIG_IDE_RESET 1
400#define CONFIG_IDE_PREINIT
401
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
403#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk4d13cba2004-03-14 14:09:05 +0000404
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk4d13cba2004-03-14 14:09:05 +0000406
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
wdenk4d13cba2004-03-14 14:09:05 +0000408
409/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
wdenk4d13cba2004-03-14 14:09:05 +0000411
412/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
wdenk4d13cba2004-03-14 14:09:05 +0000414
415/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_ATA_ALT_OFFSET (0x005c)
wdenk4d13cba2004-03-14 14:09:05 +0000417
418/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_ATA_STRIDE 4
wdenk4d13cba2004-03-14 14:09:05 +0000420
wdenkc1896002003-12-28 11:44:59 +0000421#endif /* __CONFIG_H */