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wdenk945af8d2003-07-16 21:53:01 +00001/*
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <mpc5xxx.h>
26
Wolfgang Denkd87080b2006-03-31 18:32:53 +020027DECLARE_GLOBAL_DATA_PTR;
28
wdenk945af8d2003-07-16 21:53:01 +000029/*
30 * Breath some life into the CPU...
31 *
32 * Set up the memory map,
33 * initialize a bunch of registers.
34 */
35void cpu_init_f (void)
36{
wdenk945af8d2003-07-16 21:53:01 +000037 unsigned long addecr = (1 << 25); /* Boot_CS */
38#if defined(CFG_RAMBOOT) && defined(CONFIG_MGT5100)
39 addecr |= (1 << 22); /* SDRAM enable */
40#endif
41 /* Pointer is writable since we allocated a register for it */
42 gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
43
44 /* Clear initial global data */
45 memset ((void *) gd, 0, sizeof (gd_t));
46
47 /*
48 * Memory Controller: configure chip selects and enable them
49 */
50#if defined(CFG_BOOTCS_START) && defined(CFG_BOOTCS_SIZE)
51 *(vu_long *)MPC5XXX_BOOTCS_START = START_REG(CFG_BOOTCS_START);
52 *(vu_long *)MPC5XXX_BOOTCS_STOP = STOP_REG(CFG_BOOTCS_START,
53 CFG_BOOTCS_SIZE);
54#endif
55#if defined(CFG_BOOTCS_CFG)
56 *(vu_long *)MPC5XXX_BOOTCS_CFG = CFG_BOOTCS_CFG;
57#endif
58
59#if defined(CFG_CS0_START) && defined(CFG_CS0_SIZE)
60 *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_CS0_START);
61 *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_CS0_START, CFG_CS0_SIZE);
62 /* CS0 and BOOT_CS cannot be enabled at once. */
63 /* addecr |= (1 << 16); */
64#endif
65#if defined(CFG_CS0_CFG)
66 *(vu_long *)MPC5XXX_CS0_CFG = CFG_CS0_CFG;
67#endif
68
69#if defined(CFG_CS1_START) && defined(CFG_CS1_SIZE)
70 *(vu_long *)MPC5XXX_CS1_START = START_REG(CFG_CS1_START);
71 *(vu_long *)MPC5XXX_CS1_STOP = STOP_REG(CFG_CS1_START, CFG_CS1_SIZE);
72 addecr |= (1 << 17);
73#endif
74#if defined(CFG_CS1_CFG)
75 *(vu_long *)MPC5XXX_CS1_CFG = CFG_CS1_CFG;
76#endif
77
78#if defined(CFG_CS2_START) && defined(CFG_CS2_SIZE)
79 *(vu_long *)MPC5XXX_CS2_START = START_REG(CFG_CS2_START);
80 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, CFG_CS2_SIZE);
81 addecr |= (1 << 18);
82#endif
83#if defined(CFG_CS2_CFG)
84 *(vu_long *)MPC5XXX_CS2_CFG = CFG_CS2_CFG;
85#endif
86
87#if defined(CFG_CS3_START) && defined(CFG_CS3_SIZE)
88 *(vu_long *)MPC5XXX_CS3_START = START_REG(CFG_CS3_START);
89 *(vu_long *)MPC5XXX_CS3_STOP = STOP_REG(CFG_CS3_START, CFG_CS3_SIZE);
90 addecr |= (1 << 19);
91#endif
92#if defined(CFG_CS3_CFG)
93 *(vu_long *)MPC5XXX_CS3_CFG = CFG_CS3_CFG;
94#endif
95
96#if defined(CFG_CS4_START) && defined(CFG_CS4_SIZE)
97 *(vu_long *)MPC5XXX_CS4_START = START_REG(CFG_CS4_START);
98 *(vu_long *)MPC5XXX_CS4_STOP = STOP_REG(CFG_CS4_START, CFG_CS4_SIZE);
99 addecr |= (1 << 20);
100#endif
101#if defined(CFG_CS4_CFG)
102 *(vu_long *)MPC5XXX_CS4_CFG = CFG_CS4_CFG;
103#endif
104
105#if defined(CFG_CS5_START) && defined(CFG_CS5_SIZE)
106 *(vu_long *)MPC5XXX_CS5_START = START_REG(CFG_CS5_START);
107 *(vu_long *)MPC5XXX_CS5_STOP = STOP_REG(CFG_CS5_START, CFG_CS5_SIZE);
108 addecr |= (1 << 21);
109#endif
110#if defined(CFG_CS5_CFG)
111 *(vu_long *)MPC5XXX_CS5_CFG = CFG_CS5_CFG;
112#endif
113
114#if defined(CONFIG_MPC5200)
115 addecr |= 1;
116#if defined(CFG_CS6_START) && defined(CFG_CS6_SIZE)
117 *(vu_long *)MPC5XXX_CS6_START = START_REG(CFG_CS6_START);
118 *(vu_long *)MPC5XXX_CS6_STOP = STOP_REG(CFG_CS6_START, CFG_CS6_SIZE);
119 addecr |= (1 << 26);
120#endif
121#if defined(CFG_CS6_CFG)
122 *(vu_long *)MPC5XXX_CS6_CFG = CFG_CS6_CFG;
123#endif
124
125#if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE)
Heiko Schocher6dedf3d2006-12-21 16:14:48 +0100126 *(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS7_START);
wdenk945af8d2003-07-16 21:53:01 +0000127 *(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE);
128 addecr |= (1 << 27);
129#endif
130#if defined(CFG_CS7_CFG)
131 *(vu_long *)MPC5XXX_CS7_CFG = CFG_CS7_CFG;
132#endif
133
134#if defined(CFG_CS_BURST)
135 *(vu_long *)MPC5XXX_CS_BURST = CFG_CS_BURST;
136#endif
137#if defined(CFG_CS_DEADCYCLE)
138 *(vu_long *)MPC5XXX_CS_DEADCYCLE = CFG_CS_DEADCYCLE;
139#endif
140#endif /* CONFIG_MPC5200 */
141
142 /* Enable chip selects */
143 *(vu_long *)MPC5XXX_ADDECR = addecr;
144 *(vu_long *)MPC5XXX_CS_CTRL = (1 << 24);
145
146 /* Setup pin multiplexing */
147#if defined(CFG_GPS_PORT_CONFIG)
148 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG = CFG_GPS_PORT_CONFIG;
149#endif
wdenk96dd9af2003-07-31 22:56:30 +0000150
151#if defined(CONFIG_MPC5200)
152 /* enable timebase */
153 *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13);
wdenk7152b1d2003-09-05 23:19:14 +0000154
Wolfgang Denk8419c012006-04-18 11:05:03 +0200155 /* Enable snooping for RAM */
156 *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
157 *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d;
158
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200159# if defined(CFG_IPBCLK_EQUALS_XLBCLK)
wdenk7152b1d2003-09-05 23:19:14 +0000160 /* Motorola reports IPB should better run at 133 MHz. */
161 *(vu_long *)MPC5XXX_ADDECR |= 1;
162 /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
163 addecr = *(vu_long *)MPC5XXX_CDM_CFG;
164 addecr &= ~0x103;
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200165# if defined(CFG_PCICLK_EQUALS_IPBCLK_DIV2)
wdenk56523f12004-07-11 17:40:54 +0000166 /* pci_clk_sel = 0x01 -> IPB_CLK/2 */
167 addecr |= 0x01;
168# else
169 /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
wdenk7152b1d2003-09-05 23:19:14 +0000170 addecr |= 0x02;
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200171# endif /* CFG_PCICLK_EQUALS_IPBCLK_DIV2 */
wdenk7152b1d2003-09-05 23:19:14 +0000172 *(vu_long *)MPC5XXX_CDM_CFG = addecr;
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200173# endif /* CFG_IPBCLK_EQUALS_XLBCLK */
wdenk4aeb2512003-09-16 17:06:05 +0000174 /* Configure the XLB Arbiter */
175 *(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff;
176 *(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111;
wdenke1599e82004-10-10 23:27:33 +0000177
178# if defined(CFG_XLB_PIPELINING)
179 /* Enable piplining */
180 *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
181# endif
wdenk56523f12004-07-11 17:40:54 +0000182#endif /* CONFIG_MPC5200 */
wdenk945af8d2003-07-16 21:53:01 +0000183}
184
185/*
186 * initialize higher level parts of CPU like time base and timers
187 */
188int cpu_init_r (void)
189{
190 /* mask all interrupts */
191#if defined(CONFIG_MGT5100)
192 *(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xfffffc00;
193#elif defined(CONFIG_MPC5200)
194 *(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xffffff00;
195#endif
196 *(vu_long *)MPC5XXX_ICTL_CRIT |= 0x0001ffff;
197 *(vu_long *)MPC5XXX_ICTL_EXT &= ~0x00000f00;
wdenk4aeb2512003-09-16 17:06:05 +0000198 /* route critical ints to normal ints */
199 *(vu_long *)MPC5XXX_ICTL_EXT |= 0x00000001;
wdenk945af8d2003-07-16 21:53:01 +0000200
Jon Loeliger44312832007-07-09 19:06:00 -0500201#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
wdenk945af8d2003-07-16 21:53:01 +0000202 /* load FEC microcode */
203 loadtask(0, 2);
204#endif
205
206 return (0);
207}