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Stefan Roese79b2d0b2007-02-20 10:27:08 +01001/*
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +01002 * (C) Copyright 2007-2009
Stefan Roese79b2d0b2007-02-20 10:27:08 +01003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
6 *
7 * (C) Copyright 2001
8 * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
wdenkc6097192002-11-03 00:24:07 +000028
29#include <common.h>
30#include <ppc4xx.h>
Stefan Roese79b2d0b2007-02-20 10:27:08 +010031#include <4xx_i2c.h>
wdenkc6097192002-11-03 00:24:07 +000032#include <i2c.h>
Stefan Roese79b2d0b2007-02-20 10:27:08 +010033#include <asm-ppc/io.h>
wdenkc6097192002-11-03 00:24:07 +000034
35#ifdef CONFIG_HARD_I2C
36
Wolfgang Denkd87080b2006-03-31 18:32:53 +020037DECLARE_GLOBAL_DATA_PTR;
38
Stefan Roese79b2d0b2007-02-20 10:27:08 +010039#if defined(CONFIG_I2C_MULTI_BUS)
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +010040/*
41 * Initialize the bus pointer to whatever one the SPD EEPROM is on.
Stefan Roese79b2d0b2007-02-20 10:27:08 +010042 * Default is bus 0. This is necessary because the DDR initialization
43 * runs from ROM, and we can't switch buses because we can't modify
44 * the global variables.
45 */
Trent Piepho5e3ab682008-11-12 17:29:48 -080046#ifndef CONFIG_SYS_SPD_BUS_NUM
47#define CONFIG_SYS_SPD_BUS_NUM 0
Stefan Roese79b2d0b2007-02-20 10:27:08 +010048#endif
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +010049static unsigned int i2c_bus_num __attribute__ ((section (".data"))) =
50 CONFIG_SYS_SPD_BUS_NUM;
Stefan Roese79b2d0b2007-02-20 10:27:08 +010051#endif /* CONFIG_I2C_MULTI_BUS */
wdenkc6097192002-11-03 00:24:07 +000052
Stefan Roese79b2d0b2007-02-20 10:27:08 +010053static void _i2c_bus_reset(void)
wdenkc6097192002-11-03 00:24:07 +000054{
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +010055 struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
Stefan Roese79b2d0b2007-02-20 10:27:08 +010056 int i;
57 u8 dc;
wdenkc6097192002-11-03 00:24:07 +000058
59 /* Reset status register */
60 /* write 1 in SCMP and IRQA to clear these fields */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +010061 out_8(&i2c->sts, 0x0A);
wdenkc6097192002-11-03 00:24:07 +000062
63 /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +010064 out_8(&i2c->extsts, 0x8F);
wdenkc6097192002-11-03 00:24:07 +000065
Wolfgang Denk53677ef2008-05-20 16:00:29 +020066 /* Place chip in the reset state */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +010067 out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
wdenkc6097192002-11-03 00:24:07 +000068
Stefan Roese79b2d0b2007-02-20 10:27:08 +010069 /* Check if bus is free */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +010070 dc = in_8(&i2c->directcntl);
Stefan Roese79b2d0b2007-02-20 10:27:08 +010071 if (!DIRCTNL_FREE(dc)){
72 /* Try to set bus free state */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +010073 out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
Stefan Roese79b2d0b2007-02-20 10:27:08 +010074
75 /* Wait until we regain bus control */
76 for (i = 0; i < 100; ++i) {
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +010077 dc = in_8(&i2c->directcntl);
Stefan Roese79b2d0b2007-02-20 10:27:08 +010078 if (DIRCTNL_FREE(dc))
79 break;
80
81 /* Toggle SCL line */
82 dc ^= IIC_DIRCNTL_SCC;
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +010083 out_8(&i2c->directcntl, dc);
Stefan Roese79b2d0b2007-02-20 10:27:08 +010084 udelay(10);
85 dc ^= IIC_DIRCNTL_SCC;
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +010086 out_8(&i2c->directcntl, dc);
wdenkc6097192002-11-03 00:24:07 +000087 }
88 }
Stefan Roese79b2d0b2007-02-20 10:27:08 +010089
90 /* Remove reset */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +010091 out_8(&i2c->xtcntlss, 0);
wdenkc6097192002-11-03 00:24:07 +000092}
93
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +010094void i2c_init(int speed, int slaveaddr)
wdenkc6097192002-11-03 00:24:07 +000095{
Stefan Roese1a332da2010-03-29 15:30:46 +020096 struct ppc4xx_i2c *i2c;
wdenkc6097192002-11-03 00:24:07 +000097 int val, divisor;
Stefan Roese79b2d0b2007-02-20 10:27:08 +010098 int bus;
wdenkc6097192002-11-03 00:24:07 +000099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#ifdef CONFIG_SYS_I2C_INIT_BOARD
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100101 /*
102 * Call board specific i2c bus reset routine before accessing the
103 * environment, which might be in a chip on that bus. For details
104 * about this problem see doc/I2C_Edge_Conditions.
105 */
wdenk47cd00f2003-03-06 13:39:27 +0000106 i2c_init_board();
107#endif
108
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109 for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) {
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100110 I2C_SET_BUS(bus);
wdenkc6097192002-11-03 00:24:07 +0000111
Stefan Roese1a332da2010-03-29 15:30:46 +0200112 /* Set i2c pointer after calling I2C_SET_BUS() */
113 i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
114
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100115 /* Handle possible failed I2C state */
116 /* FIXME: put this into i2c_init_board()? */
117 _i2c_bus_reset();
wdenkc6097192002-11-03 00:24:07 +0000118
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100119 /* clear lo master address */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100120 out_8(&i2c->lmadr, 0);
wdenkc6097192002-11-03 00:24:07 +0000121
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100122 /* clear hi master address */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100123 out_8(&i2c->hmadr, 0);
wdenkc6097192002-11-03 00:24:07 +0000124
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100125 /* clear lo slave address */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100126 out_8(&i2c->lsadr, 0);
wdenkc6097192002-11-03 00:24:07 +0000127
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100128 /* clear hi slave address */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100129 out_8(&i2c->hsadr, 0);
wdenkc6097192002-11-03 00:24:07 +0000130
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100131 /* Clock divide Register */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100132 /* set divisor according to freq_opb */
133 divisor = (get_OPB_freq() - 1) / 10000000;
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100134 if (divisor == 0)
135 divisor = 1;
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100136 out_8(&i2c->clkdiv, divisor);
wdenkc6097192002-11-03 00:24:07 +0000137
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100138 /* no interrupts */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100139 out_8(&i2c->intrmsk, 0);
wdenkc6097192002-11-03 00:24:07 +0000140
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100141 /* clear transfer count */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100142 out_8(&i2c->xfrcnt, 0);
wdenkc6097192002-11-03 00:24:07 +0000143
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100144 /* clear extended control & stat */
145 /* write 1 in SRC SRS SWC SWS to clear these fields */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100146 out_8(&i2c->xtcntlss, 0xF0);
wdenkc6097192002-11-03 00:24:07 +0000147
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100148 /* Mode Control Register
149 Flush Slave/Master data buffer */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100150 out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
wdenkc6097192002-11-03 00:24:07 +0000151
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100152 val = in_8(&i2c->mdcntl);
wdenkc6097192002-11-03 00:24:07 +0000153
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100154 /* Ignore General Call, slave transfers are ignored,
155 * disable interrupts, exit unknown bus state, enable hold
156 * SCL 100kHz normaly or FastMode for 400kHz and above
157 */
wdenkc6097192002-11-03 00:24:07 +0000158
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100159 val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL;
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100160 if (speed >= 400000)
161 val |= IIC_MDCNTL_FSM;
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100162 out_8(&i2c->mdcntl, val);
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100163
164 /* clear control reg */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100165 out_8(&i2c->cntl, 0x00);
wdenk8bde7f72003-06-27 21:31:46 +0000166 }
wdenkc6097192002-11-03 00:24:07 +0000167
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100168 /* set to SPD bus as default bus upon powerup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169 I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
wdenkc6097192002-11-03 00:24:07 +0000170}
171
172/*
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100173 * This code tries to use the features of the 405GP i2c
174 * controller. It will transfer up to 4 bytes in one pass
175 * on the loop. It only does out_8((u8 *)lbz) to the buffer when it
176 * is possible to do out16(lhz) transfers.
177 *
178 * cmd_type is 0 for write 1 for read.
179 *
180 * addr_len can take any value from 0-255, it is only limited
181 * by the char, we could make it larger if needed. If it is
182 * 0 we skip the address write cycle.
183 *
184 * Typical case is a Write of an addr followd by a Read. The
185 * IBM FAQ does not cover this. On the last byte of the write
186 * we don't set the creg CHT bit, and on the first bytes of the
187 * read we set the RPST bit.
188 *
189 * It does not support address only transfers, there must be
190 * a data part. If you want to write the address yourself, put
191 * it in the data pointer.
192 *
193 * It does not support transfer to/from address 0.
194 *
195 * It does not check XFRCNT.
196 */
197static int i2c_transfer(unsigned char cmd_type,
198 unsigned char chip,
199 unsigned char addr[],
200 unsigned char addr_len,
201 unsigned char data[],
202 unsigned short data_len)
wdenkc6097192002-11-03 00:24:07 +0000203{
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100204 struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
205 u8 *ptr;
wdenk8bde7f72003-06-27 21:31:46 +0000206 int reading;
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100207 int tran, cnt;
wdenk8bde7f72003-06-27 21:31:46 +0000208 int result;
209 int status;
210 int i;
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100211 u8 creg;
wdenkc6097192002-11-03 00:24:07 +0000212
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100213 if (data == 0 || data_len == 0) {
214 /* Don't support data transfer of no length or to address 0 */
wdenk8bde7f72003-06-27 21:31:46 +0000215 printf( "i2c_transfer: bad call\n" );
216 return IIC_NOK;
217 }
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100218 if (addr && addr_len) {
wdenk8bde7f72003-06-27 21:31:46 +0000219 ptr = addr;
220 cnt = addr_len;
221 reading = 0;
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100222 } else {
wdenk8bde7f72003-06-27 21:31:46 +0000223 ptr = data;
224 cnt = data_len;
225 reading = cmd_type;
226 }
wdenkc6097192002-11-03 00:24:07 +0000227
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100228 /* Clear Stop Complete Bit */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100229 out_8(&i2c->sts, IIC_STS_SCMP);
230
wdenk8bde7f72003-06-27 21:31:46 +0000231 /* Check init */
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100232 i = 10;
wdenk8bde7f72003-06-27 21:31:46 +0000233 do {
234 /* Get status */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100235 status = in_8(&i2c->sts);
wdenk8bde7f72003-06-27 21:31:46 +0000236 i--;
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100237 } while ((status & IIC_STS_PT) && (i > 0));
wdenkc6097192002-11-03 00:24:07 +0000238
wdenk8bde7f72003-06-27 21:31:46 +0000239 if (status & IIC_STS_PT) {
240 result = IIC_NOK_TOUT;
241 return(result);
242 }
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100243
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100244 /* flush the Master/Slave Databuffers */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100245 out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) |
246 IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB);
247
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100248 /* need to wait 4 OPB clocks? code below should take that long */
wdenkc6097192002-11-03 00:24:07 +0000249
wdenk8bde7f72003-06-27 21:31:46 +0000250 /* 7-bit adressing */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100251 out_8(&i2c->hmadr, 0);
252 out_8(&i2c->lmadr, chip);
wdenkc6097192002-11-03 00:24:07 +0000253
wdenk8bde7f72003-06-27 21:31:46 +0000254 tran = 0;
255 result = IIC_OK;
256 creg = 0;
wdenkc6097192002-11-03 00:24:07 +0000257
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100258 while (tran != cnt && (result == IIC_OK)) {
wdenk8bde7f72003-06-27 21:31:46 +0000259 int bc,j;
wdenkc6097192002-11-03 00:24:07 +0000260
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100261 /*
262 * Control register =
263 * Normal transfer, 7-bits adressing, Transfer up to
264 * bc bytes, Normal start, Transfer is a sequence of transfers
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100265 */
wdenk8bde7f72003-06-27 21:31:46 +0000266 creg |= IIC_CNTL_PT;
267
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100268 bc = (cnt - tran) > 4 ? 4 : cnt - tran;
269 creg |= (bc - 1) << 4;
270 /* if the real cmd type is write continue trans */
271 if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
wdenk8bde7f72003-06-27 21:31:46 +0000272 creg |= IIC_CNTL_CHT;
273
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100274 if (reading) {
wdenk8bde7f72003-06-27 21:31:46 +0000275 creg |= IIC_CNTL_READ;
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100276 } else {
277 for(j = 0; j < bc; j++) {
wdenk8bde7f72003-06-27 21:31:46 +0000278 /* Set buffer */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100279 out_8(&i2c->mdbuf, ptr[tran + j]);
280 }
281 }
282 out_8(&i2c->cntl, creg);
wdenk8bde7f72003-06-27 21:31:46 +0000283
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100284 /*
285 * Transfer is in progress
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100286 * we have to wait for upto 5 bytes of data
287 * 1 byte chip address+r/w bit then bc bytes
288 * of data.
289 * udelay(10) is 1 bit time at 100khz
290 * Doubled for slop. 20 is too small.
291 */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100292 i = 2 * 5 * 8;
wdenk8bde7f72003-06-27 21:31:46 +0000293 do {
294 /* Get status */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100295 status = in_8(&i2c->sts);
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100296 udelay(10);
wdenk8bde7f72003-06-27 21:31:46 +0000297 i--;
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100298 } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) &&
299 (i > 0));
wdenkc6097192002-11-03 00:24:07 +0000300
wdenk8bde7f72003-06-27 21:31:46 +0000301 if (status & IIC_STS_ERR) {
302 result = IIC_NOK;
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100303 status = in_8(&i2c->extsts);
wdenk8bde7f72003-06-27 21:31:46 +0000304 /* Lost arbitration? */
305 if (status & IIC_EXTSTS_LA)
306 result = IIC_NOK_LA;
307 /* Incomplete transfer? */
308 if (status & IIC_EXTSTS_ICT)
309 result = IIC_NOK_ICT;
310 /* Transfer aborted? */
311 if (status & IIC_EXTSTS_XFRA)
312 result = IIC_NOK_XFRA;
313 } else if ( status & IIC_STS_PT) {
314 result = IIC_NOK_TOUT;
315 }
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100316
wdenk8bde7f72003-06-27 21:31:46 +0000317 /* Command is reading => get buffer */
318 if ((reading) && (result == IIC_OK)) {
319 /* Are there data in buffer */
320 if (status & IIC_STS_MDBS) {
321 /*
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100322 * even if we have data we have to wait 4OPB
323 * clocks for it to hit the front of the FIFO,
324 * after that we can just read. We should check
325 * XFCNT here and if the FIFO is full there is
326 * no need to wait.
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100327 */
328 udelay(1);
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100329 for (j = 0; j < bc; j++)
330 ptr[tran + j] = in_8(&i2c->mdbuf);
wdenk8bde7f72003-06-27 21:31:46 +0000331 } else
332 result = IIC_NOK_DATA;
333 }
334 creg = 0;
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100335 tran += bc;
336 if (ptr == addr && tran == cnt) {
wdenk8bde7f72003-06-27 21:31:46 +0000337 ptr = data;
338 cnt = data_len;
339 tran = 0;
340 reading = cmd_type;
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100341 if (reading)
wdenk8bde7f72003-06-27 21:31:46 +0000342 creg = IIC_CNTL_RPST;
343 }
344 }
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100345 return result;
wdenkc6097192002-11-03 00:24:07 +0000346}
347
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100348int i2c_probe(uchar chip)
wdenkc6097192002-11-03 00:24:07 +0000349{
350 uchar buf[1];
351
352 buf[0] = 0;
353
wdenk8bde7f72003-06-27 21:31:46 +0000354 /*
355 * What is needed is to send the chip address and verify that the
356 * address was <ACK>ed (i.e. there was a chip at that address which
357 * drove the data line low).
358 */
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100359 return (i2c_transfer(1, chip << 1, 0, 0, buf, 1) != 0);
wdenkc6097192002-11-03 00:24:07 +0000360}
361
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100362static int ppc4xx_i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer,
363 int len, int read)
wdenkc6097192002-11-03 00:24:07 +0000364{
wdenk8bde7f72003-06-27 21:31:46 +0000365 uchar xaddr[4];
366 int ret;
wdenkc6097192002-11-03 00:24:07 +0000367
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100368 if (alen > 4) {
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100369 printf("I2C: addr len %d not supported\n", alen);
wdenkc6097192002-11-03 00:24:07 +0000370 return 1;
371 }
372
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100373 if (alen > 0) {
wdenk8bde7f72003-06-27 21:31:46 +0000374 xaddr[0] = (addr >> 24) & 0xFF;
375 xaddr[1] = (addr >> 16) & 0xFF;
376 xaddr[2] = (addr >> 8) & 0xFF;
377 xaddr[3] = addr & 0xFF;
378 }
wdenkc6097192002-11-03 00:24:07 +0000379
380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
wdenkc6097192002-11-03 00:24:07 +0000382 /*
wdenk8bde7f72003-06-27 21:31:46 +0000383 * EEPROM chips that implement "address overflow" are ones
384 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
385 * address and the extra bits end up in the "chip address"
386 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
387 * four 256 byte chips.
wdenkc6097192002-11-03 00:24:07 +0000388 *
wdenk8bde7f72003-06-27 21:31:46 +0000389 * Note that we consider the length of the address field to
390 * still be one byte because the extra address bits are
391 * hidden in the chip address.
wdenkc6097192002-11-03 00:24:07 +0000392 */
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100393 if (alen > 0)
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100394 chip |= ((addr >> (alen * 8)) &
395 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
wdenkc6097192002-11-03 00:24:07 +0000396#endif
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100397 if ((ret = i2c_transfer(read, chip << 1, &xaddr[4 - alen], alen,
398 buffer, len)) != 0) {
399 if (gd->have_console) {
400 printf("I2C %s: failed %d\n",
401 read ? "read" : "write", ret);
402 }
403
wdenk8bde7f72003-06-27 21:31:46 +0000404 return 1;
405 }
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100406
wdenk8bde7f72003-06-27 21:31:46 +0000407 return 0;
wdenkc6097192002-11-03 00:24:07 +0000408}
409
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100410int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
411{
412 return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 1);
413}
414
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100415int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
wdenkc6097192002-11-03 00:24:07 +0000416{
Stefan Roeseeb5eb2b2009-11-19 14:03:17 +0100417 return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 0);
wdenkc6097192002-11-03 00:24:07 +0000418}
419
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100420#if defined(CONFIG_I2C_MULTI_BUS)
421/*
422 * Functions for multiple I2C bus handling
423 */
424unsigned int i2c_get_bus_num(void)
425{
426 return i2c_bus_num;
427}
428
429int i2c_set_bus_num(unsigned int bus)
430{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431 if (bus >= CONFIG_SYS_MAX_I2C_BUS)
Stefan Roese79b2d0b2007-02-20 10:27:08 +0100432 return -1;
433
434 i2c_bus_num = bus;
435
436 return 0;
437}
Matthias Fuchsced5b902007-03-08 16:23:11 +0100438#endif /* CONFIG_I2C_MULTI_BUS */
wdenkc6097192002-11-03 00:24:07 +0000439#endif /* CONFIG_HARD_I2C */