Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Exceet Electronics GmbH |
| 4 | * Copyright (C) 2018 Bootlin |
| 5 | * |
| 6 | * Author: Boris Brezillon <boris.brezillon@bootlin.com> |
| 7 | */ |
| 8 | |
| 9 | #ifndef __UBOOT__ |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 10 | #include <log.h> |
Simon Glass | 61b29b8 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 11 | #include <dm/devres.h> |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 12 | #include <linux/dmaengine.h> |
| 13 | #include <linux/pm_runtime.h> |
| 14 | #include "internals.h" |
| 15 | #else |
Simon Glass | 340fd10 | 2020-07-19 10:15:34 -0600 | [diff] [blame] | 16 | #include <common.h> |
| 17 | #include <dm.h> |
| 18 | #include <errno.h> |
| 19 | #include <malloc.h> |
| 20 | #include <spi.h> |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 21 | #include <spi.h> |
| 22 | #include <spi-mem.h> |
Simon Glass | 340fd10 | 2020-07-19 10:15:34 -0600 | [diff] [blame] | 23 | #include <dm/device_compat.h> |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 24 | #endif |
| 25 | |
| 26 | #ifndef __UBOOT__ |
| 27 | /** |
| 28 | * spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a |
| 29 | * memory operation |
| 30 | * @ctlr: the SPI controller requesting this dma_map() |
| 31 | * @op: the memory operation containing the buffer to map |
| 32 | * @sgt: a pointer to a non-initialized sg_table that will be filled by this |
| 33 | * function |
| 34 | * |
| 35 | * Some controllers might want to do DMA on the data buffer embedded in @op. |
| 36 | * This helper prepares everything for you and provides a ready-to-use |
| 37 | * sg_table. This function is not intended to be called from spi drivers. |
| 38 | * Only SPI controller drivers should use it. |
| 39 | * Note that the caller must ensure the memory region pointed by |
| 40 | * op->data.buf.{in,out} is DMA-able before calling this function. |
| 41 | * |
| 42 | * Return: 0 in case of success, a negative error code otherwise. |
| 43 | */ |
| 44 | int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr, |
| 45 | const struct spi_mem_op *op, |
| 46 | struct sg_table *sgt) |
| 47 | { |
| 48 | struct device *dmadev; |
| 49 | |
| 50 | if (!op->data.nbytes) |
| 51 | return -EINVAL; |
| 52 | |
| 53 | if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx) |
| 54 | dmadev = ctlr->dma_tx->device->dev; |
| 55 | else if (op->data.dir == SPI_MEM_DATA_IN && ctlr->dma_rx) |
| 56 | dmadev = ctlr->dma_rx->device->dev; |
| 57 | else |
| 58 | dmadev = ctlr->dev.parent; |
| 59 | |
| 60 | if (!dmadev) |
| 61 | return -EINVAL; |
| 62 | |
| 63 | return spi_map_buf(ctlr, dmadev, sgt, op->data.buf.in, op->data.nbytes, |
| 64 | op->data.dir == SPI_MEM_DATA_IN ? |
| 65 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
| 66 | } |
| 67 | EXPORT_SYMBOL_GPL(spi_controller_dma_map_mem_op_data); |
| 68 | |
| 69 | /** |
| 70 | * spi_controller_dma_unmap_mem_op_data() - DMA-unmap the buffer attached to a |
| 71 | * memory operation |
| 72 | * @ctlr: the SPI controller requesting this dma_unmap() |
| 73 | * @op: the memory operation containing the buffer to unmap |
| 74 | * @sgt: a pointer to an sg_table previously initialized by |
| 75 | * spi_controller_dma_map_mem_op_data() |
| 76 | * |
| 77 | * Some controllers might want to do DMA on the data buffer embedded in @op. |
| 78 | * This helper prepares things so that the CPU can access the |
| 79 | * op->data.buf.{in,out} buffer again. |
| 80 | * |
| 81 | * This function is not intended to be called from SPI drivers. Only SPI |
| 82 | * controller drivers should use it. |
| 83 | * |
| 84 | * This function should be called after the DMA operation has finished and is |
| 85 | * only valid if the previous spi_controller_dma_map_mem_op_data() call |
| 86 | * returned 0. |
| 87 | * |
| 88 | * Return: 0 in case of success, a negative error code otherwise. |
| 89 | */ |
| 90 | void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr, |
| 91 | const struct spi_mem_op *op, |
| 92 | struct sg_table *sgt) |
| 93 | { |
| 94 | struct device *dmadev; |
| 95 | |
| 96 | if (!op->data.nbytes) |
| 97 | return; |
| 98 | |
| 99 | if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx) |
| 100 | dmadev = ctlr->dma_tx->device->dev; |
| 101 | else if (op->data.dir == SPI_MEM_DATA_IN && ctlr->dma_rx) |
| 102 | dmadev = ctlr->dma_rx->device->dev; |
| 103 | else |
| 104 | dmadev = ctlr->dev.parent; |
| 105 | |
| 106 | spi_unmap_buf(ctlr, dmadev, sgt, |
| 107 | op->data.dir == SPI_MEM_DATA_IN ? |
| 108 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
| 109 | } |
| 110 | EXPORT_SYMBOL_GPL(spi_controller_dma_unmap_mem_op_data); |
| 111 | #endif /* __UBOOT__ */ |
| 112 | |
| 113 | static int spi_check_buswidth_req(struct spi_slave *slave, u8 buswidth, bool tx) |
| 114 | { |
| 115 | u32 mode = slave->mode; |
| 116 | |
| 117 | switch (buswidth) { |
| 118 | case 1: |
| 119 | return 0; |
| 120 | |
| 121 | case 2: |
| 122 | if ((tx && (mode & (SPI_TX_DUAL | SPI_TX_QUAD))) || |
| 123 | (!tx && (mode & (SPI_RX_DUAL | SPI_RX_QUAD)))) |
| 124 | return 0; |
| 125 | |
| 126 | break; |
| 127 | |
| 128 | case 4: |
| 129 | if ((tx && (mode & SPI_TX_QUAD)) || |
| 130 | (!tx && (mode & SPI_RX_QUAD))) |
| 131 | return 0; |
| 132 | |
| 133 | break; |
Vignesh Raghavendra | 658df8b | 2019-12-05 15:46:05 +0530 | [diff] [blame] | 134 | case 8: |
| 135 | if ((tx && (mode & SPI_TX_OCTAL)) || |
| 136 | (!tx && (mode & SPI_RX_OCTAL))) |
| 137 | return 0; |
| 138 | |
| 139 | break; |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 140 | |
| 141 | default: |
| 142 | break; |
| 143 | } |
| 144 | |
| 145 | return -ENOTSUPP; |
| 146 | } |
| 147 | |
Pratyush Yadav | 5752d6a | 2021-06-26 00:47:06 +0530 | [diff] [blame] | 148 | static bool spi_mem_check_buswidth(struct spi_slave *slave, |
| 149 | const struct spi_mem_op *op) |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 150 | { |
| 151 | if (spi_check_buswidth_req(slave, op->cmd.buswidth, true)) |
| 152 | return false; |
| 153 | |
| 154 | if (op->addr.nbytes && |
| 155 | spi_check_buswidth_req(slave, op->addr.buswidth, true)) |
| 156 | return false; |
| 157 | |
| 158 | if (op->dummy.nbytes && |
| 159 | spi_check_buswidth_req(slave, op->dummy.buswidth, true)) |
| 160 | return false; |
| 161 | |
Tudor Ambarus | 790c169 | 2020-03-20 09:35:31 +0000 | [diff] [blame] | 162 | if (op->data.dir != SPI_MEM_NO_DATA && |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 163 | spi_check_buswidth_req(slave, op->data.buswidth, |
| 164 | op->data.dir == SPI_MEM_DATA_OUT)) |
| 165 | return false; |
| 166 | |
Pratyush Yadav | 5752d6a | 2021-06-26 00:47:06 +0530 | [diff] [blame] | 167 | return true; |
| 168 | } |
| 169 | |
| 170 | bool spi_mem_dtr_supports_op(struct spi_slave *slave, |
| 171 | const struct spi_mem_op *op) |
| 172 | { |
| 173 | if (op->cmd.buswidth == 8 && op->cmd.nbytes % 2) |
| 174 | return false; |
| 175 | |
| 176 | if (op->addr.nbytes && op->addr.buswidth == 8 && op->addr.nbytes % 2) |
| 177 | return false; |
| 178 | |
| 179 | if (op->dummy.nbytes && op->dummy.buswidth == 8 && op->dummy.nbytes % 2) |
| 180 | return false; |
| 181 | |
| 182 | if (op->data.dir != SPI_MEM_NO_DATA && |
| 183 | op->dummy.buswidth == 8 && op->data.nbytes % 2) |
| 184 | return false; |
| 185 | |
| 186 | return spi_mem_check_buswidth(slave, op); |
| 187 | } |
| 188 | EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op); |
| 189 | |
| 190 | bool spi_mem_default_supports_op(struct spi_slave *slave, |
| 191 | const struct spi_mem_op *op) |
| 192 | { |
Pratyush Yadav | a1eb40b | 2021-06-26 00:47:03 +0530 | [diff] [blame] | 193 | if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) |
| 194 | return false; |
| 195 | |
Pratyush Yadav | d15de62 | 2021-06-26 00:47:04 +0530 | [diff] [blame] | 196 | if (op->cmd.nbytes != 1) |
| 197 | return false; |
| 198 | |
Pratyush Yadav | 5752d6a | 2021-06-26 00:47:06 +0530 | [diff] [blame] | 199 | return spi_mem_check_buswidth(slave, op); |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 200 | } |
| 201 | EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); |
| 202 | |
| 203 | /** |
| 204 | * spi_mem_supports_op() - Check if a memory device and the controller it is |
| 205 | * connected to support a specific memory operation |
| 206 | * @slave: the SPI device |
| 207 | * @op: the memory operation to check |
| 208 | * |
| 209 | * Some controllers are only supporting Single or Dual IOs, others might only |
| 210 | * support specific opcodes, or it can even be that the controller and device |
| 211 | * both support Quad IOs but the hardware prevents you from using it because |
| 212 | * only 2 IO lines are connected. |
| 213 | * |
| 214 | * This function checks whether a specific operation is supported. |
| 215 | * |
| 216 | * Return: true if @op is supported, false otherwise. |
| 217 | */ |
| 218 | bool spi_mem_supports_op(struct spi_slave *slave, |
| 219 | const struct spi_mem_op *op) |
| 220 | { |
| 221 | struct udevice *bus = slave->dev->parent; |
| 222 | struct dm_spi_ops *ops = spi_get_ops(bus); |
| 223 | |
| 224 | if (ops->mem_ops && ops->mem_ops->supports_op) |
| 225 | return ops->mem_ops->supports_op(slave, op); |
| 226 | |
| 227 | return spi_mem_default_supports_op(slave, op); |
| 228 | } |
| 229 | EXPORT_SYMBOL_GPL(spi_mem_supports_op); |
| 230 | |
| 231 | /** |
| 232 | * spi_mem_exec_op() - Execute a memory operation |
| 233 | * @slave: the SPI device |
| 234 | * @op: the memory operation to execute |
| 235 | * |
| 236 | * Executes a memory operation. |
| 237 | * |
| 238 | * This function first checks that @op is supported and then tries to execute |
| 239 | * it. |
| 240 | * |
| 241 | * Return: 0 in case of success, a negative error code otherwise. |
| 242 | */ |
| 243 | int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) |
| 244 | { |
| 245 | struct udevice *bus = slave->dev->parent; |
| 246 | struct dm_spi_ops *ops = spi_get_ops(bus); |
| 247 | unsigned int pos = 0; |
| 248 | const u8 *tx_buf = NULL; |
| 249 | u8 *rx_buf = NULL; |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 250 | int op_len; |
| 251 | u32 flag; |
| 252 | int ret; |
| 253 | int i; |
| 254 | |
| 255 | if (!spi_mem_supports_op(slave, op)) |
| 256 | return -ENOTSUPP; |
| 257 | |
Vignesh R | 7609448 | 2019-02-05 11:29:14 +0530 | [diff] [blame] | 258 | ret = spi_claim_bus(slave); |
| 259 | if (ret < 0) |
| 260 | return ret; |
| 261 | |
Bernhard Messerklinger | 567a3eb | 2019-03-26 10:01:24 +0100 | [diff] [blame] | 262 | if (ops->mem_ops && ops->mem_ops->exec_op) { |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 263 | #ifndef __UBOOT__ |
| 264 | /* |
| 265 | * Flush the message queue before executing our SPI memory |
| 266 | * operation to prevent preemption of regular SPI transfers. |
| 267 | */ |
| 268 | spi_flush_queue(ctlr); |
| 269 | |
| 270 | if (ctlr->auto_runtime_pm) { |
| 271 | ret = pm_runtime_get_sync(ctlr->dev.parent); |
| 272 | if (ret < 0) { |
| 273 | dev_err(&ctlr->dev, |
| 274 | "Failed to power device: %d\n", |
| 275 | ret); |
| 276 | return ret; |
| 277 | } |
| 278 | } |
| 279 | |
| 280 | mutex_lock(&ctlr->bus_lock_mutex); |
| 281 | mutex_lock(&ctlr->io_mutex); |
| 282 | #endif |
| 283 | ret = ops->mem_ops->exec_op(slave, op); |
Vignesh R | 7609448 | 2019-02-05 11:29:14 +0530 | [diff] [blame] | 284 | |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 285 | #ifndef __UBOOT__ |
| 286 | mutex_unlock(&ctlr->io_mutex); |
| 287 | mutex_unlock(&ctlr->bus_lock_mutex); |
| 288 | |
| 289 | if (ctlr->auto_runtime_pm) |
| 290 | pm_runtime_put(ctlr->dev.parent); |
| 291 | #endif |
| 292 | |
| 293 | /* |
| 294 | * Some controllers only optimize specific paths (typically the |
| 295 | * read path) and expect the core to use the regular SPI |
| 296 | * interface in other cases. |
| 297 | */ |
Vignesh R | 7609448 | 2019-02-05 11:29:14 +0530 | [diff] [blame] | 298 | if (!ret || ret != -ENOTSUPP) { |
| 299 | spi_release_bus(slave); |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 300 | return ret; |
Vignesh R | 7609448 | 2019-02-05 11:29:14 +0530 | [diff] [blame] | 301 | } |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | #ifndef __UBOOT__ |
Pratyush Yadav | d15de62 | 2021-06-26 00:47:04 +0530 | [diff] [blame] | 305 | tmpbufsize = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 306 | |
| 307 | /* |
| 308 | * Allocate a buffer to transmit the CMD, ADDR cycles with kmalloc() so |
| 309 | * we're guaranteed that this buffer is DMA-able, as required by the |
| 310 | * SPI layer. |
| 311 | */ |
| 312 | tmpbuf = kzalloc(tmpbufsize, GFP_KERNEL | GFP_DMA); |
| 313 | if (!tmpbuf) |
| 314 | return -ENOMEM; |
| 315 | |
| 316 | spi_message_init(&msg); |
| 317 | |
| 318 | tmpbuf[0] = op->cmd.opcode; |
| 319 | xfers[xferpos].tx_buf = tmpbuf; |
Pratyush Yadav | d15de62 | 2021-06-26 00:47:04 +0530 | [diff] [blame] | 320 | xfers[xferpos].len = op->cmd.nbytes; |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 321 | xfers[xferpos].tx_nbits = op->cmd.buswidth; |
| 322 | spi_message_add_tail(&xfers[xferpos], &msg); |
| 323 | xferpos++; |
| 324 | totalxferlen++; |
| 325 | |
| 326 | if (op->addr.nbytes) { |
| 327 | int i; |
| 328 | |
| 329 | for (i = 0; i < op->addr.nbytes; i++) |
| 330 | tmpbuf[i + 1] = op->addr.val >> |
| 331 | (8 * (op->addr.nbytes - i - 1)); |
| 332 | |
| 333 | xfers[xferpos].tx_buf = tmpbuf + 1; |
| 334 | xfers[xferpos].len = op->addr.nbytes; |
| 335 | xfers[xferpos].tx_nbits = op->addr.buswidth; |
| 336 | spi_message_add_tail(&xfers[xferpos], &msg); |
| 337 | xferpos++; |
| 338 | totalxferlen += op->addr.nbytes; |
| 339 | } |
| 340 | |
| 341 | if (op->dummy.nbytes) { |
| 342 | memset(tmpbuf + op->addr.nbytes + 1, 0xff, op->dummy.nbytes); |
| 343 | xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1; |
| 344 | xfers[xferpos].len = op->dummy.nbytes; |
| 345 | xfers[xferpos].tx_nbits = op->dummy.buswidth; |
| 346 | spi_message_add_tail(&xfers[xferpos], &msg); |
| 347 | xferpos++; |
| 348 | totalxferlen += op->dummy.nbytes; |
| 349 | } |
| 350 | |
| 351 | if (op->data.nbytes) { |
| 352 | if (op->data.dir == SPI_MEM_DATA_IN) { |
| 353 | xfers[xferpos].rx_buf = op->data.buf.in; |
| 354 | xfers[xferpos].rx_nbits = op->data.buswidth; |
| 355 | } else { |
| 356 | xfers[xferpos].tx_buf = op->data.buf.out; |
| 357 | xfers[xferpos].tx_nbits = op->data.buswidth; |
| 358 | } |
| 359 | |
| 360 | xfers[xferpos].len = op->data.nbytes; |
| 361 | spi_message_add_tail(&xfers[xferpos], &msg); |
| 362 | xferpos++; |
| 363 | totalxferlen += op->data.nbytes; |
| 364 | } |
| 365 | |
| 366 | ret = spi_sync(slave, &msg); |
| 367 | |
| 368 | kfree(tmpbuf); |
| 369 | |
| 370 | if (ret) |
| 371 | return ret; |
| 372 | |
| 373 | if (msg.actual_length != totalxferlen) |
| 374 | return -EIO; |
| 375 | #else |
| 376 | |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 377 | if (op->data.nbytes) { |
| 378 | if (op->data.dir == SPI_MEM_DATA_IN) |
| 379 | rx_buf = op->data.buf.in; |
| 380 | else |
| 381 | tx_buf = op->data.buf.out; |
| 382 | } |
| 383 | |
Pratyush Yadav | d15de62 | 2021-06-26 00:47:04 +0530 | [diff] [blame] | 384 | op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; |
Simon Glass | ca2abb7 | 2019-05-18 11:59:54 -0600 | [diff] [blame] | 385 | |
| 386 | /* |
| 387 | * Avoid using malloc() here so that we can use this code in SPL where |
| 388 | * simple malloc may be used. That implementation does not allow free() |
| 389 | * so repeated calls to this code can exhaust the space. |
| 390 | * |
| 391 | * The value of op_len is small, since it does not include the actual |
| 392 | * data being sent, only the op-code and address. In fact, it should be |
| 393 | * possible to just use a small fixed value here instead of op_len. |
| 394 | */ |
| 395 | u8 op_buf[op_len]; |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 396 | |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 397 | op_buf[pos++] = op->cmd.opcode; |
| 398 | |
| 399 | if (op->addr.nbytes) { |
| 400 | for (i = 0; i < op->addr.nbytes; i++) |
| 401 | op_buf[pos + i] = op->addr.val >> |
| 402 | (8 * (op->addr.nbytes - i - 1)); |
| 403 | |
| 404 | pos += op->addr.nbytes; |
| 405 | } |
| 406 | |
| 407 | if (op->dummy.nbytes) |
| 408 | memset(op_buf + pos, 0xff, op->dummy.nbytes); |
| 409 | |
| 410 | /* 1st transfer: opcode + address + dummy cycles */ |
| 411 | flag = SPI_XFER_BEGIN; |
| 412 | /* Make sure to set END bit if no tx or rx data messages follow */ |
| 413 | if (!tx_buf && !rx_buf) |
| 414 | flag |= SPI_XFER_END; |
| 415 | |
| 416 | ret = spi_xfer(slave, op_len * 8, op_buf, NULL, flag); |
| 417 | if (ret) |
| 418 | return ret; |
| 419 | |
| 420 | /* 2nd transfer: rx or tx data path */ |
| 421 | if (tx_buf || rx_buf) { |
| 422 | ret = spi_xfer(slave, op->data.nbytes * 8, tx_buf, |
| 423 | rx_buf, SPI_XFER_END); |
| 424 | if (ret) |
| 425 | return ret; |
| 426 | } |
| 427 | |
| 428 | spi_release_bus(slave); |
| 429 | |
| 430 | for (i = 0; i < pos; i++) |
| 431 | debug("%02x ", op_buf[i]); |
| 432 | debug("| [%dB %s] ", |
| 433 | tx_buf || rx_buf ? op->data.nbytes : 0, |
| 434 | tx_buf || rx_buf ? (tx_buf ? "out" : "in") : "-"); |
| 435 | for (i = 0; i < op->data.nbytes; i++) |
| 436 | debug("%02x ", tx_buf ? tx_buf[i] : rx_buf[i]); |
| 437 | debug("[ret %d]\n", ret); |
| 438 | |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 439 | if (ret < 0) |
| 440 | return ret; |
| 441 | #endif /* __UBOOT__ */ |
| 442 | |
| 443 | return 0; |
| 444 | } |
| 445 | EXPORT_SYMBOL_GPL(spi_mem_exec_op); |
| 446 | |
| 447 | /** |
| 448 | * spi_mem_adjust_op_size() - Adjust the data size of a SPI mem operation to |
| 449 | * match controller limitations |
| 450 | * @slave: the SPI device |
| 451 | * @op: the operation to adjust |
| 452 | * |
| 453 | * Some controllers have FIFO limitations and must split a data transfer |
| 454 | * operation into multiple ones, others require a specific alignment for |
| 455 | * optimized accesses. This function allows SPI mem drivers to split a single |
| 456 | * operation into multiple sub-operations when required. |
| 457 | * |
| 458 | * Return: a negative error code if the controller can't properly adjust @op, |
| 459 | * 0 otherwise. Note that @op->data.nbytes will be updated if @op |
| 460 | * can't be handled in a single step. |
| 461 | */ |
| 462 | int spi_mem_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op) |
| 463 | { |
| 464 | struct udevice *bus = slave->dev->parent; |
| 465 | struct dm_spi_ops *ops = spi_get_ops(bus); |
| 466 | |
| 467 | if (ops->mem_ops && ops->mem_ops->adjust_op_size) |
| 468 | return ops->mem_ops->adjust_op_size(slave, op); |
| 469 | |
Vignesh R | 12563f7 | 2019-02-05 11:29:13 +0530 | [diff] [blame] | 470 | if (!ops->mem_ops || !ops->mem_ops->exec_op) { |
| 471 | unsigned int len; |
| 472 | |
Pratyush Yadav | d15de62 | 2021-06-26 00:47:04 +0530 | [diff] [blame] | 473 | len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; |
Vignesh R | 12563f7 | 2019-02-05 11:29:13 +0530 | [diff] [blame] | 474 | if (slave->max_write_size && len > slave->max_write_size) |
| 475 | return -EINVAL; |
| 476 | |
Ye Li | 535b1fd | 2019-07-10 09:23:51 +0000 | [diff] [blame] | 477 | if (op->data.dir == SPI_MEM_DATA_IN) { |
| 478 | if (slave->max_read_size) |
| 479 | op->data.nbytes = min(op->data.nbytes, |
Vignesh R | 12563f7 | 2019-02-05 11:29:13 +0530 | [diff] [blame] | 480 | slave->max_read_size); |
Ye Li | 535b1fd | 2019-07-10 09:23:51 +0000 | [diff] [blame] | 481 | } else if (slave->max_write_size) { |
Vignesh R | 12563f7 | 2019-02-05 11:29:13 +0530 | [diff] [blame] | 482 | op->data.nbytes = min(op->data.nbytes, |
| 483 | slave->max_write_size - len); |
Ye Li | 535b1fd | 2019-07-10 09:23:51 +0000 | [diff] [blame] | 484 | } |
Vignesh R | 12563f7 | 2019-02-05 11:29:13 +0530 | [diff] [blame] | 485 | |
| 486 | if (!op->data.nbytes) |
| 487 | return -EINVAL; |
| 488 | } |
| 489 | |
Boris Brezillon | d13f5b2 | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 490 | return 0; |
| 491 | } |
| 492 | EXPORT_SYMBOL_GPL(spi_mem_adjust_op_size); |
| 493 | |
| 494 | #ifndef __UBOOT__ |
| 495 | static inline struct spi_mem_driver *to_spi_mem_drv(struct device_driver *drv) |
| 496 | { |
| 497 | return container_of(drv, struct spi_mem_driver, spidrv.driver); |
| 498 | } |
| 499 | |
| 500 | static int spi_mem_probe(struct spi_device *spi) |
| 501 | { |
| 502 | struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver); |
| 503 | struct spi_mem *mem; |
| 504 | |
| 505 | mem = devm_kzalloc(&spi->dev, sizeof(*mem), GFP_KERNEL); |
| 506 | if (!mem) |
| 507 | return -ENOMEM; |
| 508 | |
| 509 | mem->spi = spi; |
| 510 | spi_set_drvdata(spi, mem); |
| 511 | |
| 512 | return memdrv->probe(mem); |
| 513 | } |
| 514 | |
| 515 | static int spi_mem_remove(struct spi_device *spi) |
| 516 | { |
| 517 | struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver); |
| 518 | struct spi_mem *mem = spi_get_drvdata(spi); |
| 519 | |
| 520 | if (memdrv->remove) |
| 521 | return memdrv->remove(mem); |
| 522 | |
| 523 | return 0; |
| 524 | } |
| 525 | |
| 526 | static void spi_mem_shutdown(struct spi_device *spi) |
| 527 | { |
| 528 | struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver); |
| 529 | struct spi_mem *mem = spi_get_drvdata(spi); |
| 530 | |
| 531 | if (memdrv->shutdown) |
| 532 | memdrv->shutdown(mem); |
| 533 | } |
| 534 | |
| 535 | /** |
| 536 | * spi_mem_driver_register_with_owner() - Register a SPI memory driver |
| 537 | * @memdrv: the SPI memory driver to register |
| 538 | * @owner: the owner of this driver |
| 539 | * |
| 540 | * Registers a SPI memory driver. |
| 541 | * |
| 542 | * Return: 0 in case of success, a negative error core otherwise. |
| 543 | */ |
| 544 | |
| 545 | int spi_mem_driver_register_with_owner(struct spi_mem_driver *memdrv, |
| 546 | struct module *owner) |
| 547 | { |
| 548 | memdrv->spidrv.probe = spi_mem_probe; |
| 549 | memdrv->spidrv.remove = spi_mem_remove; |
| 550 | memdrv->spidrv.shutdown = spi_mem_shutdown; |
| 551 | |
| 552 | return __spi_register_driver(owner, &memdrv->spidrv); |
| 553 | } |
| 554 | EXPORT_SYMBOL_GPL(spi_mem_driver_register_with_owner); |
| 555 | |
| 556 | /** |
| 557 | * spi_mem_driver_unregister_with_owner() - Unregister a SPI memory driver |
| 558 | * @memdrv: the SPI memory driver to unregister |
| 559 | * |
| 560 | * Unregisters a SPI memory driver. |
| 561 | */ |
| 562 | void spi_mem_driver_unregister(struct spi_mem_driver *memdrv) |
| 563 | { |
| 564 | spi_unregister_driver(&memdrv->spidrv); |
| 565 | } |
| 566 | EXPORT_SYMBOL_GPL(spi_mem_driver_unregister); |
| 567 | #endif /* __UBOOT__ */ |