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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Matt Waddel23b93e12011-04-16 11:54:07 +00002/*
3 * ARM PrimeCell MultiMedia Card Interface - PL180
4 *
5 * Copyright (C) ST-Ericsson SA 2010
6 *
7 * Author: Ulf Hansson <ulf.hansson@stericsson.com>
8 * Author: Martin Lundholm <martin.xa.lundholm@stericsson.com>
9 * Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org>
Matt Waddel23b93e12011-04-16 11:54:07 +000010 */
11
12/* #define DEBUG */
13
Matt Waddel23b93e12011-04-16 11:54:07 +000014#include "common.h"
Patrice Chotard5f256fe2017-10-23 10:57:33 +020015#include <clk.h>
Matt Waddel23b93e12011-04-16 11:54:07 +000016#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060017#include <log.h>
Matt Waddel23b93e12011-04-16 11:54:07 +000018#include <malloc.h>
Patrice Chotard3c0dbed2017-10-23 10:57:31 +020019#include <mmc.h>
Simon Glass336d4612020-02-03 07:36:16 -070020#include <dm/device_compat.h>
Patrice Chotard3c0dbed2017-10-23 10:57:31 +020021
Patrice Chotard3c0dbed2017-10-23 10:57:31 +020022#include <asm/io.h>
Patrice Chotard5829fe22017-10-23 10:57:34 +020023#include <asm-generic/gpio.h>
24
25#include "arm_pl180_mmci.h"
Simon Glassc05ed002020-05-10 11:40:11 -060026#include <linux/delay.h>
Patrice Chotard3c0dbed2017-10-23 10:57:31 +020027
28#ifdef CONFIG_DM_MMC
29#include <dm.h>
Patrice Chotard3c0dbed2017-10-23 10:57:31 +020030#define MMC_CLOCK_MAX 48000000
31#define MMC_CLOCK_MIN 400000
32
33struct arm_pl180_mmc_plat {
34 struct mmc_config cfg;
35 struct mmc mmc;
36};
37#endif
Matt Waddel23b93e12011-04-16 11:54:07 +000038
Matt Waddel23b93e12011-04-16 11:54:07 +000039static int wait_for_command_end(struct mmc *dev, struct mmc_cmd *cmd)
40{
41 u32 hoststatus, statusmask;
John Rigby10ed93d2012-07-31 08:59:31 +000042 struct pl180_mmc_host *host = dev->priv;
Matt Waddel23b93e12011-04-16 11:54:07 +000043
44 statusmask = SDI_STA_CTIMEOUT | SDI_STA_CCRCFAIL;
45 if ((cmd->resp_type & MMC_RSP_PRESENT))
46 statusmask |= SDI_STA_CMDREND;
47 else
48 statusmask |= SDI_STA_CMDSENT;
49
50 do
51 hoststatus = readl(&host->base->status) & statusmask;
52 while (!hoststatus);
53
54 writel(statusmask, &host->base->status_clear);
55 if (hoststatus & SDI_STA_CTIMEOUT) {
John Rigby10ed93d2012-07-31 08:59:31 +000056 debug("CMD%d time out\n", cmd->cmdidx);
Jaehoon Chung915ffa52016-07-19 16:33:36 +090057 return -ETIMEDOUT;
Matt Waddel23b93e12011-04-16 11:54:07 +000058 } else if ((hoststatus & SDI_STA_CCRCFAIL) &&
Andy Fleming95b01c42012-09-06 15:23:13 -050059 (cmd->resp_type & MMC_RSP_CRC)) {
Matt Waddel23b93e12011-04-16 11:54:07 +000060 printf("CMD%d CRC error\n", cmd->cmdidx);
61 return -EILSEQ;
62 }
63
64 if (cmd->resp_type & MMC_RSP_PRESENT) {
65 cmd->response[0] = readl(&host->base->response0);
66 cmd->response[1] = readl(&host->base->response1);
67 cmd->response[2] = readl(&host->base->response2);
68 cmd->response[3] = readl(&host->base->response3);
69 debug("CMD%d response[0]:0x%08X, response[1]:0x%08X, "
70 "response[2]:0x%08X, response[3]:0x%08X\n",
71 cmd->cmdidx, cmd->response[0], cmd->response[1],
72 cmd->response[2], cmd->response[3]);
73 }
74
75 return 0;
76}
77
78/* send command to the mmc card and wait for results */
79static int do_command(struct mmc *dev, struct mmc_cmd *cmd)
80{
81 int result;
82 u32 sdi_cmd = 0;
John Rigby10ed93d2012-07-31 08:59:31 +000083 struct pl180_mmc_host *host = dev->priv;
Matt Waddel23b93e12011-04-16 11:54:07 +000084
85 sdi_cmd = ((cmd->cmdidx & SDI_CMD_CMDINDEX_MASK) | SDI_CMD_CPSMEN);
86
87 if (cmd->resp_type) {
88 sdi_cmd |= SDI_CMD_WAITRESP;
89 if (cmd->resp_type & MMC_RSP_136)
90 sdi_cmd |= SDI_CMD_LONGRESP;
91 }
92
93 writel((u32)cmd->cmdarg, &host->base->argument);
94 udelay(COMMAND_REG_DELAY);
95 writel(sdi_cmd, &host->base->command);
96 result = wait_for_command_end(dev, cmd);
97
98 /* After CMD2 set RCA to a none zero value. */
99 if ((result == 0) && (cmd->cmdidx == MMC_CMD_ALL_SEND_CID))
100 dev->rca = 10;
101
102 /* After CMD3 open drain is switched off and push pull is used. */
103 if ((result == 0) && (cmd->cmdidx == MMC_CMD_SET_RELATIVE_ADDR)) {
104 u32 sdi_pwr = readl(&host->base->power) & ~SDI_PWR_OPD;
105 writel(sdi_pwr, &host->base->power);
106 }
107
108 return result;
109}
110
111static int read_bytes(struct mmc *dev, u32 *dest, u32 blkcount, u32 blksize)
112{
113 u32 *tempbuff = dest;
Matt Waddel23b93e12011-04-16 11:54:07 +0000114 u64 xfercount = blkcount * blksize;
John Rigby10ed93d2012-07-31 08:59:31 +0000115 struct pl180_mmc_host *host = dev->priv;
Matt Waddel23b93e12011-04-16 11:54:07 +0000116 u32 status, status_err;
117
118 debug("read_bytes: blkcount=%u blksize=%u\n", blkcount, blksize);
119
120 status = readl(&host->base->status);
121 status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
122 SDI_STA_RXOVERR);
Matt Waddel23b93e12011-04-16 11:54:07 +0000123 while ((!status_err) && (xfercount >= sizeof(u32))) {
124 if (status & SDI_STA_RXDAVL) {
125 *(tempbuff) = readl(&host->base->fifo);
126 tempbuff++;
127 xfercount -= sizeof(u32);
128 }
129 status = readl(&host->base->status);
130 status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
131 SDI_STA_RXOVERR);
132 }
133
134 status_err = status &
135 (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND |
136 SDI_STA_RXOVERR);
137 while (!status_err) {
138 status = readl(&host->base->status);
139 status_err = status &
140 (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND |
141 SDI_STA_RXOVERR);
142 }
143
144 if (status & SDI_STA_DTIMEOUT) {
145 printf("Read data timed out, xfercount: %llu, status: 0x%08X\n",
146 xfercount, status);
147 return -ETIMEDOUT;
148 } else if (status & SDI_STA_DCRCFAIL) {
149 printf("Read data bytes CRC error: 0x%x\n", status);
150 return -EILSEQ;
151 } else if (status & SDI_STA_RXOVERR) {
152 printf("Read data RX overflow error\n");
153 return -EIO;
154 }
155
156 writel(SDI_ICR_MASK, &host->base->status_clear);
157
158 if (xfercount) {
159 printf("Read data error, xfercount: %llu\n", xfercount);
160 return -ENOBUFS;
161 }
162
163 return 0;
164}
165
166static int write_bytes(struct mmc *dev, u32 *src, u32 blkcount, u32 blksize)
167{
168 u32 *tempbuff = src;
169 int i;
170 u64 xfercount = blkcount * blksize;
John Rigby10ed93d2012-07-31 08:59:31 +0000171 struct pl180_mmc_host *host = dev->priv;
Matt Waddel23b93e12011-04-16 11:54:07 +0000172 u32 status, status_err;
173
174 debug("write_bytes: blkcount=%u blksize=%u\n", blkcount, blksize);
175
176 status = readl(&host->base->status);
177 status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT);
178 while (!status_err && xfercount) {
179 if (status & SDI_STA_TXFIFOBW) {
180 if (xfercount >= SDI_FIFO_BURST_SIZE * sizeof(u32)) {
181 for (i = 0; i < SDI_FIFO_BURST_SIZE; i++)
182 writel(*(tempbuff + i),
183 &host->base->fifo);
184 tempbuff += SDI_FIFO_BURST_SIZE;
185 xfercount -= SDI_FIFO_BURST_SIZE * sizeof(u32);
186 } else {
187 while (xfercount >= sizeof(u32)) {
188 writel(*(tempbuff), &host->base->fifo);
189 tempbuff++;
190 xfercount -= sizeof(u32);
191 }
192 }
193 }
194 status = readl(&host->base->status);
195 status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT);
196 }
197
198 status_err = status &
199 (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND);
200 while (!status_err) {
201 status = readl(&host->base->status);
202 status_err = status &
203 (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND);
204 }
205
206 if (status & SDI_STA_DTIMEOUT) {
207 printf("Write data timed out, xfercount:%llu,status:0x%08X\n",
208 xfercount, status);
209 return -ETIMEDOUT;
210 } else if (status & SDI_STA_DCRCFAIL) {
211 printf("Write data CRC error\n");
212 return -EILSEQ;
213 }
214
215 writel(SDI_ICR_MASK, &host->base->status_clear);
216
217 if (xfercount) {
218 printf("Write data error, xfercount:%llu", xfercount);
219 return -ENOBUFS;
220 }
221
222 return 0;
223}
224
225static int do_data_transfer(struct mmc *dev,
226 struct mmc_cmd *cmd,
227 struct mmc_data *data)
228{
229 int error = -ETIMEDOUT;
John Rigby10ed93d2012-07-31 08:59:31 +0000230 struct pl180_mmc_host *host = dev->priv;
Matt Waddel23b93e12011-04-16 11:54:07 +0000231 u32 blksz = 0;
232 u32 data_ctrl = 0;
233 u32 data_len = (u32) (data->blocks * data->blocksize);
234
John Rigby10ed93d2012-07-31 08:59:31 +0000235 if (!host->version2) {
236 blksz = (ffs(data->blocksize) - 1);
237 data_ctrl |= ((blksz << 4) & SDI_DCTRL_DBLKSIZE_MASK);
238 } else {
239 blksz = data->blocksize;
240 data_ctrl |= (blksz << SDI_DCTRL_DBLOCKSIZE_V2_SHIFT);
241 }
242 data_ctrl |= SDI_DCTRL_DTEN | SDI_DCTRL_BUSYMODE;
Matt Waddel23b93e12011-04-16 11:54:07 +0000243
244 writel(SDI_DTIMER_DEFAULT, &host->base->datatimer);
245 writel(data_len, &host->base->datalength);
246 udelay(DATA_REG_DELAY);
247
248 if (data->flags & MMC_DATA_READ) {
249 data_ctrl |= SDI_DCTRL_DTDIR_IN;
250 writel(data_ctrl, &host->base->datactrl);
251
252 error = do_command(dev, cmd);
253 if (error)
254 return error;
255
256 error = read_bytes(dev, (u32 *)data->dest, (u32)data->blocks,
257 (u32)data->blocksize);
258 } else if (data->flags & MMC_DATA_WRITE) {
259 error = do_command(dev, cmd);
260 if (error)
261 return error;
262
263 writel(data_ctrl, &host->base->datactrl);
264 error = write_bytes(dev, (u32 *)data->src, (u32)data->blocks,
John Rigby10ed93d2012-07-31 08:59:31 +0000265 (u32)data->blocksize);
Matt Waddel23b93e12011-04-16 11:54:07 +0000266 }
267
268 return error;
269}
270
271static int host_request(struct mmc *dev,
272 struct mmc_cmd *cmd,
273 struct mmc_data *data)
274{
275 int result;
276
277 if (data)
278 result = do_data_transfer(dev, cmd, data);
279 else
280 result = do_command(dev, cmd);
281
282 return result;
283}
284
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900285static int host_set_ios(struct mmc *dev)
Matt Waddel23b93e12011-04-16 11:54:07 +0000286{
John Rigby10ed93d2012-07-31 08:59:31 +0000287 struct pl180_mmc_host *host = dev->priv;
Matt Waddel23b93e12011-04-16 11:54:07 +0000288 u32 sdi_clkcr;
289
290 sdi_clkcr = readl(&host->base->clock);
291
292 /* Ramp up the clock rate */
293 if (dev->clock) {
294 u32 clkdiv = 0;
John Rigby10ed93d2012-07-31 08:59:31 +0000295 u32 tmp_clock;
Matt Waddel23b93e12011-04-16 11:54:07 +0000296
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200297 if (dev->clock >= dev->cfg->f_max) {
John Rigby10ed93d2012-07-31 08:59:31 +0000298 clkdiv = 0;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200299 dev->clock = dev->cfg->f_max;
John Rigby10ed93d2012-07-31 08:59:31 +0000300 } else {
301 clkdiv = (host->clock_in / dev->clock) - 2;
302 }
Matt Waddel23b93e12011-04-16 11:54:07 +0000303
John Rigby10ed93d2012-07-31 08:59:31 +0000304 tmp_clock = host->clock_in / (clkdiv + 2);
305 while (tmp_clock > dev->clock) {
306 clkdiv++;
307 tmp_clock = host->clock_in / (clkdiv + 2);
308 }
Matt Waddel23b93e12011-04-16 11:54:07 +0000309
310 if (clkdiv > SDI_CLKCR_CLKDIV_MASK)
311 clkdiv = SDI_CLKCR_CLKDIV_MASK;
312
John Rigby10ed93d2012-07-31 08:59:31 +0000313 tmp_clock = host->clock_in / (clkdiv + 2);
314 dev->clock = tmp_clock;
Matt Waddel23b93e12011-04-16 11:54:07 +0000315 sdi_clkcr &= ~(SDI_CLKCR_CLKDIV_MASK);
316 sdi_clkcr |= clkdiv;
317 }
318
319 /* Set the bus width */
320 if (dev->bus_width) {
321 u32 buswidth = 0;
322
323 switch (dev->bus_width) {
324 case 1:
325 buswidth |= SDI_CLKCR_WIDBUS_1;
326 break;
327 case 4:
328 buswidth |= SDI_CLKCR_WIDBUS_4;
329 break;
John Rigby10ed93d2012-07-31 08:59:31 +0000330 case 8:
331 buswidth |= SDI_CLKCR_WIDBUS_8;
332 break;
Matt Waddel23b93e12011-04-16 11:54:07 +0000333 default:
John Rigby10ed93d2012-07-31 08:59:31 +0000334 printf("Invalid bus width: %d\n", dev->bus_width);
Matt Waddel23b93e12011-04-16 11:54:07 +0000335 break;
336 }
337 sdi_clkcr &= ~(SDI_CLKCR_WIDBUS_MASK);
338 sdi_clkcr |= buswidth;
339 }
340
341 writel(sdi_clkcr, &host->base->clock);
342 udelay(CLK_CHANGE_DELAY);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900343
344 return 0;
Matt Waddel23b93e12011-04-16 11:54:07 +0000345}
346
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200347#ifndef CONFIG_DM_MMC
348/* MMC uses open drain drivers in the enumeration phase */
349static int mmc_host_reset(struct mmc *dev)
350{
351 struct pl180_mmc_host *host = dev->priv;
352
353 writel(host->pwr_init, &host->base->power);
354
355 return 0;
356}
357
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200358static const struct mmc_ops arm_pl180_mmci_ops = {
359 .send_cmd = host_request,
360 .set_ios = host_set_ios,
361 .init = mmc_host_reset,
362};
363
Matt Waddel23b93e12011-04-16 11:54:07 +0000364/*
365 * mmc_host_init - initialize the mmc controller.
366 * Set initial clock and power for mmc slot.
367 * Initialize mmc struct and register with mmc framework.
368 */
Patrice Chotard80150932018-07-25 17:49:07 +0200369
Patrice Chotardcb0060e2017-10-23 10:57:30 +0200370int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct mmc **mmc)
Matt Waddel23b93e12011-04-16 11:54:07 +0000371{
Matt Waddel23b93e12011-04-16 11:54:07 +0000372 u32 sdi_u32;
373
John Rigby10ed93d2012-07-31 08:59:31 +0000374 writel(host->pwr_init, &host->base->power);
375 writel(host->clkdiv_init, &host->base->clock);
Matt Waddel23b93e12011-04-16 11:54:07 +0000376 udelay(CLK_CHANGE_DELAY);
377
378 /* Disable mmc interrupts */
379 sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
380 writel(sdi_u32, &host->base->mask0);
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200381
382 host->cfg.name = host->name;
383 host->cfg.ops = &arm_pl180_mmci_ops;
Patrice Chotard80150932018-07-25 17:49:07 +0200384
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200385 /* TODO remove the duplicates */
386 host->cfg.host_caps = host->caps;
387 host->cfg.voltages = host->voltages;
388 host->cfg.f_min = host->clock_min;
389 host->cfg.f_max = host->clock_max;
390 if (host->b_max != 0)
391 host->cfg.b_max = host->b_max;
392 else
393 host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
394
Patrice Chotardcb0060e2017-10-23 10:57:30 +0200395 *mmc = mmc_create(&host->cfg, host);
396 if (!*mmc)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200397 return -1;
Patrice Chotardcb0060e2017-10-23 10:57:30 +0200398 debug("registered mmc interface number is:%d\n",
399 (*mmc)->block_dev.devnum);
Matt Waddel23b93e12011-04-16 11:54:07 +0000400
401 return 0;
402}
Patrice Chotard80150932018-07-25 17:49:07 +0200403#endif
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200404
405#ifdef CONFIG_DM_MMC
Patrice Chotard80150932018-07-25 17:49:07 +0200406static void arm_pl180_mmc_init(struct pl180_mmc_host *host)
407{
408 u32 sdi_u32;
409
410 writel(host->pwr_init, &host->base->power);
411 writel(host->clkdiv_init, &host->base->clock);
412 udelay(CLK_CHANGE_DELAY);
413
414 /* Disable mmc interrupts */
415 sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
416 writel(sdi_u32, &host->base->mask0);
417}
418
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200419static int arm_pl180_mmc_probe(struct udevice *dev)
420{
Simon Glassc69cda22020-12-03 16:55:20 -0700421 struct arm_pl180_mmc_plat *pdata = dev_get_plat(dev);
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200422 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
423 struct mmc *mmc = &pdata->mmc;
Simon Glass0fd3d912020-12-22 19:30:28 -0700424 struct pl180_mmc_host *host = dev_get_priv(dev);
Patrice Chotard80150932018-07-25 17:49:07 +0200425 struct mmc_config *cfg = &pdata->cfg;
Patrice Chotard5f256fe2017-10-23 10:57:33 +0200426 struct clk clk;
Patrice Chotard6f41d1a2018-12-05 14:04:32 +0100427 u32 periphid;
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200428 int ret;
429
Patrice Chotard5f256fe2017-10-23 10:57:33 +0200430 ret = clk_get_by_index(dev, 0, &clk);
431 if (ret < 0)
432 return ret;
433
434 ret = clk_enable(&clk);
435 if (ret) {
Patrice Chotard43d36a02018-07-25 17:49:08 +0200436 clk_free(&clk);
Patrice Chotard5f256fe2017-10-23 10:57:33 +0200437 dev_err(dev, "failed to enable clock\n");
438 return ret;
439 }
440
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200441 host->pwr_init = INIT_PWR;
442 host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN |
443 SDI_CLKCR_HWFC_EN;
Patrice Chotard5f256fe2017-10-23 10:57:33 +0200444 host->clock_in = clk_get_rate(&clk);
Patrice Chotard6f41d1a2018-12-05 14:04:32 +0100445
Patrice Chotard80150932018-07-25 17:49:07 +0200446 cfg->name = dev->name;
447 cfg->voltages = VOLTAGE_WINDOW_SD;
448 cfg->host_caps = 0;
449 cfg->f_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
Stephan Gerhold4daf2ec2021-07-06 16:54:35 +0200450 cfg->f_max = MMC_CLOCK_MAX;
Patrice Chotard80150932018-07-25 17:49:07 +0200451 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
452
Stephan Gerholdd890f232021-07-06 16:54:36 +0200453 periphid = dev_read_u32_default(dev, "arm,primecell-periphid", 0);
454 switch (periphid) {
455 case STM32_MMCI_ID: /* stm32 variant */
456 host->version2 = false;
457 break;
458 case UX500V2_MMCI_ID:
459 host->pwr_init = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON;
460 host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 | SDI_CLKCR_CLKEN |
461 SDI_CLKCR_HWFC_EN;
462 cfg->voltages = VOLTAGE_WINDOW_MMC;
463 cfg->f_min = host->clock_in / (2 + SDI_CLKCR_CLKDIV_INIT_V2);
464 host->version2 = true;
465 break;
466 default:
467 host->version2 = true;
468 }
469
Patrice Chotard5829fe22017-10-23 10:57:34 +0200470 gpio_request_by_name(dev, "cd-gpios", 0, &host->cd_gpio, GPIOD_IS_IN);
471
Stephan Gerhold4daf2ec2021-07-06 16:54:35 +0200472 ret = mmc_of_parse(dev, cfg);
473 if (ret)
474 return ret;
Patrice Chotard9035bb72017-10-23 10:57:32 +0200475
Patrice Chotard80150932018-07-25 17:49:07 +0200476 arm_pl180_mmc_init(host);
477 mmc->priv = host;
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200478 mmc->dev = dev;
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200479 upriv->mmc = mmc;
480
481 return 0;
482}
483
Patrice Chotard80150932018-07-25 17:49:07 +0200484int arm_pl180_mmc_bind(struct udevice *dev)
485{
Simon Glassc69cda22020-12-03 16:55:20 -0700486 struct arm_pl180_mmc_plat *plat = dev_get_plat(dev);
Patrice Chotard80150932018-07-25 17:49:07 +0200487
488 return mmc_bind(dev, &plat->mmc, &plat->cfg);
489}
490
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200491static int dm_host_request(struct udevice *dev, struct mmc_cmd *cmd,
492 struct mmc_data *data)
493{
494 struct mmc *mmc = mmc_get_mmc_dev(dev);
495
496 return host_request(mmc, cmd, data);
497}
498
499static int dm_host_set_ios(struct udevice *dev)
500{
501 struct mmc *mmc = mmc_get_mmc_dev(dev);
502
503 return host_set_ios(mmc);
504}
505
Patrice Chotard5829fe22017-10-23 10:57:34 +0200506static int dm_mmc_getcd(struct udevice *dev)
507{
Simon Glass0fd3d912020-12-22 19:30:28 -0700508 struct pl180_mmc_host *host = dev_get_priv(dev);
Patrice Chotard5829fe22017-10-23 10:57:34 +0200509 int value = 1;
510
Patrice Chotardfa911562018-07-25 17:49:09 +0200511 if (dm_gpio_is_valid(&host->cd_gpio))
Patrice Chotard5829fe22017-10-23 10:57:34 +0200512 value = dm_gpio_get_value(&host->cd_gpio);
Patrice Chotard5829fe22017-10-23 10:57:34 +0200513
514 return value;
515}
516
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200517static const struct dm_mmc_ops arm_pl180_dm_mmc_ops = {
518 .send_cmd = dm_host_request,
519 .set_ios = dm_host_set_ios,
Patrice Chotard5829fe22017-10-23 10:57:34 +0200520 .get_cd = dm_mmc_getcd,
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200521};
522
Simon Glassd1998a92020-12-03 16:55:21 -0700523static int arm_pl180_mmc_of_to_plat(struct udevice *dev)
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200524{
Simon Glass0fd3d912020-12-22 19:30:28 -0700525 struct pl180_mmc_host *host = dev_get_priv(dev);
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200526
Stephan Gerhold19e1da02021-07-06 16:54:34 +0200527 host->base = dev_read_addr_ptr(dev);
528 if (!host->base)
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200529 return -EINVAL;
530
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200531 return 0;
532}
533
534static const struct udevice_id arm_pl180_mmc_match[] = {
Patrice Chotard6f41d1a2018-12-05 14:04:32 +0100535 { .compatible = "arm,pl180" },
Stephan Gerhold936e9cd2021-07-06 16:54:33 +0200536 { .compatible = "arm,pl18x" },
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200537 { /* sentinel */ }
538};
539
540U_BOOT_DRIVER(arm_pl180_mmc) = {
541 .name = "arm_pl180_mmc",
542 .id = UCLASS_MMC,
543 .of_match = arm_pl180_mmc_match,
544 .ops = &arm_pl180_dm_mmc_ops,
545 .probe = arm_pl180_mmc_probe,
Simon Glassd1998a92020-12-03 16:55:21 -0700546 .of_to_plat = arm_pl180_mmc_of_to_plat,
Patrice Chotard80150932018-07-25 17:49:07 +0200547 .bind = arm_pl180_mmc_bind,
Simon Glass41575d82020-12-03 16:55:17 -0700548 .priv_auto = sizeof(struct pl180_mmc_host),
Simon Glasscaa4daa2020-12-03 16:55:18 -0700549 .plat_auto = sizeof(struct arm_pl180_mmc_plat),
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200550};
551#endif