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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Tom Warren3f82b1d2011-01-27 10:58:05 +00002/*
Tom Warren7aaa5a62015-03-04 16:36:00 -07003 * (C) Copyright 2010-2015
Tom Warren3f82b1d2011-01-27 10:58:05 +00004 * NVIDIA Corporation <www.nvidia.com>
Tom Warren3f82b1d2011-01-27 10:58:05 +00005 */
6
7#include <common.h>
Simon Glass9edefc22019-11-14 12:57:37 -07008#include <cpu_func.h>
Thomas Chou18746262015-11-19 21:48:11 +08009#include <dm.h>
Simon Glass9b4a2052019-12-28 10:45:05 -070010#include <init.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Thomas Chou18746262015-11-19 21:48:11 +080012#include <ns16550.h>
Simon Glass537e9672015-05-13 07:02:29 -060013#include <spl.h>
Simon Glass90526e92020-05-10 11:39:56 -060014#include <asm/cache.h>
Simon Glass401d1c42020-10-30 21:38:53 -060015#include <asm/global_data.h>
Tom Warren3f82b1d2011-01-27 10:58:05 +000016#include <asm/io.h>
Thierry Redingb64e0b92019-04-15 11:32:18 +020017#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
Simon Glassbb6997f2011-11-28 15:04:39 +000018#include <asm/arch/clock.h>
Thierry Redingb64e0b92019-04-15 11:32:18 +020019#endif
Thierry Reding07ea02b2019-04-15 11:32:21 +020020#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
Simon Glassbb6997f2011-11-28 15:04:39 +000021#include <asm/arch/funcmux.h>
Thierry Reding07ea02b2019-04-15 11:32:21 +020022#endif
Thierry Reding1a869c72019-04-15 11:32:20 +020023#if IS_ENABLED(CONFIG_TEGRA_MC)
Marcel Ziswiler8c33ba72014-10-10 23:32:32 +020024#include <asm/arch/mc.h>
Thierry Reding1a869c72019-04-15 11:32:20 +020025#endif
Tom Warren150c2492012-09-19 15:50:56 -070026#include <asm/arch/tegra.h>
Stephen Warren73c38932015-01-19 16:25:52 -070027#include <asm/arch-tegra/ap.h>
Lucas Stach516f00b2012-09-29 10:02:08 +000028#include <asm/arch-tegra/board.h>
Thierry Redinga0dbc132019-04-15 11:32:28 +020029#include <asm/arch-tegra/cboot.h>
Tom Warren150c2492012-09-19 15:50:56 -070030#include <asm/arch-tegra/pmc.h>
31#include <asm/arch-tegra/sys_proto.h>
32#include <asm/arch-tegra/warmboot.h>
Tom Warren3f82b1d2011-01-27 10:58:05 +000033
Tom Warren659a0752015-07-08 08:05:35 -070034void save_boot_params_ret(void);
35
Tom Warren3f82b1d2011-01-27 10:58:05 +000036DECLARE_GLOBAL_DATA_PTR;
37
Simon Glassbb6997f2011-11-28 15:04:39 +000038enum {
39 /* UARTs which we can enable */
40 UARTA = 1 << 0,
41 UARTB = 1 << 1,
Tom Warrene23bb6a2013-01-28 13:32:10 +000042 UARTC = 1 << 2,
Simon Glassbb6997f2011-11-28 15:04:39 +000043 UARTD = 1 << 3,
Tom Warrene23bb6a2013-01-28 13:32:10 +000044 UARTE = 1 << 4,
45 UART_COUNT = 5,
Simon Glassbb6997f2011-11-28 15:04:39 +000046};
47
Simon Glass537e9672015-05-13 07:02:29 -060048static bool from_spl __attribute__ ((section(".data")));
49
50#ifndef CONFIG_SPL_BUILD
Thierry Reding8f60d182019-04-15 11:32:23 +020051void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
52 unsigned long r3)
Simon Glass537e9672015-05-13 07:02:29 -060053{
54 from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
Thierry Redinga0dbc132019-04-15 11:32:28 +020055
56 /*
57 * The logic for this is somewhat indirect. The purpose of the marker
58 * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot
59 * was loaded from a read-only instance of itself, which is something
60 * that can happen in secure boot setups. So basically the presence
61 * of the marker is an indication that U-Boot was loaded by one such
62 * special variant of U-Boot. Conversely, the absence of the marker
63 * indicates that this instance of U-Boot was loaded by something
64 * other than a special U-Boot. This could be SPL, but it could just
65 * as well be one of any number of other first stage bootloaders.
66 */
67 if (from_spl)
68 cboot_save_boot_params(r0, r1, r2, r3);
69
Simon Glass537e9672015-05-13 07:02:29 -060070 save_boot_params_ret();
71}
72#endif
73
74bool spl_was_boot_source(void)
75{
76 return from_spl;
77}
78
Stephen Warren73c38932015-01-19 16:25:52 -070079#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
80#if !defined(CONFIG_TEGRA124)
81#error tegra_cpu_is_non_secure has only been validated on Tegra124
82#endif
83bool tegra_cpu_is_non_secure(void)
84{
85 /*
86 * This register reads 0xffffffff in non-secure mode. This register
87 * only implements bits 31:20, so the lower bits will always read 0 in
88 * secure mode. Thus, the lower bits are an indicator for secure vs.
89 * non-secure mode.
90 */
91 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
92 uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
93 return (mc_s_cfg0 & 1) == 1;
94}
95#endif
96
Thierry Reding1a869c72019-04-15 11:32:20 +020097#if IS_ENABLED(CONFIG_TEGRA_MC)
Stephen Warrenaeb3fcb2014-07-02 14:12:30 -060098/* Read the RAM size directly from the memory controller */
Stephen Warrena5fc3d02015-08-07 16:12:44 -060099static phys_size_t query_sdram_size(void)
Stephen Warrenaeb3fcb2014-07-02 14:12:30 -0600100{
101 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
Stephen Warrena5fc3d02015-08-07 16:12:44 -0600102 u32 emem_cfg;
103 phys_size_t size_bytes;
Stephen Warrenaeb3fcb2014-07-02 14:12:30 -0600104
Stephen Warren3a2cab52014-12-23 10:34:50 -0700105 emem_cfg = readl(&mc->mc_emem_cfg);
Marcel Ziswiler8c33ba72014-10-10 23:32:32 +0200106#if defined(CONFIG_TEGRA20)
Stephen Warren3a2cab52014-12-23 10:34:50 -0700107 debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
108 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
Marcel Ziswiler8c33ba72014-10-10 23:32:32 +0200109#else
Stephen Warren3a2cab52014-12-23 10:34:50 -0700110 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
Stephen Warrena5fc3d02015-08-07 16:12:44 -0600111#ifndef CONFIG_PHYS_64BIT
Stephen Warren56519c42014-12-23 10:34:51 -0700112 /*
113 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
114 * and will wrap. Clip the reported size to the maximum that a 32-bit
115 * variable can represent (rounded to a page).
116 */
117 if (emem_cfg >= 4096) {
118 size_bytes = U32_MAX & ~(0x1000 - 1);
Stephen Warrena5fc3d02015-08-07 16:12:44 -0600119 } else
120#endif
121 {
Stephen Warren56519c42014-12-23 10:34:51 -0700122 /* RAM size EMC is programmed to. */
Stephen Warrena5fc3d02015-08-07 16:12:44 -0600123 size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
124#ifndef CONFIG_ARM64
Stephen Warren56519c42014-12-23 10:34:51 -0700125 /*
126 * If all RAM fits within 32-bits, it can be accessed without
127 * LPAE, so go test the RAM size. Otherwise, we can't access
128 * all the RAM, and get_ram_size() would get confused, so
129 * avoid using it. There's no reason we should need this
130 * validation step anyway.
131 */
132 if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
133 size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
134 size_bytes);
Stephen Warrena5fc3d02015-08-07 16:12:44 -0600135#endif
Stephen Warren56519c42014-12-23 10:34:51 -0700136 }
Stephen Warrenaeb3fcb2014-07-02 14:12:30 -0600137#endif
Tom Warren3f82b1d2011-01-27 10:58:05 +0000138
Marcel Ziswiler8c33ba72014-10-10 23:32:32 +0200139#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
140 /* External memory limited to 2047 MB due to IROM/HI-VEC */
Stephen Warren3a2cab52014-12-23 10:34:50 -0700141 if (size_bytes == SZ_2G)
142 size_bytes -= SZ_1M;
Marcel Ziswiler8c33ba72014-10-10 23:32:32 +0200143#endif
144
Stephen Warren3a2cab52014-12-23 10:34:50 -0700145 return size_bytes;
Marcel Ziswiler8c33ba72014-10-10 23:32:32 +0200146}
Thierry Reding1a869c72019-04-15 11:32:20 +0200147#endif
Marcel Ziswiler8c33ba72014-10-10 23:32:32 +0200148
Tom Warren3f82b1d2011-01-27 10:58:05 +0000149int dram_init(void)
150{
Thierry Redinga0dbc132019-04-15 11:32:28 +0200151 int err;
152
153 /* try to initialize DRAM from cboot DTB first */
154 err = cboot_dram_init();
155 if (err == 0)
156 return 0;
157
Thierry Reding1a869c72019-04-15 11:32:20 +0200158#if IS_ENABLED(CONFIG_TEGRA_MC)
Tom Warren3f82b1d2011-01-27 10:58:05 +0000159 /* We do not initialise DRAM here. We just query the size */
Simon Glass7f8c0702011-11-05 03:56:57 +0000160 gd->ram_size = query_sdram_size();
Thierry Reding1a869c72019-04-15 11:32:20 +0200161#endif
162
Tom Warren3f82b1d2011-01-27 10:58:05 +0000163 return 0;
164}
165
Thierry Reding07ea02b2019-04-15 11:32:21 +0200166#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
Stephen Warrenb9607e72012-05-14 13:13:45 +0000167static int uart_configs[] = {
Tom Warrenb2871032012-12-11 13:34:15 +0000168#if defined(CONFIG_TEGRA20)
169 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
Stephen Warrenb9607e72012-05-14 13:13:45 +0000170 FUNCMUX_UART1_UAA_UAB,
Tom Warrenb2871032012-12-11 13:34:15 +0000171 #elif defined(CONFIG_TEGRA_UARTA_GPU)
Stephen Warrene21649b2012-05-16 05:59:59 +0000172 FUNCMUX_UART1_GPU,
Tom Warrenb2871032012-12-11 13:34:15 +0000173 #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
Lucas Stacha2cfe632012-05-16 08:21:02 +0000174 FUNCMUX_UART1_SDIO1,
Tom Warrenb2871032012-12-11 13:34:15 +0000175 #else
Stephen Warrenb9607e72012-05-14 13:13:45 +0000176 FUNCMUX_UART1_IRRX_IRTX,
Stephen Warren4727a132013-01-22 06:20:08 +0000177#endif
178 FUNCMUX_UART2_UAD,
Stephen Warrenb9607e72012-05-14 13:13:45 +0000179 -1,
180 FUNCMUX_UART4_GMC,
181 -1,
Tom Warrene23bb6a2013-01-28 13:32:10 +0000182#elif defined(CONFIG_TEGRA30)
Tom Warrenb2871032012-12-11 13:34:15 +0000183 FUNCMUX_UART1_ULPI, /* UARTA */
184 -1,
185 -1,
186 -1,
187 -1,
Tom Warren2f5dac92014-01-24 12:46:16 -0700188#elif defined(CONFIG_TEGRA114)
Tom Warrene23bb6a2013-01-28 13:32:10 +0000189 -1,
190 -1,
191 -1,
192 FUNCMUX_UART4_GMI, /* UARTD */
193 -1,
Tom Warren7aaa5a62015-03-04 16:36:00 -0700194#elif defined(CONFIG_TEGRA124)
Tom Warren2f5dac92014-01-24 12:46:16 -0700195 FUNCMUX_UART1_KBC, /* UARTA */
196 -1,
197 -1,
198 FUNCMUX_UART4_GPIO, /* UARTD */
199 -1,
Tom Warren7aaa5a62015-03-04 16:36:00 -0700200#else /* Tegra210 */
201 FUNCMUX_UART1_UART1, /* UARTA */
202 -1,
203 -1,
204 FUNCMUX_UART4_UART4, /* UARTD */
205 -1,
Tom Warrenb2871032012-12-11 13:34:15 +0000206#endif
Stephen Warrenb9607e72012-05-14 13:13:45 +0000207};
208
Simon Glassbb6997f2011-11-28 15:04:39 +0000209/**
210 * Set up the specified uarts
211 *
212 * @param uarts_ids Mask containing UARTs to init (UARTx)
213 */
214static void setup_uarts(int uart_ids)
215{
216 static enum periph_id id_for_uart[] = {
217 PERIPH_ID_UART1,
218 PERIPH_ID_UART2,
219 PERIPH_ID_UART3,
220 PERIPH_ID_UART4,
Tom Warrene23bb6a2013-01-28 13:32:10 +0000221 PERIPH_ID_UART5,
Simon Glassbb6997f2011-11-28 15:04:39 +0000222 };
223 size_t i;
224
225 for (i = 0; i < UART_COUNT; i++) {
226 if (uart_ids & (1 << i)) {
227 enum periph_id id = id_for_uart[i];
228
Stephen Warrenb9607e72012-05-14 13:13:45 +0000229 funcmux_select(id, uart_configs[i]);
Simon Glassbb6997f2011-11-28 15:04:39 +0000230 clock_ll_start_uart(id);
231 }
232 }
233}
Thierry Reding07ea02b2019-04-15 11:32:21 +0200234#endif
Simon Glassbb6997f2011-11-28 15:04:39 +0000235
236void board_init_uart_f(void)
237{
Thierry Reding07ea02b2019-04-15 11:32:21 +0200238#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
Simon Glassbb6997f2011-11-28 15:04:39 +0000239 int uart_ids = 0; /* bit mask of which UART ids to enable */
240
Tom Warren29f3e3f2012-09-04 17:00:24 -0700241#ifdef CONFIG_TEGRA_ENABLE_UARTA
Simon Glassbb6997f2011-11-28 15:04:39 +0000242 uart_ids |= UARTA;
243#endif
Tom Warren29f3e3f2012-09-04 17:00:24 -0700244#ifdef CONFIG_TEGRA_ENABLE_UARTB
Simon Glassbb6997f2011-11-28 15:04:39 +0000245 uart_ids |= UARTB;
246#endif
Tom Warrene23bb6a2013-01-28 13:32:10 +0000247#ifdef CONFIG_TEGRA_ENABLE_UARTC
248 uart_ids |= UARTC;
249#endif
Tom Warren29f3e3f2012-09-04 17:00:24 -0700250#ifdef CONFIG_TEGRA_ENABLE_UARTD
Simon Glassbb6997f2011-11-28 15:04:39 +0000251 uart_ids |= UARTD;
252#endif
Tom Warrene23bb6a2013-01-28 13:32:10 +0000253#ifdef CONFIG_TEGRA_ENABLE_UARTE
254 uart_ids |= UARTE;
255#endif
Simon Glassbb6997f2011-11-28 15:04:39 +0000256 setup_uarts(uart_ids);
Thierry Reding07ea02b2019-04-15 11:32:21 +0200257#endif
Simon Glassbb6997f2011-11-28 15:04:39 +0000258}
Simon Glassbd29cb02012-01-09 13:22:15 +0000259
Simon Glass878a3ed2015-12-04 08:58:39 -0700260#if !CONFIG_IS_ENABLED(OF_CONTROL)
Simon Glass8a8d24b2020-12-03 16:55:23 -0700261static struct ns16550_plat ns16550_com1_pdata = {
Thomas Chou18746262015-11-19 21:48:11 +0800262 .base = CONFIG_SYS_NS16550_COM1,
263 .reg_shift = 2,
264 .clock = CONFIG_SYS_NS16550_CLK,
Heiko Schocher17fa0322017-01-18 08:05:49 +0100265 .fcr = UART_FCR_DEFVAL,
Thomas Chou18746262015-11-19 21:48:11 +0800266};
267
Simon Glass20e442a2020-12-28 20:34:54 -0700268U_BOOT_DRVINFO(ns16550_com1) = {
Thomas Chou18746262015-11-19 21:48:11 +0800269 "ns16550_serial", &ns16550_com1_pdata
270};
271#endif
272
Trevor Woerner10015022019-05-03 09:41:00 -0400273#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
Simon Glassbd29cb02012-01-09 13:22:15 +0000274void enable_caches(void)
275{
276 /* Enable D-cache. I-cache is already enabled in start.S */
277 dcache_enable();
278}
279#endif