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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glasse761ecd2013-04-17 16:13:36 +00002/*
3 * Copyright (c) 2012 The Chromium OS Authors.
4 *
Bin Meng076bb442014-11-09 22:19:13 +08005 * TSC calibration codes are adapted from Linux kernel
6 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
Simon Glasse761ecd2013-04-17 16:13:36 +00007 */
8
9#include <common.h>
Simon Glass52f24232020-05-10 11:40:00 -060010#include <bootstage.h>
Bin Meng4e51fc22015-11-13 00:11:21 -080011#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
Simon Glasse761ecd2013-04-17 16:13:36 +000013#include <malloc.h>
Simon Glass10453152019-11-14 12:57:30 -070014#include <time.h>
Bin Meng4e51fc22015-11-13 00:11:21 -080015#include <timer.h>
Bin Meng0b992e42017-07-25 20:12:01 -070016#include <asm/cpu.h>
Simon Glass401d1c42020-10-30 21:38:53 -060017#include <asm/global_data.h>
Simon Glasse761ecd2013-04-17 16:13:36 +000018#include <asm/io.h>
19#include <asm/i8254.h>
20#include <asm/ibmpc.h>
21#include <asm/msr.h>
22#include <asm/u-boot-x86.h>
Simon Glassc05ed002020-05-10 11:40:11 -060023#include <linux/delay.h>
Simon Glasse761ecd2013-04-17 16:13:36 +000024
Bin Meng3df39ef2017-08-15 22:41:50 -070025#define MAX_NUM_FREQS 9
Bin Meng076bb442014-11-09 22:19:13 +080026
Bernhard Messerklingerca7db862019-01-07 12:14:40 +010027#define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
28#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
29#define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
30#define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
31#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
32#define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
33
Simon Glasse761ecd2013-04-17 16:13:36 +000034DECLARE_GLOBAL_DATA_PTR;
35
Bernhard Messerklingerca7db862019-01-07 12:14:40 +010036/*
37 * native_calibrate_tsc
38 * Determine TSC frequency via CPUID, else return 0.
39 */
40static unsigned long native_calibrate_tsc(void)
41{
42 struct cpuid_result tsc_info;
43 unsigned int crystal_freq;
44
45 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
46 return 0;
47
48 if (cpuid_eax(0) < 0x15)
49 return 0;
50
51 tsc_info = cpuid(0x15);
52
53 if (tsc_info.ebx == 0 || tsc_info.eax == 0)
54 return 0;
55
56 crystal_freq = tsc_info.ecx / 1000;
Simon Glass642e8482019-12-06 21:41:50 -070057 if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) {
Bernhard Messerklingerca7db862019-01-07 12:14:40 +010058 switch (gd->arch.x86_model) {
59 case INTEL_FAM6_SKYLAKE_MOBILE:
60 case INTEL_FAM6_SKYLAKE_DESKTOP:
61 case INTEL_FAM6_KABYLAKE_MOBILE:
62 case INTEL_FAM6_KABYLAKE_DESKTOP:
63 crystal_freq = 24000; /* 24.0 MHz */
64 break;
65 case INTEL_FAM6_ATOM_GOLDMONT_X:
66 crystal_freq = 25000; /* 25.0 MHz */
67 break;
68 case INTEL_FAM6_ATOM_GOLDMONT:
69 crystal_freq = 19200; /* 19.2 MHz */
70 break;
71 default:
72 return 0;
73 }
74 }
75
76 return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
77}
78
Christian Gmeineracc24822018-05-14 11:32:17 +020079static unsigned long cpu_mhz_from_cpuid(void)
80{
81 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
82 return 0;
83
84 if (cpuid_eax(0) < 0x16)
85 return 0;
86
87 return cpuid_eax(0x16);
88}
89
Bin Meng076bb442014-11-09 22:19:13 +080090/*
91 * According to Intel 64 and IA-32 System Programming Guide,
92 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
93 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
94 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
95 * so we need manually differentiate SoC families. This is what the
96 * field msr_plat does.
97 */
98struct freq_desc {
99 u8 x86_family; /* CPU family */
100 u8 x86_model; /* model */
Simon Glass5c1b6852014-11-12 22:42:04 -0700101 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
102 u8 msr_plat;
Bin Meng076bb442014-11-09 22:19:13 +0800103 u32 freqs[MAX_NUM_FREQS];
104};
105
106static struct freq_desc freq_desc_tables[] = {
107 /* PNW */
Bin Meng3df39ef2017-08-15 22:41:50 -0700108 { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
Bin Meng076bb442014-11-09 22:19:13 +0800109 /* CLV+ */
Bin Meng3df39ef2017-08-15 22:41:50 -0700110 { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
Bin Mengc6367742017-07-25 20:12:03 -0700111 /* TNG - Intel Atom processor Z3400 series */
Bin Meng3df39ef2017-08-15 22:41:50 -0700112 { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
Bin Mengc6367742017-07-25 20:12:03 -0700113 /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
Bin Meng3df39ef2017-08-15 22:41:50 -0700114 { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
Bin Mengc6367742017-07-25 20:12:03 -0700115 /* ANN - Intel Atom processor Z3500 series */
Bin Meng3df39ef2017-08-15 22:41:50 -0700116 { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
117 /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
118 { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
119 80000, 93300, 90000, 88900, 87500 } },
Simon Glass5c1b6852014-11-12 22:42:04 -0700120 /* Ivybridge */
Bin Meng3df39ef2017-08-15 22:41:50 -0700121 { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
Bin Meng076bb442014-11-09 22:19:13 +0800122};
123
124static int match_cpu(u8 family, u8 model)
125{
126 int i;
127
128 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
129 if ((family == freq_desc_tables[i].x86_family) &&
130 (model == freq_desc_tables[i].x86_model))
131 return i;
132 }
133
134 return -1;
135}
136
137/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
138#define id_to_freq(cpu_index, freq_id) \
139 (freq_desc_tables[cpu_index].freqs[freq_id])
140
141/*
Bin Meng167a4012017-07-25 20:12:05 -0700142 * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
143 * reliable and the frequency is known (provided by HW).
Bin Meng076bb442014-11-09 22:19:13 +0800144 *
Bin Meng167a4012017-07-25 20:12:05 -0700145 * On these platforms PIT/HPET is generally not available so calibration won't
146 * work at all and there is no other clocksource to act as a watchdog for the
147 * TSC, so we have no other choice than to trust it.
148 *
149 * Returns the TSC frequency in MHz or 0 if HW does not provide it.
Bin Meng076bb442014-11-09 22:19:13 +0800150 */
Bin Meng167a4012017-07-25 20:12:05 -0700151static unsigned long __maybe_unused cpu_mhz_from_msr(void)
Bin Meng076bb442014-11-09 22:19:13 +0800152{
153 u32 lo, hi, ratio, freq_id, freq;
154 unsigned long res;
155 int cpu_index;
156
Bin Meng0b992e42017-07-25 20:12:01 -0700157 if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
158 return 0;
159
Bin Meng076bb442014-11-09 22:19:13 +0800160 cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
161 if (cpu_index < 0)
162 return 0;
163
164 if (freq_desc_tables[cpu_index].msr_plat) {
165 rdmsr(MSR_PLATFORM_INFO, lo, hi);
Bin Mengd92e9c82017-07-25 20:12:00 -0700166 ratio = (lo >> 8) & 0xff;
Bin Meng076bb442014-11-09 22:19:13 +0800167 } else {
168 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
169 ratio = (hi >> 8) & 0x1f;
170 }
171 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
172
Simon Glass5c1b6852014-11-12 22:42:04 -0700173 if (freq_desc_tables[cpu_index].msr_plat == 2) {
174 /* TODO: Figure out how best to deal with this */
Bin Mengf5757152017-07-25 20:12:04 -0700175 freq = 100000;
Simon Glass5c1b6852014-11-12 22:42:04 -0700176 debug("Using frequency: %u KHz\n", freq);
177 } else {
178 /* Get FSB FREQ ID */
179 rdmsr(MSR_FSB_FREQ, lo, hi);
180 freq_id = lo & 0x7;
181 freq = id_to_freq(cpu_index, freq_id);
182 debug("Resolved frequency ID: %u, frequency: %u KHz\n",
183 freq_id, freq);
184 }
Bin Meng076bb442014-11-09 22:19:13 +0800185
186 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
187 res = freq * ratio / 1000;
188 debug("TSC runs at %lu MHz\n", res);
189
190 return res;
Bin Meng076bb442014-11-09 22:19:13 +0800191}
192
Bin Meng80de0492014-11-09 22:19:25 +0800193/*
194 * This reads the current MSB of the PIT counter, and
195 * checks if we are running on sufficiently fast and
196 * non-virtualized hardware.
197 *
198 * Our expectations are:
199 *
200 * - the PIT is running at roughly 1.19MHz
201 *
202 * - each IO is going to take about 1us on real hardware,
203 * but we allow it to be much faster (by a factor of 10) or
204 * _slightly_ slower (ie we allow up to a 2us read+counter
205 * update - anything else implies a unacceptably slow CPU
206 * or PIT for the fast calibration to work.
207 *
208 * - with 256 PIT ticks to read the value, we have 214us to
209 * see the same MSB (and overhead like doing a single TSC
210 * read per MSB value etc).
211 *
212 * - We're doing 2 reads per loop (LSB, MSB), and we expect
213 * them each to take about a microsecond on real hardware.
214 * So we expect a count value of around 100. But we'll be
215 * generous, and accept anything over 50.
216 *
217 * - if the PIT is stuck, and we see *many* more reads, we
218 * return early (and the next caller of pit_expect_msb()
219 * then consider it a failure when they don't see the
220 * next expected value).
221 *
222 * These expectations mean that we know that we have seen the
223 * transition from one expected value to another with a fairly
224 * high accuracy, and we didn't miss any events. We can thus
225 * use the TSC value at the transitions to calculate a pretty
226 * good value for the TSC frequencty.
227 */
228static inline int pit_verify_msb(unsigned char val)
229{
230 /* Ignore LSB */
231 inb(0x42);
232 return inb(0x42) == val;
233}
234
235static inline int pit_expect_msb(unsigned char val, u64 *tscp,
236 unsigned long *deltap)
237{
238 int count;
239 u64 tsc = 0, prev_tsc = 0;
240
241 for (count = 0; count < 50000; count++) {
242 if (!pit_verify_msb(val))
243 break;
244 prev_tsc = tsc;
245 tsc = rdtsc();
246 }
247 *deltap = rdtsc() - prev_tsc;
248 *tscp = tsc;
249
250 /*
251 * We require _some_ success, but the quality control
252 * will be based on the error terms on the TSC values.
253 */
254 return count > 5;
255}
256
257/*
258 * How many MSB values do we want to see? We aim for
259 * a maximum error rate of 500ppm (in practice the
260 * real error is much smaller), but refuse to spend
261 * more than 50ms on it.
262 */
263#define MAX_QUICK_PIT_MS 50
264#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
265
Bin Meng3ba6a0f2015-01-06 22:14:14 +0800266static unsigned long __maybe_unused quick_pit_calibrate(void)
Bin Meng80de0492014-11-09 22:19:25 +0800267{
268 int i;
269 u64 tsc, delta;
270 unsigned long d1, d2;
271
272 /* Set the Gate high, disable speaker */
273 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
274
275 /*
276 * Counter 2, mode 0 (one-shot), binary count
277 *
278 * NOTE! Mode 2 decrements by two (and then the
279 * output is flipped each time, giving the same
280 * final output frequency as a decrement-by-one),
281 * so mode 0 is much better when looking at the
282 * individual counts.
283 */
284 outb(0xb0, 0x43);
285
286 /* Start at 0xffff */
287 outb(0xff, 0x42);
288 outb(0xff, 0x42);
289
290 /*
291 * The PIT starts counting at the next edge, so we
292 * need to delay for a microsecond. The easiest way
293 * to do that is to just read back the 16-bit counter
294 * once from the PIT.
295 */
296 pit_verify_msb(0);
297
298 if (pit_expect_msb(0xff, &tsc, &d1)) {
299 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
300 if (!pit_expect_msb(0xff-i, &delta, &d2))
301 break;
302
303 /*
304 * Iterate until the error is less than 500 ppm
305 */
306 delta -= tsc;
307 if (d1+d2 >= delta >> 11)
308 continue;
309
310 /*
311 * Check the PIT one more time to verify that
312 * all TSC reads were stable wrt the PIT.
313 *
314 * This also guarantees serialization of the
315 * last cycle read ('d2') in pit_expect_msb.
316 */
317 if (!pit_verify_msb(0xfe - i))
318 break;
319 goto success;
320 }
321 }
322 debug("Fast TSC calibration failed\n");
323 return 0;
324
325success:
326 /*
327 * Ok, if we get here, then we've seen the
328 * MSB of the PIT decrement 'i' times, and the
329 * error has shrunk to less than 500 ppm.
330 *
331 * As a result, we can depend on there not being
332 * any odd delays anywhere, and the TSC reads are
333 * reliable (within the error).
334 *
335 * kHz = ticks / time-in-seconds / 1000;
336 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
337 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
338 */
339 delta *= PIT_TICK_RATE;
340 delta /= (i*256*1000);
341 debug("Fast TSC calibration using PIT\n");
342 return delta / 1000;
343}
344
Simon Glasse761ecd2013-04-17 16:13:36 +0000345/* Get the speed of the TSC timer in MHz */
Bin Meng2f80fc52015-11-13 00:11:20 -0800346unsigned notrace long get_tbclk_mhz(void)
Simon Glasse761ecd2013-04-17 16:13:36 +0000347{
Bin Meng4e51fc22015-11-13 00:11:21 -0800348 return get_tbclk() / 1000000;
Simon Glasse761ecd2013-04-17 16:13:36 +0000349}
350
Simon Glasse761ecd2013-04-17 16:13:36 +0000351static ulong get_ms_timer(void)
352{
353 return (get_ticks() * 1000) / get_tbclk();
354}
355
356ulong get_timer(ulong base)
357{
358 return get_ms_timer() - base;
359}
360
Bin Meng2f80fc52015-11-13 00:11:20 -0800361ulong notrace timer_get_us(void)
Simon Glasse761ecd2013-04-17 16:13:36 +0000362{
363 return get_ticks() / get_tbclk_mhz();
364}
365
366ulong timer_get_boot_us(void)
367{
368 return timer_get_us();
369}
370
371void __udelay(unsigned long usec)
372{
373 u64 now = get_ticks();
374 u64 stop;
375
Simon Glass9edf20f2021-01-13 20:29:45 -0700376 stop = now + (u64)usec * get_tbclk_mhz();
Simon Glasse761ecd2013-04-17 16:13:36 +0000377
378 while ((int64_t)(stop - get_ticks()) > 0)
Miao Yan417576c2015-07-27 19:16:07 +0800379#if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
380 /*
381 * Add a 'pause' instruction on qemu target,
382 * to give other VCPUs a chance to run.
383 */
384 asm volatile("pause");
385#else
Simon Glasse761ecd2013-04-17 16:13:36 +0000386 ;
Miao Yan417576c2015-07-27 19:16:07 +0800387#endif
Simon Glasse761ecd2013-04-17 16:13:36 +0000388}
389
Sean Anderson8af7bb92020-10-07 14:37:44 -0400390static u64 tsc_timer_get_count(struct udevice *dev)
Bin Meng4e51fc22015-11-13 00:11:21 -0800391{
392 u64 now_tick = rdtsc();
393
Sean Anderson8af7bb92020-10-07 14:37:44 -0400394 return now_tick - gd->arch.tsc_base;
Bin Meng4e51fc22015-11-13 00:11:21 -0800395}
396
Bin Meng6ce38362018-10-13 20:52:10 -0700397static void tsc_timer_ensure_setup(bool early)
Bin Meng4e51fc22015-11-13 00:11:21 -0800398{
Simon Glassa478a262019-10-20 21:37:47 -0600399 if (gd->arch.tsc_inited)
Simon Glass2ff50f52017-09-05 19:49:46 -0600400 return;
Simon Glass77dd7c62019-12-06 21:41:49 -0700401 if (IS_ENABLED(CONFIG_X86_TSC_READ_BASE))
402 gd->arch.tsc_base = rdtsc();
Bin Meng4e51fc22015-11-13 00:11:21 -0800403
Simon Glass2ff50f52017-09-05 19:49:46 -0600404 if (!gd->arch.clock_rate) {
Bin Meng4e51fc22015-11-13 00:11:21 -0800405 unsigned long fast_calibrate;
406
Bernhard Messerklingerca7db862019-01-07 12:14:40 +0100407 fast_calibrate = native_calibrate_tsc();
408 if (fast_calibrate)
409 goto done;
410
Simon Glass642e8482019-12-06 21:41:50 -0700411 /* Reduce code size by dropping other methods */
412 if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE))
413 panic("no timer");
414
Christian Gmeineracc24822018-05-14 11:32:17 +0200415 fast_calibrate = cpu_mhz_from_cpuid();
416 if (fast_calibrate)
417 goto done;
Bin Meng4e51fc22015-11-13 00:11:21 -0800418
Christian Gmeineracc24822018-05-14 11:32:17 +0200419 fast_calibrate = cpu_mhz_from_msr();
420 if (fast_calibrate)
421 goto done;
422
423 fast_calibrate = quick_pit_calibrate();
424 if (fast_calibrate)
425 goto done;
426
Bin Meng6ce38362018-10-13 20:52:10 -0700427 if (early)
428 fast_calibrate = CONFIG_X86_TSC_TIMER_EARLY_FREQ;
Bin Meng165db7c2018-08-10 02:39:36 -0700429 else
430 return;
Christian Gmeineracc24822018-05-14 11:32:17 +0200431
432done:
Simon Glass2ff50f52017-09-05 19:49:46 -0600433 gd->arch.clock_rate = fast_calibrate * 1000000;
Bin Meng4e51fc22015-11-13 00:11:21 -0800434 }
Simon Glassa478a262019-10-20 21:37:47 -0600435 gd->arch.tsc_inited = true;
Simon Glass2ff50f52017-09-05 19:49:46 -0600436}
437
438static int tsc_timer_probe(struct udevice *dev)
439{
440 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
441
Bin Meng165db7c2018-08-10 02:39:36 -0700442 /* Try hardware calibration first */
443 tsc_timer_ensure_setup(false);
444 if (!gd->arch.clock_rate) {
445 /*
446 * Use the clock frequency specified in the
447 * device tree as last resort
448 */
449 if (!uc_priv->clock_rate)
450 panic("TSC frequency is ZERO");
Bin Meng94e72a62018-06-23 03:03:47 -0700451 } else {
Bin Meng165db7c2018-08-10 02:39:36 -0700452 uc_priv->clock_rate = gd->arch.clock_rate;
Bin Meng94e72a62018-06-23 03:03:47 -0700453 }
Bin Meng4e51fc22015-11-13 00:11:21 -0800454
455 return 0;
456}
457
Simon Glass2ff50f52017-09-05 19:49:46 -0600458unsigned long notrace timer_early_get_rate(void)
459{
Bin Meng94e72a62018-06-23 03:03:47 -0700460 /*
461 * When TSC timer is used as the early timer, be warned that the timer
462 * clock rate can only be calibrated via some hardware ways. Specifying
463 * it in the device tree won't work for the early timer.
464 */
Bin Meng165db7c2018-08-10 02:39:36 -0700465 tsc_timer_ensure_setup(true);
Simon Glass2ff50f52017-09-05 19:49:46 -0600466
467 return gd->arch.clock_rate;
468}
469
470u64 notrace timer_early_get_count(void)
471{
Simon Glass096c71e2019-10-20 21:31:54 -0600472 tsc_timer_ensure_setup(true);
473
Simon Glass2ff50f52017-09-05 19:49:46 -0600474 return rdtsc() - gd->arch.tsc_base;
475}
476
Bin Meng4e51fc22015-11-13 00:11:21 -0800477static const struct timer_ops tsc_timer_ops = {
478 .get_count = tsc_timer_get_count,
479};
480
Simon Glass8b842be2020-12-23 08:11:30 -0700481#if !CONFIG_IS_ENABLED(OF_PLATDATA)
Bin Meng4e51fc22015-11-13 00:11:21 -0800482static const struct udevice_id tsc_timer_ids[] = {
483 { .compatible = "x86,tsc-timer", },
484 { }
485};
Simon Glass8b842be2020-12-23 08:11:30 -0700486#endif
Bin Meng4e51fc22015-11-13 00:11:21 -0800487
Simon Glass9d20db02020-10-05 05:27:01 -0600488U_BOOT_DRIVER(x86_tsc_timer) = {
489 .name = "x86_tsc_timer",
Bin Meng4e51fc22015-11-13 00:11:21 -0800490 .id = UCLASS_TIMER,
Simon Glass8b842be2020-12-23 08:11:30 -0700491 .of_match = of_match_ptr(tsc_timer_ids),
Bin Meng4e51fc22015-11-13 00:11:21 -0800492 .probe = tsc_timer_probe,
493 .ops = &tsc_timer_ops,
Bin Meng4e51fc22015-11-13 00:11:21 -0800494};