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Jon Loeligerdebb7352006-04-26 17:58:56 -05001/*
Kumar Gala561e7102011-01-31 15:51:20 -06002 * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor.
Jon Loeligerdebb7352006-04-26 17:58:56 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Jon Loeligerdebb7352006-04-26 17:58:56 -05005 */
6
7#include <common.h>
8#include <pci.h>
9#include <asm/processor.h>
10#include <asm/immap_86xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050011#include <asm/fsl_pci.h>
York Sun5614e712013-09-30 09:22:09 -070012#include <fsl_ddr_sdram.h>
Kumar Gala5d27e022010-12-15 04:55:20 -060013#include <asm/fsl_serdes.h>
Haiying Wang3d98b852007-01-22 12:37:30 -060014#include <asm/io.h>
Jon Loeligerea9f7392007-11-28 14:47:18 -060015#include <libfdt.h>
16#include <fdt_support.h>
Ben Warren0b252f52008-08-31 21:41:08 -070017#include <netdev.h>
Jon Loeligerdebb7352006-04-26 17:58:56 -050018
Becky Bruce4c77de32008-10-31 17:13:32 -050019phys_size_t fixed_sdram(void);
Jon Loeligerdebb7352006-04-26 17:58:56 -050020
Jon Loeliger80e955c2006-08-22 12:25:27 -050021int checkboard(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -050022{
Kumar Gala9af9c6b2009-07-15 13:45:00 -050023 u8 vboot;
24 u8 *pixis_base = (u8 *)PIXIS_BASE;
25
26 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
27 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
28 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
29 in_8(pixis_base + PIXIS_PVER));
30
31 vboot = in_8(pixis_base + PIXIS_VBOOT);
32 if (vboot & PIXIS_VBOOT_FMAP)
33 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
34 else
35 puts ("Promjet\n");
36
Jon Loeligerdebb7352006-04-26 17:58:56 -050037 return 0;
38}
39
Becky Bruce9973e3c2008-06-09 16:03:40 -050040phys_size_t
Jon Loeligerdebb7352006-04-26 17:58:56 -050041initdram(int board_type)
42{
Becky Bruce4c77de32008-10-31 17:13:32 -050043 phys_size_t dram_size = 0;
Jon Loeligerdebb7352006-04-26 17:58:56 -050044
45#if defined(CONFIG_SPD_EEPROM)
Kumar Gala6a8e5692008-08-26 15:01:35 -050046 dram_size = fsl_ddr_sdram();
Jon Loeligerdebb7352006-04-26 17:58:56 -050047#else
Jon Loeliger80e955c2006-08-22 12:25:27 -050048 dram_size = fixed_sdram();
Jon Loeligerdebb7352006-04-26 17:58:56 -050049#endif
50
Timur Tabi9ff32d82010-03-29 12:51:07 -050051 setup_ddr_bat(dram_size);
52
Wolfgang Denk21cd5812011-07-25 10:13:53 +020053 debug(" DDR: ");
Jon Loeligerdebb7352006-04-26 17:58:56 -050054 return dram_size;
55}
56
57
Jon Loeligerdebb7352006-04-26 17:58:56 -050058#if !defined(CONFIG_SPD_EEPROM)
Jon Loeliger5c9efb32006-04-27 10:15:16 -050059/*
60 * Fixed sdram init -- doesn't use serial presence detect.
61 */
Becky Bruce4c77de32008-10-31 17:13:32 -050062phys_size_t
Jon Loeliger80e955c2006-08-22 12:25:27 -050063fixed_sdram(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -050064{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#if !defined(CONFIG_SYS_RAMBOOT)
66 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
York Sun9a17eb52013-11-18 10:29:32 -080067 struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
Jon Loeligerdebb7352006-04-26 17:58:56 -050068
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
70 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
71 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
72 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
73 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
74 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
Peter Tysere7ee23e2009-07-17 10:14:45 -050075 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
77 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
78 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
79 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
80 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
81 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
Jon Loeligerdebb7352006-04-26 17:58:56 -050082
83#if defined (CONFIG_DDR_ECC)
84 ddr->err_disable = 0x0000008D;
85 ddr->err_sbe = 0x00ff0000;
86#endif
87 asm("sync;isync");
Jon Loeligercb5965f2006-05-31 12:44:44 -050088
Jon Loeligerdebb7352006-04-26 17:58:56 -050089 udelay(500);
90
91#if defined (CONFIG_DDR_ECC)
92 /* Enable ECC checking */
Peter Tysere7ee23e2009-07-17 10:14:45 -050093 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
Jon Loeligerdebb7352006-04-26 17:58:56 -050094#else
Peter Tysere7ee23e2009-07-17 10:14:45 -050095 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
Jon Loeligerdebb7352006-04-26 17:58:56 -050097#endif
98 asm("sync; isync");
Jon Loeligercb5965f2006-05-31 12:44:44 -050099
Jon Loeligerdebb7352006-04-26 17:58:56 -0500100 udelay(500);
101#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500103}
104#endif /* !defined(CONFIG_SPD_EEPROM) */
105
Jon Loeliger80e955c2006-08-22 12:25:27 -0500106void pci_init_board(void)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500107{
Kumar Gala64e55d52010-12-17 10:47:36 -0600108 fsl_pcie_init_board(0);
Peter Tyser9a268e42010-09-29 13:37:26 -0500109
Kumar Gala46f3e382010-07-09 00:02:34 -0500110#ifdef CONFIG_PCIE1
Ed Swarthout63cec582007-08-02 14:09:49 -0500111 /*
112 * Activate ULI1575 legacy chip by performing a fake
113 * memory access. Needed to make ULI RTC work.
114 */
Kumar Gala46f3e382010-07-09 00:02:34 -0500115 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
116 + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
Kumar Gala46f3e382010-07-09 00:02:34 -0500117#endif /* CONFIG_PCIE1 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500118}
119
Jon Loeliger13f54332008-02-18 14:01:56 -0600120
Jon Loeligerea9f7392007-11-28 14:47:18 -0600121#if defined(CONFIG_OF_BOARD_SETUP)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500122void
123ft_board_setup(void *blob, bd_t *bd)
124{
Becky Bruced52082b2008-11-07 13:46:19 -0600125 int off;
126 u64 *tmp;
127 u32 *addrcells;
128
Jon Loeliger13f54332008-02-18 14:01:56 -0600129 ft_cpu_setup(blob, bd);
Jon Loeligerea9f7392007-11-28 14:47:18 -0600130
Kumar Gala6525d512010-07-08 22:37:44 -0500131 FT_FSL_PCI_SETUP;
Becky Bruced52082b2008-11-07 13:46:19 -0600132
133 /*
134 * Warn if it looks like the device tree doesn't match u-boot.
135 * This is just an estimation, based on the location of CCSR,
136 * which is defined by the "reg" property in the soc node.
137 */
138 off = fdt_path_offset(blob, "/soc8641");
139 addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
140 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
141
142 if (tmp) {
143 u64 addr;
Becky Bruce3f510db2008-11-10 19:45:35 -0600144 if (addrcells && (*addrcells == 1))
Becky Bruced52082b2008-11-07 13:46:19 -0600145 addr = *(u32 *)tmp;
Becky Bruce3f510db2008-11-10 19:45:35 -0600146 else
147 addr = *tmp;
Becky Bruced52082b2008-11-07 13:46:19 -0600148
149 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
150 printf("WARNING: The CCSRBAR address in your .dts "
151 "does not match the address of the CCSR "
152 "in u-boot. This means your .dts might "
153 "be old.\n");
154 }
Jon Loeligerdebb7352006-04-26 17:58:56 -0500155}
156#endif
157
Jon Loeligerdebb7352006-04-26 17:58:56 -0500158
Haiying Wang239db372006-07-28 12:41:18 -0400159/*
160 * get_board_sys_clk
161 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
162 */
163
Jon Loeliger80e955c2006-08-22 12:25:27 -0500164unsigned long
165get_board_sys_clk(ulong dummy)
Haiying Wang239db372006-07-28 12:41:18 -0400166{
167 u8 i, go_bit, rd_clks;
168 ulong val = 0;
Kumar Gala048e7ef2009-07-22 10:12:39 -0500169 u8 *pixis_base = (u8 *)PIXIS_BASE;
Haiying Wang239db372006-07-28 12:41:18 -0400170
Kumar Gala048e7ef2009-07-22 10:12:39 -0500171 go_bit = in_8(pixis_base + PIXIS_VCTL);
Haiying Wang239db372006-07-28 12:41:18 -0400172 go_bit &= 0x01;
173
Kumar Gala048e7ef2009-07-22 10:12:39 -0500174 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
Haiying Wang239db372006-07-28 12:41:18 -0400175 rd_clks &= 0x1C;
176
177 /*
178 * Only if both go bit and the SCLK bit in VCFGEN0 are set
179 * should we be using the AUX register. Remember, we also set the
180 * GO bit to boot from the alternate bank on the on-board flash
181 */
182
183 if (go_bit) {
184 if (rd_clks == 0x1c)
Kumar Gala048e7ef2009-07-22 10:12:39 -0500185 i = in_8(pixis_base + PIXIS_AUX);
Haiying Wang239db372006-07-28 12:41:18 -0400186 else
Kumar Gala048e7ef2009-07-22 10:12:39 -0500187 i = in_8(pixis_base + PIXIS_SPD);
Haiying Wang239db372006-07-28 12:41:18 -0400188 } else {
Kumar Gala048e7ef2009-07-22 10:12:39 -0500189 i = in_8(pixis_base + PIXIS_SPD);
Haiying Wang239db372006-07-28 12:41:18 -0400190 }
191
192 i &= 0x07;
193
194 switch (i) {
195 case 0:
196 val = 33000000;
197 break;
198 case 1:
199 val = 40000000;
200 break;
201 case 2:
202 val = 50000000;
203 break;
204 case 3:
205 val = 66000000;
206 break;
207 case 4:
208 val = 83000000;
209 break;
210 case 5:
211 val = 100000000;
212 break;
213 case 6:
214 val = 134000000;
215 break;
216 case 7:
217 val = 166000000;
218 break;
219 }
220
221 return val;
222}
Ben Warren0b252f52008-08-31 21:41:08 -0700223
224int board_eth_init(bd_t *bis)
225{
226 /* Initialize TSECs */
227 cpu_eth_init(bis);
228 return pci_eth_init(bis);
229}
Peter Tyser4ef630d2009-02-05 11:25:25 -0600230
231void board_reset(void)
232{
Kumar Gala048e7ef2009-07-22 10:12:39 -0500233 u8 *pixis_base = (u8 *)PIXIS_BASE;
234
235 out_8(pixis_base + PIXIS_RST, 0);
Peter Tyser4ef630d2009-02-05 11:25:25 -0600236
237 while (1)
238 ;
239}