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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 42a13a0b9faf88da332675c997f06a063fc77133 / . / include / w83c553f.h
blob: 2403e3401a6fc3e27fac425907f4618d14ace372 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
wdenk012771d2002-03-08 21:31:05 +0000[diff] [blame]2/*
3 * (C) Copyright 2000
4 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
wdenk012771d2002-03-08 21:31:05 +0000[diff] [blame]5 */
6
7 /* winbond access routines and defines*/
8
9/* from the winbond data sheet -
10 The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
11 Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller.
12*/
13
14/*ISA bridge configuration space*/
15
16#define W83C553F_VID 0x10AD
17#define W83C553F_DID 0x0565
18
19#define WINBOND_PCICONTR 0x40 /*pci control reg*/
20#define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/
21#define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/
22#define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/
23#define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/
24#define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/
25#define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/
26#define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/
27#define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/
28#define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/
29#define WINBOND_CDR 0x4c /*Clock Divisor Register*/
30#define WINBOND_CSCR 0x4d /*Chip Select Control Register*/
31#define WINBOND_ATSCR 0x4e /*AT System Control register*/
32#define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/
33#define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/
34#define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/
35#define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/
36#define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/
37
38#define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/
39
40#define IPADCR_MBE512 0x1
41#define IPADCR_MBE640 0x2
42#define IPADCR_IPATOM4 0x10
43#define IPADCR_IPATOM5 0x20
44#define IPADCR_IPATOM6 0x40
45#define IPADCR_IPATOM7 0x80
46
47#define CSCR_UBIOSCSE 0x10
48#define CSCR_BIOSWP 0x20
49
50#define IDECSR_P0EN 0x01
51#define IDECSR_P0F16 0x02
52#define IDECSR_P1EN 0x10
53#define IDECSR_P1F16 0x20
54#define IDECSR_LEGIRQ 0x800
55
56/*
57 * Interrupt controller
58 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]59#define W83C553F_PIC1_ICW1 CONFIG_SYS_ISA_IO + 0x20
60#define W83C553F_PIC1_ICW2 CONFIG_SYS_ISA_IO + 0x21
61#define W83C553F_PIC1_ICW3 CONFIG_SYS_ISA_IO + 0x21
62#define W83C553F_PIC1_ICW4 CONFIG_SYS_ISA_IO + 0x21
63#define W83C553F_PIC1_OCW1 CONFIG_SYS_ISA_IO + 0x21
64#define W83C553F_PIC1_OCW2 CONFIG_SYS_ISA_IO + 0x20
65#define W83C553F_PIC1_OCW3 CONFIG_SYS_ISA_IO + 0x20
66#define W83C553F_PIC1_ELC CONFIG_SYS_ISA_IO + 0x4D0
67#define W83C553F_PIC2_ICW1 CONFIG_SYS_ISA_IO + 0xA0
68#define W83C553F_PIC2_ICW2 CONFIG_SYS_ISA_IO + 0xA1
69#define W83C553F_PIC2_ICW3 CONFIG_SYS_ISA_IO + 0xA1
70#define W83C553F_PIC2_ICW4 CONFIG_SYS_ISA_IO + 0xA1
71#define W83C553F_PIC2_OCW1 CONFIG_SYS_ISA_IO + 0xA1
72#define W83C553F_PIC2_OCW2 CONFIG_SYS_ISA_IO + 0xA0
73#define W83C553F_PIC2_OCW3 CONFIG_SYS_ISA_IO + 0xA0
74#define W83C553F_PIC2_ELC CONFIG_SYS_ISA_IO + 0x4D1
wdenk012771d2002-03-08 21:31:05 +0000[diff] [blame]75
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]76#define W83C553F_TMR1_CMOD CONFIG_SYS_ISA_IO + 0x43
wdenk012771d2002-03-08 21:31:05 +0000[diff] [blame]77
78/*
79 * DMA controller
80 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]81#define W83C553F_DMA1 CONFIG_SYS_ISA_IO + 0x000 /* channel 0 - 3 */
82#define W83C553F_DMA2 CONFIG_SYS_ISA_IO + 0x0C0 /* channel 4 - 7 */
wdenk012771d2002-03-08 21:31:05 +0000[diff] [blame]83
84/* command/status register bit definitions */
85
86#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */
87#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */
88#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */
89#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */
90
91#define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */
92#define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */
93#define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */
94#define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */
95
96#define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */
97#define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */
98#define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */
99#define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */
100
101/* mode register bit definitions */
102
103#define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */
104#define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */
105#define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */
106#define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */
107#define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */
108#define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */
109#define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */
110#define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */
111#define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */
112#define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */
113#define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */
114#define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */
115#define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */
116#define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */
117
118/* request register bit definitions */
119
120#define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */
121#define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */
122#define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */
123#define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */
124#define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */
125
126/* write single mask bit register bit definitions */
127
128#define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */
129#define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */
130#define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */
131#define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */
132#define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */
133
134/* read/write all mask bits register bit definitions */
135
136#define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */
137#define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */
138#define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */
139#define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */
140
141/* typedefs */
142
143#define W83C553F_DMA1_CS 0x8
144#define W83C553F_DMA1_WR 0x9
145#define W83C553F_DMA1_WSMB 0xA
146#define W83C553F_DMA1_WM 0xB
147#define W83C553F_DMA1_CBP 0xC
148#define W83C553F_DMA1_MC 0xD
149#define W83C553F_DMA1_CM 0xE
150#define W83C553F_DMA1_RWAMB 0xF
151
152#define W83C553F_DMA2_CS 0x10
153#define W83C553F_DMA2_WR 0x12
154#define W83C553F_DMA2_WSMB 0x14
155#define W83C553F_DMA2_WM 0x16
156#define W83C553F_DMA2_CBP 0x18
157#define W83C553F_DMA2_MC 0x1A
158#define W83C553F_DMA2_CM 0x1C
159#define W83C553F_DMA2_RWAMB 0x1E
160
161void initialise_w83c553f(void);