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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Chander Kashyape21185b2011-05-24 20:02:56 +00002/*
3 * Copyright (C) 2011 Samsung Electronics
4 *
Chander Kashyap393cb362011-12-06 23:34:12 +00005 * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board.
Chander Kashyape21185b2011-05-24 20:02:56 +00006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Simon Glass1d551102014-10-07 22:01:49 -060011#include "exynos4-common.h"
12
Marek Vasute30824f2015-08-19 23:27:26 +020013#undef CONFIG_USB_GADGET_DWC2_OTG_PHY
Simon Glass1d551102014-10-07 22:01:49 -060014
Chander Kashyape21185b2011-05-24 20:02:56 +000015/* High Level Configuration Options */
Chander Kashyap393cb362011-12-06 23:34:12 +000016#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
Chander Kashyape21185b2011-05-24 20:02:56 +000017
Chander Kashyape21185b2011-05-24 20:02:56 +000018#define CONFIG_SYS_SDRAM_BASE 0x40000000
Chander Kashyape21185b2011-05-24 20:02:56 +000019
Chander Kashyape21185b2011-05-24 20:02:56 +000020/* Handling Sleep Mode*/
21#define S5P_CHECK_SLEEP 0x00000BAD
22#define S5P_CHECK_DIDLE 0xBAD00000
Rajeshwari Shinde643be9c2013-07-04 12:29:17 +053023#define S5P_CHECK_LPA 0xABAD0000
Chander Kashyape21185b2011-05-24 20:02:56 +000024
Chander Kashyap5187d8d2011-09-20 21:25:03 +000025/* MMC SPL */
Chander Kashyap9b3ab1c2011-09-20 21:25:04 +000026#define COPY_BL2_FNPTR_ADDR 0x00002488
Chander Kashyape21185b2011-05-24 20:02:56 +000027
Chander Kashyape21185b2011-05-24 20:02:56 +000028/* SMDKV310 has 4 bank of DRAM */
Chander Kashyape21185b2011-05-24 20:02:56 +000029#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
30#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
31#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
32#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
33#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
34#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
35#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
36#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
37#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
38
39/* FLASH and environment organization */
Chander Kashyape21185b2011-05-24 20:02:56 +000040
Chander Kashyape21185b2011-05-24 20:02:56 +000041/* MIU (Memory Interleaving Unit) */
42#define CONFIG_MIU_2BIT_INTERLEAVED
43
Chander Kashyape21185b2011-05-24 20:02:56 +000044#define RESERVE_BLOCK_SIZE (512)
45#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
Chander Kashyape21185b2011-05-24 20:02:56 +000046
Rajeshwari Shinde643be9c2013-07-04 12:29:17 +053047#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
48
49#define CONFIG_SYS_INIT_SP_ADDR 0x02040000
Chander Kashyape21185b2011-05-24 20:02:56 +000050
Chander Kashyape21185b2011-05-24 20:02:56 +000051/* Ethernet Controllor Driver */
52#ifdef CONFIG_CMD_NET
Chander Kashyape21185b2011-05-24 20:02:56 +000053#define CONFIG_ENV_SROM_BANK 1
54#endif /*CONFIG_CMD_NET*/
Thomas Abraham07407d92011-06-03 22:52:17 +000055
Chander Kashyape21185b2011-05-24 20:02:56 +000056#endif /* __CONFIG_H */