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wdenkf12e5682003-07-07 20:07:54 +00001/*
Wolfgang Denk23c5d252014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenkf12e5682003-07-07 20:07:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf12e5682003-07-07 20:07:54 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
21#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
Wolfgang Denk23c5d252014-10-24 15:31:26 +020022#define CONFIG_SYS_GENERIC_BOARD
23#define CONFIG_DISPLAY_BOARDINFO
wdenkf12e5682003-07-07 20:07:54 +000024
Wolfgang Denk2ae18242010-10-06 09:05:45 +020025#define CONFIG_SYS_TEXT_BASE 0x40000000
26
wdenkf12e5682003-07-07 20:07:54 +000027#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020028#define CONFIG_SYS_SMC_RXBUFLEN 128
29#define CONFIG_SYS_MAXIDLE 10
wdenkf12e5682003-07-07 20:07:54 +000030#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
31
wdenkae3af052003-08-07 22:18:11 +000032#define CONFIG_BOOTCOUNT_LIMIT
wdenkf12e5682003-07-07 20:07:54 +000033
wdenkae3af052003-08-07 22:18:11 +000034#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf12e5682003-07-07 20:07:54 +000035
36#define CONFIG_BOARD_TYPES 1 /* support board types */
37
38#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010039 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkf12e5682003-07-07 20:07:54 +000040 "echo"
41
42#undef CONFIG_BOOTARGS
43
44#define CONFIG_EXTRA_ENV_SETTINGS \
45 "netdev=eth0\0" \
46 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010047 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf12e5682003-07-07 20:07:54 +000048 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010049 "addip=setenv bootargs ${bootargs} " \
50 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
51 ":${hostname}:${netdev}:off panic=1\0" \
wdenkf12e5682003-07-07 20:07:54 +000052 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010053 "bootm ${kernel_addr}\0" \
wdenkf12e5682003-07-07 20:07:54 +000054 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010055 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
56 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkf12e5682003-07-07 20:07:54 +000057 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020058 "hostname=TQM855M\0" \
59 "bootfile=TQM855M/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020060 "fdt_addr=40080000\0" \
61 "kernel_addr=400A0000\0" \
62 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020063 "u-boot=TQM855M/u-image.bin\0" \
64 "load=tftp 200000 ${u-boot}\0" \
65 "update=prot off 40000000 +${filesize};" \
66 "era 40000000 +${filesize};" \
67 "cp.b 200000 40000000 ${filesize};" \
68 "sete filesize;save\0" \
wdenkf12e5682003-07-07 20:07:54 +000069 ""
70#define CONFIG_BOOTCOMMAND "run flash_self"
71
72#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf12e5682003-07-07 20:07:54 +000074
75#undef CONFIG_WATCHDOG /* watchdog disabled */
76
77#define CONFIG_STATUS_LED 1 /* Status LED enabled */
78
79#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
80
wdenkd4ca31c2004-01-02 14:00:00 +000081/* enable I2C and select the hardware/software driver */
Heiko Schocherea818db2013-01-29 08:53:15 +010082#define CONFIG_SYS_I2C
83#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
84#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
85#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
wdenkd4ca31c2004-01-02 14:00:00 +000086/*
87 * Software (bit-bang) I2C driver configuration
88 */
89#define PB_SCL 0x00000020 /* PB 26 */
90#define PB_SDA 0x00000010 /* PB 27 */
91
92#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
93#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
94#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
95#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
96#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
97 else immr->im_cpm.cp_pbdat &= ~PB_SDA
98#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
99 else immr->im_cpm.cp_pbdat &= ~PB_SCL
100#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
wdenkd4ca31c2004-01-02 14:00:00 +0000101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
103#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
wdenkd4ca31c2004-01-02 14:00:00 +0000104#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
106#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
107#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
wdenkd4ca31c2004-01-02 14:00:00 +0000108#endif
109
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500110/*
111 * BOOTP options
112 */
113#define CONFIG_BOOTP_SUBNETMASK
114#define CONFIG_BOOTP_GATEWAY
115#define CONFIG_BOOTP_HOSTNAME
116#define CONFIG_BOOTP_BOOTPATH
117#define CONFIG_BOOTP_BOOTFILESIZE
118
wdenkf12e5682003-07-07 20:07:54 +0000119
120#define CONFIG_MAC_PARTITION
121#define CONFIG_DOS_PARTITION
122
123#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
124
wdenkf12e5682003-07-07 20:07:54 +0000125
Jon Loeliger26946902007-07-04 22:30:50 -0500126/*
127 * Command line configuration.
128 */
129#include <config_cmd_default.h>
130
131#define CONFIG_CMD_ASKENV
132#define CONFIG_CMD_DATE
133#define CONFIG_CMD_DHCP
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200134#define CONFIG_CMD_ELF
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100135#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500136#define CONFIG_CMD_EEPROM
137#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200138#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500139#define CONFIG_CMD_NFS
140#define CONFIG_CMD_SNTP
141
wdenkf12e5682003-07-07 20:07:54 +0000142
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200143#define CONFIG_NETCONSOLE
144
145
wdenkf12e5682003-07-07 20:07:54 +0000146/*
147 * Miscellaneous configurable options
148 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkf12e5682003-07-07 20:07:54 +0000150
Wolfgang Denk2751a952006-10-28 02:29:14 +0200151#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkf12e5682003-07-07 20:07:54 +0000153
Jon Loeliger26946902007-07-04 22:30:50 -0500154#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000156#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000158#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
160#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
161#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
164#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf12e5682003-07-07 20:07:54 +0000165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf12e5682003-07-07 20:07:54 +0000167
wdenkf12e5682003-07-07 20:07:54 +0000168/*
169 * Low Level Configuration Settings
170 * (address mappings, register initial values, etc.)
171 * You should know what you are doing if you make changes here.
172 */
173/*-----------------------------------------------------------------------
174 * Internal Memory Mapped Register
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf12e5682003-07-07 20:07:54 +0000177
178/*-----------------------------------------------------------------------
179 * Definitions for initial stack pointer and data area (in DPRAM)
180 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200182#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200183#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf12e5682003-07-07 20:07:54 +0000185
186/*-----------------------------------------------------------------------
187 * Start addresses for the final memory configuration
188 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf12e5682003-07-07 20:07:54 +0000190 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_SDRAM_BASE 0x00000000
192#define CONFIG_SYS_FLASH_BASE 0x40000000
193#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
194#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
195#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf12e5682003-07-07 20:07:54 +0000196
197/*
198 * For booting Linux, the board info and command line data
199 * have to be in the first 8 MB of memory, since this is
200 * the maximum mapped by the Linux kernel during initialization.
201 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf12e5682003-07-07 20:07:54 +0000203
204/*-----------------------------------------------------------------------
205 * FLASH organization
206 */
wdenkf12e5682003-07-07 20:07:54 +0000207
Martin Krausee318d9e2007-09-27 11:10:08 +0200208/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200210#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
212#define CONFIG_SYS_FLASH_EMPTY_INFO
213#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
214#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
215#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkf12e5682003-07-07 20:07:54 +0000216
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200217#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200218#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
219#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
220#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
wdenkf12e5682003-07-07 20:07:54 +0000221
222/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200223#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
224#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf12e5682003-07-07 20:07:54 +0000225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200227
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200228#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
229
wdenkf12e5682003-07-07 20:07:54 +0000230/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200231 * Dynamic MTD partition support
232 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100233#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200234#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
235#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200236#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
237
238#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
239 "128k(dtb)," \
240 "1920k(kernel)," \
241 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200242 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200243
244/*-----------------------------------------------------------------------
wdenkf12e5682003-07-07 20:07:54 +0000245 * Hardware Information Block
246 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
248#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
249#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf12e5682003-07-07 20:07:54 +0000250
251/*-----------------------------------------------------------------------
252 * Cache Configuration
253 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500255#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf12e5682003-07-07 20:07:54 +0000257#endif
258
259/*-----------------------------------------------------------------------
260 * SYPCR - System Protection Control 11-9
261 * SYPCR can only be written once after reset!
262 *-----------------------------------------------------------------------
263 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
264 */
265#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf12e5682003-07-07 20:07:54 +0000267 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
268#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf12e5682003-07-07 20:07:54 +0000270#endif
271
272/*-----------------------------------------------------------------------
273 * SIUMCR - SIU Module Configuration 11-6
274 *-----------------------------------------------------------------------
275 * PCMCIA config., multi-function pin tri-state
276 */
277#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000279#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000281#endif /* CONFIG_CAN_DRIVER */
282
283/*-----------------------------------------------------------------------
284 * TBSCR - Time Base Status and Control 11-26
285 *-----------------------------------------------------------------------
286 * Clear Reference Interrupt Status, Timebase freezing enabled
287 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf12e5682003-07-07 20:07:54 +0000289
290/*-----------------------------------------------------------------------
291 * RTCSC - Real-Time Clock Status and Control Register 11-27
292 *-----------------------------------------------------------------------
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf12e5682003-07-07 20:07:54 +0000295
296/*-----------------------------------------------------------------------
297 * PISCR - Periodic Interrupt Status and Control 11-31
298 *-----------------------------------------------------------------------
299 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
300 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf12e5682003-07-07 20:07:54 +0000302
303/*-----------------------------------------------------------------------
304 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
305 *-----------------------------------------------------------------------
306 * Reset PLL lock status sticky bit, timer expired status bit and timer
307 * interrupt status bit
wdenkf12e5682003-07-07 20:07:54 +0000308 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf12e5682003-07-07 20:07:54 +0000310
311/*-----------------------------------------------------------------------
312 * SCCR - System Clock and reset Control Register 15-27
313 *-----------------------------------------------------------------------
314 * Set clock output, timebase and RTC source and divider,
315 * power management and some other internal clocks
316 */
317#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf12e5682003-07-07 20:07:54 +0000319 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
320 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000321
322/*-----------------------------------------------------------------------
323 * PCMCIA stuff
324 *-----------------------------------------------------------------------
325 *
326 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
328#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
329#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
330#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
331#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
332#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
333#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
334#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf12e5682003-07-07 20:07:54 +0000335
336/*-----------------------------------------------------------------------
337 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
338 *-----------------------------------------------------------------------
339 */
340
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000341#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkf12e5682003-07-07 20:07:54 +0000342#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
343
344#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
345#undef CONFIG_IDE_LED /* LED for ide not supported */
346#undef CONFIG_IDE_RESET /* reset for ide not supported */
347
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
349#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf12e5682003-07-07 20:07:54 +0000350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf12e5682003-07-07 20:07:54 +0000352
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf12e5682003-07-07 20:07:54 +0000354
355/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000357
358/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000360
361/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf12e5682003-07-07 20:07:54 +0000363
364/*-----------------------------------------------------------------------
365 *
366 *-----------------------------------------------------------------------
367 *
368 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_DER 0
wdenkf12e5682003-07-07 20:07:54 +0000370
371/*
372 * Init Memory Controller:
373 *
374 * BR0/1 and OR0/1 (FLASH)
375 */
376
377#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
378#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
379
380/* used to re-map FLASH both when starting from SRAM or FLASH:
381 * restrict access enough to keep SRAM working (if any)
382 * but not too much to meddle with FLASH accesses
383 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
385#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf12e5682003-07-07 20:07:54 +0000386
387/*
388 * FLASH timing:
389 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf12e5682003-07-07 20:07:54 +0000391 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf12e5682003-07-07 20:07:54 +0000392
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
394#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
395#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000396
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
398#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
399#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000400
401/*
402 * BR2/3 and OR2/3 (SDRAM)
403 *
404 */
405#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
406#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
407#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
408
409/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf12e5682003-07-07 20:07:54 +0000411
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
413#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000414
415#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
417#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000418#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
420#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
421#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
422#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf12e5682003-07-07 20:07:54 +0000423 BR_PS_8 | BR_MS_UPMB | BR_V )
424#endif /* CONFIG_CAN_DRIVER */
425
426/*
427 * Memory Periodic Timer Prescaler
428 *
429 * The Divider for PTA (refresh timer) configuration is based on an
430 * example SDRAM configuration (64 MBit, one bank). The adjustment to
431 * the number of chip selects (NCS) and the actually needed refresh
432 * rate is done by setting MPTPR.
433 *
434 * PTA is calculated from
435 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
436 *
437 * gclk CPU clock (not bus clock!)
438 * Trefresh Refresh cycle * 4 (four word bursts used)
439 *
440 * 4096 Rows from SDRAM example configuration
441 * 1000 factor s -> ms
442 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
443 * 4 Number of refresh cycles per period
444 * 64 Refresh cycle in ms per number of rows
445 * --------------------------------------------
446 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
447 *
448 * 50 MHz => 50.000.000 / Divider = 98
449 * 66 Mhz => 66.000.000 / Divider = 129
450 * 80 Mhz => 80.000.000 / Divider = 156
451 */
wdenke9132ea2004-04-24 23:23:30 +0000452
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
454#define CONFIG_SYS_MAMR_PTA 98
wdenkf12e5682003-07-07 20:07:54 +0000455
456/*
457 * For 16 MBit, refresh rates could be 31.3 us
458 * (= 64 ms / 2K = 125 / quad bursts).
459 * For a simpler initialization, 15.6 us is used instead.
460 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
462 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf12e5682003-07-07 20:07:54 +0000463 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
465#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000466
467/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
469#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000470
471/*
472 * MAMR settings for SDRAM
473 */
474
475/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200476#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000477 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
478 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
479/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000481 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
482 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
483
wdenkf12e5682003-07-07 20:07:54 +0000484#define CONFIG_SCC1_ENET
485#define CONFIG_FEC_ENET
Heiko Schocher48690d82010-07-20 17:45:02 +0200486#define CONFIG_ETHPRIME "SCC"
wdenkf12e5682003-07-07 20:07:54 +0000487
Heiko Schocher7026ead2010-02-09 15:50:27 +0100488/* pass open firmware flat tree */
489#define CONFIG_OF_LIBFDT 1
490#define CONFIG_OF_BOARD_SETUP 1
491#define CONFIG_HWCONFIG 1
492
wdenkf12e5682003-07-07 20:07:54 +0000493#endif /* __CONFIG_H */