blob: d4a4b68c8098d5af21d39fa2d29573a112fbcca1 [file] [log] [blame]
stroese13fdf8a2003-09-12 08:55:18 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
stroese13fdf8a2003-09-12 08:55:18 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_405EP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000021#define CONFIG_VOH405 1 /* ...on a VOH405 board */
stroese13fdf8a2003-09-12 08:55:18 +000022
Wolfgang Denk2ae18242010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0xFFF80000
24
wdenkc837dcb2004-01-20 23:12:12 +000025#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
26#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroese13fdf8a2003-09-12 08:55:18 +000027
stroesea20b27a2004-12-16 18:05:42 +000028#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
stroese13fdf8a2003-09-12 08:55:18 +000029
30#define CONFIG_BAUDRATE 9600
31#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
32
33#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000034#undef CONFIG_BOOTCOMMAND
stroese13fdf8a2003-09-12 08:55:18 +000035
stroesea20b27a2004-12-16 18:05:42 +000036#define CONFIG_PREBOOT /* enable preboot variable */
37
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroese13fdf8a2003-09-12 08:55:18 +000039
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +010040#undef CONFIG_HAS_ETH1
41
Ben Warren96e21f82008-10-27 23:50:15 -070042#define CONFIG_PPC4xx_EMAC
stroese13fdf8a2003-09-12 08:55:18 +000043#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000044#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000045#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +010046#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
stroesea20b27a2004-12-16 18:05:42 +000047
48#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
stroese13fdf8a2003-09-12 08:55:18 +000049
Jon Loeligera5562902007-07-08 15:31:57 -050050
51/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050052 * BOOTP options
53 */
54#define CONFIG_BOOTP_BOOTFILESIZE
55#define CONFIG_BOOTP_BOOTPATH
56#define CONFIG_BOOTP_GATEWAY
57#define CONFIG_BOOTP_HOSTNAME
58
59
60/*
Jon Loeligera5562902007-07-08 15:31:57 -050061 * Command line configuration.
62 */
63#include <config_cmd_default.h>
64
65#define CONFIG_CMD_DHCP
66#define CONFIG_CMD_PCI
67#define CONFIG_CMD_IRQ
68#define CONFIG_CMD_IDE
69#define CONFIG_CMD_FAT
70#define CONFIG_CMD_ELF
71#define CONFIG_CMD_NAND
72#define CONFIG_CMD_DATE
73#define CONFIG_CMD_I2C
74#define CONFIG_CMD_MII
75#define CONFIG_CMD_PING
76#define CONFIG_CMD_EEPROM
77
stroese13fdf8a2003-09-12 08:55:18 +000078
79#define CONFIG_MAC_PARTITION
80#define CONFIG_DOS_PARTITION
81
stroesea20b27a2004-12-16 18:05:42 +000082#define CONFIG_SUPPORT_VFAT
83
wdenkc837dcb2004-01-20 23:12:12 +000084#undef CONFIG_WATCHDOG /* watchdog disabled */
stroese13fdf8a2003-09-12 08:55:18 +000085
wdenkc837dcb2004-01-20 23:12:12 +000086#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
stroese13fdf8a2003-09-12 08:55:18 +000088
wdenkc837dcb2004-01-20 23:12:12 +000089#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
stroese13fdf8a2003-09-12 08:55:18 +000090
91/*
92 * Miscellaneous configurable options
93 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_LONGHELP /* undef to save memory */
stroese13fdf8a2003-09-12 08:55:18 +000095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
stroese13fdf8a2003-09-12 08:55:18 +000097
Jon Loeligera5562902007-07-08 15:31:57 -050098#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +0000100#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +0000102#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
104#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
105#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +0000106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroese13fdf8a2003-09-12 08:55:18 +0000108
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroese13fdf8a2003-09-12 08:55:18 +0000110
stroesea20b27a2004-12-16 18:05:42 +0000111#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
114#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroese13fdf8a2003-09-12 08:55:18 +0000115
Stefan Roese550650d2010-09-20 16:05:31 +0200116#define CONFIG_CONS_INDEX 2 /* Use UART1 */
117#define CONFIG_SYS_NS16550
118#define CONFIG_SYS_NS16550_SERIAL
119#define CONFIG_SYS_NS16550_REG_SIZE 1
120#define CONFIG_SYS_NS16550_CLK get_serial_clock()
121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_BASE_BAUD 691200
stroese13fdf8a2003-09-12 08:55:18 +0000124
125/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_BAUDRATE_TABLE \
stroese13fdf8a2003-09-12 08:55:18 +0000127 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
128 57600, 115200, 230400, 460800, 921600 }
129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
131#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroese13fdf8a2003-09-12 08:55:18 +0000132
stroese13fdf8a2003-09-12 08:55:18 +0000133#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
134
wdenkc837dcb2004-01-20 23:12:12 +0000135#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese13fdf8a2003-09-12 08:55:18 +0000136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese13fdf8a2003-09-12 08:55:18 +0000138
139/*-----------------------------------------------------------------------
140 * NAND-FLASH stuff
141 *-----------------------------------------------------------------------
142 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200145#define NAND_BIG_DELAY_US 25
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
148#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
149#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
150#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
stroese13fdf8a2003-09-12 08:55:18 +0000151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
153#define CONFIG_SYS_NAND_QUIET 1
stroesea20b27a2004-12-16 18:05:42 +0000154
stroese13fdf8a2003-09-12 08:55:18 +0000155/*-----------------------------------------------------------------------
156 * PCI stuff
157 *-----------------------------------------------------------------------
158 */
stroesea20b27a2004-12-16 18:05:42 +0000159#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
160#define PCI_HOST_FORCE 1 /* configure as pci host */
161#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroese13fdf8a2003-09-12 08:55:18 +0000162
stroesea20b27a2004-12-16 18:05:42 +0000163#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000164#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
stroesea20b27a2004-12-16 18:05:42 +0000165#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
166#define CONFIG_PCI_PNP /* do pci plug-and-play */
167 /* resource configuration */
stroese13fdf8a2003-09-12 08:55:18 +0000168
stroesea20b27a2004-12-16 18:05:42 +0000169#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroese13fdf8a2003-09-12 08:55:18 +0000170
stroesea20b27a2004-12-16 18:05:42 +0000171#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
174#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
175#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
176#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
177#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
178#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
179#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
180#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
181#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
stroese13fdf8a2003-09-12 08:55:18 +0000182
183/*-----------------------------------------------------------------------
184 * IDE/ATA stuff
185 *-----------------------------------------------------------------------
186 */
wdenkc837dcb2004-01-20 23:12:12 +0000187#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
188#undef CONFIG_IDE_LED /* no led for ide supported */
stroese13fdf8a2003-09-12 08:55:18 +0000189#define CONFIG_IDE_RESET 1 /* reset for ide supported */
190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
192#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
stroese13fdf8a2003-09-12 08:55:18 +0000193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
195#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
196#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0010
stroese13fdf8a2003-09-12 08:55:18 +0000197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
199#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
200#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
stroese13fdf8a2003-09-12 08:55:18 +0000201
202/*
203 * For booting Linux, the board info and command line data
204 * have to be in the first 8 MB of memory, since this is
205 * the maximum mapped by the Linux kernel during initialization.
206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
stroese13fdf8a2003-09-12 08:55:18 +0000208/*-----------------------------------------------------------------------
209 * FLASH organization
210 */
211#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
214#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
stroese13fdf8a2003-09-12 08:55:18 +0000215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
217#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
stroese13fdf8a2003-09-12 08:55:18 +0000218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
220#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
221#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroese13fdf8a2003-09-12 08:55:18 +0000222/*
223 * The following defines are added for buggy IOP480 byte interface.
224 * All other boards should use the standard values (CPCI405 etc.)
225 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
227#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
228#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
stroese13fdf8a2003-09-12 08:55:18 +0000229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroese13fdf8a2003-09-12 08:55:18 +0000231
stroese13fdf8a2003-09-12 08:55:18 +0000232/*-----------------------------------------------------------------------
233 * Start addresses for the final memory configuration
234 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroese13fdf8a2003-09-12 08:55:18 +0000236 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_SDRAM_BASE 0x00000000
238#define CONFIG_SYS_FLASH_BASE 0xFFF80000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200239#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
241#define CONFIG_SYS_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */
stroese13fdf8a2003-09-12 08:55:18 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
244# define CONFIG_SYS_RAMBOOT 1
stroese13fdf8a2003-09-12 08:55:18 +0000245#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246# undef CONFIG_SYS_RAMBOOT
stroese13fdf8a2003-09-12 08:55:18 +0000247#endif
248
249/*-----------------------------------------------------------------------
250 * Environment Variable setup
251 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200252#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200253#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
254#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
stroese13fdf8a2003-09-12 08:55:18 +0000255 /* total size of a CAT24WC16 is 2048 bytes */
256
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
258#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
stroese13fdf8a2003-09-12 08:55:18 +0000259
260/*-----------------------------------------------------------------------
261 * I2C EEPROM (CAT24WC16) for environment
262 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000263#define CONFIG_SYS_I2C
264#define CONFIG_SYS_I2C_PPC4XX
265#define CONFIG_SYS_I2C_PPC4XX_CH0
266#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
267#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
stroese13fdf8a2003-09-12 08:55:18 +0000268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
270#define CONFIG_SYS_EEPROM_WREN 1
Matthias Fuchsb56bd0f2007-12-28 17:10:42 +0100271
stroese13fdf8a2003-09-12 08:55:18 +0000272/* CAT24WC32/64... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +0000274/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
276#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
stroese13fdf8a2003-09-12 08:55:18 +0000277 /* 32 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000278 /* last 5 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroese13fdf8a2003-09-12 08:55:18 +0000280
281/*-----------------------------------------------------------------------
stroese13fdf8a2003-09-12 08:55:18 +0000282 * External Bus Controller (EBC) Setup
283 */
284
wdenkc837dcb2004-01-20 23:12:12 +0000285#define CAN_BA 0xF0000000 /* CAN Base Address */
286#define DUART0_BA 0xF0000400 /* DUART Base Address */
287#define DUART1_BA 0xF0000408 /* DUART Base Address */
288#define RTC_BA 0xF0000500 /* RTC Base Address */
289#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000291
wdenkc837dcb2004-01-20 23:12:12 +0000292/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_EBC_PB0AP 0x92015480
294/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
295#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroese13fdf8a2003-09-12 08:55:18 +0000296
wdenkc837dcb2004-01-20 23:12:12 +0000297/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_EBC_PB1AP 0x92015480
299#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000300
wdenkc837dcb2004-01-20 23:12:12 +0000301/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
303#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000304
wdenkc837dcb2004-01-20 23:12:12 +0000305/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
307#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
stroese13fdf8a2003-09-12 08:55:18 +0000308
wdenkc837dcb2004-01-20 23:12:12 +0000309/* Memory Bank 4 (Epson VGA) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
311#define CONFIG_SYS_EBC_PB4CR VGA_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
stroese13fdf8a2003-09-12 08:55:18 +0000312
313/*-----------------------------------------------------------------------
stroesea20b27a2004-12-16 18:05:42 +0000314 * LCD Setup
315 */
316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
318#define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
319#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
320#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
stroesea20b27a2004-12-16 18:05:42 +0000321
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
stroesea20b27a2004-12-16 18:05:42 +0000323
324/*-----------------------------------------------------------------------
stroese13fdf8a2003-09-12 08:55:18 +0000325 * FPGA stuff
326 */
327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000329
330/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_FPGA_CTRL 0x000
stroese13fdf8a2003-09-12 08:55:18 +0000332
333/* FPGA Control Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001
335#define CONFIG_SYS_FPGA_CTRL_WDI 0x0002
336#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
stroese13fdf8a2003-09-12 08:55:18 +0000337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
339#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
stroese13fdf8a2003-09-12 08:55:18 +0000340
341/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
343#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
344#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
345#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
346#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroese13fdf8a2003-09-12 08:55:18 +0000347
348/*-----------------------------------------------------------------------
349 * Definitions for initial stack pointer and data area (in data cache)
350 */
351/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_TEMP_STACK_OCM 1
stroese13fdf8a2003-09-12 08:55:18 +0000353
354/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
356#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
357#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200358#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
stroese13fdf8a2003-09-12 08:55:18 +0000359
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200360#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroese13fdf8a2003-09-12 08:55:18 +0000362
363/*-----------------------------------------------------------------------
364 * Definitions for GPIO setup (PPC405EP specific)
365 *
wdenkc837dcb2004-01-20 23:12:12 +0000366 * GPIO0[0] - External Bus Controller BLAST output
367 * GPIO0[1-9] - Instruction trace outputs -> GPIO
stroese13fdf8a2003-09-12 08:55:18 +0000368 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
369 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
370 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
371 * GPIO0[24-27] - UART0 control signal inputs/outputs
372 * GPIO0[28-29] - UART1 data signal input/output
stroesea20b27a2004-12-16 18:05:42 +0000373 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
stroese13fdf8a2003-09-12 08:55:18 +0000374 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200375#define CONFIG_SYS_GPIO0_OSRL 0x00000550
376#define CONFIG_SYS_GPIO0_OSRH 0x00000110
377#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
378#define CONFIG_SYS_GPIO0_ISR1H 0x15555440
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_GPIO0_TSRL 0x00000000
Stefan Roeseafabb492010-09-12 06:21:37 +0200380#define CONFIG_SYS_GPIO0_TSRH 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_GPIO0_TCR 0x777E0017
stroese13fdf8a2003-09-12 08:55:18 +0000382
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
384#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7)
385#define CONFIG_SYS_IIC_ON (0x80000000 >> 8)
386#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30)
387#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31)
388#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 0)
stroese13fdf8a2003-09-12 08:55:18 +0000389
390/*
stroese13fdf8a2003-09-12 08:55:18 +0000391 * Default speed selection (cpu_plb_opb_ebc) in mhz.
392 * This value will be set if iic boot eprom is disabled.
393 */
394#if 1
wdenkc837dcb2004-01-20 23:12:12 +0000395#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
396#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000397#endif
398#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000399#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
400#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
stroese13fdf8a2003-09-12 08:55:18 +0000401#endif
402#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000403#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
404#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000405#endif
406
407#endif /* __CONFIG_H */