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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkedc48b62002-09-08 17:56:50 +00002/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenkedc48b62002-09-08 17:56:50 +00005 */
6
7/* for now: just dummy functions to satisfy the linker */
8
wdenk8ed96042005-01-09 23:16:25 +00009#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070010#include <cpu_func.h>
Thierry Reding1dfdd9b2014-12-09 22:25:22 -070011#include <malloc.h>
wdenk8ed96042005-01-09 23:16:25 +000012
Wu, Josh633b6cc2015-07-27 11:40:17 +080013/*
14 * Flush range from all levels of d-cache/unified-cache.
15 * Affects the range [start, start + size - 1].
16 */
Jeroen Hofsteefcfddfd2014-06-23 22:07:04 +020017__weak void flush_cache(unsigned long start, unsigned long size)
wdenkedc48b62002-09-08 17:56:50 +000018{
Wu, Josh633b6cc2015-07-27 11:40:17 +080019 flush_dcache_range(start, start + size);
wdenkedc48b62002-09-08 17:56:50 +000020}
Aneesh Ve05f0072011-06-16 23:30:50 +000021
22/*
23 * Default implementation:
24 * do a range flush for the entire range
25 */
Jeroen Hofsteefcfddfd2014-06-23 22:07:04 +020026__weak void flush_dcache_all(void)
Aneesh Ve05f0072011-06-16 23:30:50 +000027{
28 flush_cache(0, ~0);
29}
Aneesh Vcba4b182011-08-16 04:33:05 +000030
31/*
32 * Default implementation of enable_caches()
33 * Real implementation should be in platform code
34 */
Jeroen Hofsteefcfddfd2014-06-23 22:07:04 +020035__weak void enable_caches(void)
Aneesh Vcba4b182011-08-16 04:33:05 +000036{
37 puts("WARNING: Caches not enabled\n");
38}
Thierry Reding1dfdd9b2014-12-09 22:25:22 -070039
Wu, Josh387871a2015-07-27 11:40:16 +080040__weak void invalidate_dcache_range(unsigned long start, unsigned long stop)
41{
42 /* An empty stub, real implementation should be in platform code */
43}
44__weak void flush_dcache_range(unsigned long start, unsigned long stop)
45{
46 /* An empty stub, real implementation should be in platform code */
47}
48
Simon Glass397b5692016-06-19 19:43:01 -060049int check_cache_range(unsigned long start, unsigned long stop)
50{
51 int ok = 1;
52
53 if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
54 ok = 0;
55
56 if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
57 ok = 0;
58
59 if (!ok) {
Simon Glassbcc53bf2016-06-19 19:43:05 -060060 warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
61 start, stop);
Simon Glass397b5692016-06-19 19:43:01 -060062 }
63
64 return ok;
65}
66
Thierry Reding1dfdd9b2014-12-09 22:25:22 -070067#ifdef CONFIG_SYS_NONCACHED_MEMORY
68/*
69 * Reserve one MMU section worth of address space below the malloc() area that
70 * will be mapped uncached.
71 */
72static unsigned long noncached_start;
73static unsigned long noncached_end;
74static unsigned long noncached_next;
75
76void noncached_init(void)
77{
78 phys_addr_t start, end;
79 size_t size;
80
Stephen Warren5e0404f2019-08-27 11:54:31 -060081 /* If this calculation changes, update board_f.c:reserve_noncached() */
Thierry Reding1dfdd9b2014-12-09 22:25:22 -070082 end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
83 size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
84 start = end - size;
85
86 debug("mapping memory %pa-%pa non-cached\n", &start, &end);
87
88 noncached_start = start;
89 noncached_end = end;
90 noncached_next = start;
91
Trevor Woerner10015022019-05-03 09:41:00 -040092#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
Thierry Reding1dfdd9b2014-12-09 22:25:22 -070093 mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
94#endif
95}
96
97phys_addr_t noncached_alloc(size_t size, size_t align)
98{
99 phys_addr_t next = ALIGN(noncached_next, align);
100
101 if (next >= noncached_end || (noncached_end - next) < size)
102 return 0;
103
104 debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
105 noncached_next = next + size;
106
107 return next;
108}
109#endif /* CONFIG_SYS_NONCACHED_MEMORY */
Albert ARIBAUD62e92072015-10-23 18:06:40 +0200110
Tom Rini3a649402017-03-18 09:01:44 -0400111#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
Albert ARIBAUD62e92072015-10-23 18:06:40 +0200112void invalidate_l2_cache(void)
113{
114 unsigned int val = 0;
115
116 asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
117 : : "r" (val) : "cc");
118 isb();
119}
120#endif