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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 45dee2e620ccec6ac7b3548fe8979a34fd030e5d / . / board / mgcoge / mgcoge.c
blob: e7c3fa00c761796a4ec601f0d83257a3e2d22b54 [file] [log] [blame]
Heiko Schocherac9db062008-01-11 01:12:08 +0100[diff] [blame]1/*
2 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <mpc8260.h>
26#include <ioports.h>
27
28#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
29#include <libfdt.h>
30#endif
31
32/*
33 * I/O Port configuration table
34 *
35 * if conf is 1, then that port pin will be configured at boot time
36 * according to the five values podr/pdir/ppar/psor/pdat for that entry
37 */
38const iop_conf_t iop_conf_tab[4][32] = {
39
40 /* Port A */
41 { /* conf ppar psor pdir podr pdat */
42 /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */
43 /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */
44 /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* PA29 */
45 /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* PA28 */
46 /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* PA27 */
47 /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* PA26 */
48 /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
49 /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
50 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
51 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
52 /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* PA21 */
53 /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* PA20 */
54 /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* PA19 */
55 /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* PA18 */
56 /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* PA17 */
57 /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* PA16 */
58 /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* PA15 */
59 /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* PA14 */
60 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
61 /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
62 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
63 /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
64 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
65 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
66 /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
67 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
68 /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
69 /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
70 /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
71 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
72 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
73 /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
74 },
75
76 /* Port B */
77 { /* conf ppar psor pdir podr pdat */
78 /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */
79 /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */
80 /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */
81 /* PB28 */ { 0, 0, 0, 0, 0, 0 }, /* PB28 */
82 /* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */
83 /* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */
84 /* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */
85 /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */
86 /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */
87 /* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */
88 /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */
89 /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */
90 /* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */
91 /* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */
92 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
93 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
94 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
95 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
96 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
97 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
98 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
99 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
100 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
101 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
102 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
103 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
104 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
105 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
106 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
107 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
108 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
109 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
110 },
111
112 /* Port C */
113 { /* conf ppar psor pdir podr pdat */
114 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
115 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
116 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
117 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
118 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
119 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
120 /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RxClk */
121 /* PC24 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 TxClk */
122 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
123 /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
124 /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
125 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
126 /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
127 /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */
128 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
129 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
130 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
131 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
132 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
133 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
134 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
135 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
136 /* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CTS */
137 /* PC8 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CD */
138 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
139 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
140 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
141 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
142 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
143 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
144 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
145 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
146 },
147
148 /* Port D */
149 { /* conf ppar psor pdir podr pdat */
150 /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
151 /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
152 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
153 /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
154 /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
155 /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
156 /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
157 /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
158 /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
159 /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */
160 /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */
161 /* PD20 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: RTS */
162 /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
163 /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
164 /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
165 /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
166 /* PD15 */ { 0, 0, 0, 0, 0, 0 }, /* PD15 */
167 /* PD14 */ { 0, 0, 0, 0, 0, 0 }, /* PD14 */
168 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
169 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
170 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
171 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
172 /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
173 /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
174 /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
175 /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
176 /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
177 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
178 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
179 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
180 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
181 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
182 }
183};
184
185/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
186 *
187 * This routine performs standard 8260 initialization sequence
188 * and calculates the available memory size. It may be called
189 * several times to try different SDRAM configurations on both
190 * 60x and local buses.
191 */
192static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
193 ulong orx, volatile uchar * base)
194{
195 volatile uchar c = 0xff;
196 volatile uint *sdmr_ptr;
197 volatile uint *orx_ptr;
198 ulong maxsize, size;
199 int i;
200
201 /* We must be able to test a location outsize the maximum legal size
202 * to find out THAT we are outside; but this address still has to be
203 * mapped by the controller. That means, that the initial mapping has
204 * to be (at least) twice as large as the maximum expected size.
205 */
206 maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
207
208 sdmr_ptr = &memctl->memc_psdmr;
209 orx_ptr = &memctl->memc_or1;
210
211 *orx_ptr = orx;
212
213 /*
214 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
215 *
216 * "At system reset, initialization software must set up the
217 * programmable parameters in the memory controller banks registers
218 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
219 * system software should execute the following initialization sequence
220 * for each SDRAM device.
221 *
222 * 1. Issue a PRECHARGE-ALL-BANKS command
223 * 2. Issue eight CBR REFRESH commands
224 * 3. Issue a MODE-SET command to initialize the mode register
225 *
226 * The initial commands are executed by setting P/LSDMR[OP] and
227 * accessing the SDRAM with a single-byte transaction."
228 *
229 * The appropriate BRx/ORx registers have already been set when we
230 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
231 */
232
233 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
234 *base = c;
235
236 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
237 for (i = 0; i < 8; i++)
238 *base = c;
239
240 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
241 *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
242
243 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
244 *base = c;
245
246 size = get_ram_size((long *)base, maxsize);
247 *orx_ptr = orx | ~(size - 1);
248
249 return (size);
250}
251
252long int initdram(int board_type)
253{
254 volatile immap_t *immap = (immap_t *) CFG_IMMR;
255 volatile memctl8260_t *memctl = &immap->im_memctl;
256
257 long psize;
258
259 memctl->memc_psrt = CFG_PSRT;
260 memctl->memc_mptpr = CFG_MPTPR;
261
262#ifndef CFG_RAMBOOT
263 /* 60x SDRAM setup:
264 */
265 psize = try_init (memctl, CFG_PSDMR, CFG_OR1,
266 (uchar *) CFG_SDRAM_BASE);
267#endif /* CFG_RAMBOOT */
268
269 icache_enable ();
270
271 return (psize);
272}
273
274int checkboard(void)
275{
276 puts("Board: mgcoge\n");
277
278 return 0;
279}
280
Heiko Schochere492c902008-03-07 08:13:41 +0100[diff] [blame]281/*
282 * Early board initalization.
283 */
284int board_early_init_r(void)
285{
286 /* setup the UPIOx */
287 *(char *)(CFG_PIGGY_BASE + 0x02) = 0xc0;
288 *(char *)(CFG_PIGGY_BASE + 0x03) = 0x15;
289 return 0;
290}
291
Heiko Schocherac9db062008-01-11 01:12:08 +0100[diff] [blame]292#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
293/*
294 * update "memory" property in the blob
295 */
296void ft_blob_update(void *blob, bd_t *bd)
297{
298 int ret, nodeoffset = 0;
299 ulong memory_data[2] = {0};
Heiko Schochere492c902008-03-07 08:13:41 +0100[diff] [blame]300 ulong flash_data[8] = {0};
Heiko Schocherac9db062008-01-11 01:12:08 +0100[diff] [blame]301
302 memory_data[0] = cpu_to_be32(bd->bi_memstart);
303 memory_data[1] = cpu_to_be32(bd->bi_memsize);
304
305 nodeoffset = fdt_path_offset (blob, "/memory");
306 if (nodeoffset >= 0) {
307 ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
308 sizeof(memory_data));
309 if (ret < 0)
310 printf("ft_blob_update): cannot set /memory/reg "
311 "property err:%s\n", fdt_strerror(ret));
312 }
313 else {
314 /* memory node is required in dts */
315 printf("ft_blob_update(): cannot find /memory node "
316 "err:%s\n", fdt_strerror(nodeoffset));
317 }
Heiko Schochere492c902008-03-07 08:13:41 +0100[diff] [blame]318 /* update Flash addr, size */
319 flash_data[2] = cpu_to_be32(CFG_FLASH_BASE);
320 flash_data[3] = cpu_to_be32(CFG_FLASH_SIZE);
321 flash_data[4] = cpu_to_be32(1);
322 flash_data[5] = cpu_to_be32(0);
323 flash_data[6] = cpu_to_be32(CFG_FLASH_BASE_1);
324 flash_data[7] = cpu_to_be32(CFG_FLASH_SIZE_1);
Heiko Schocherac9db062008-01-11 01:12:08 +0100[diff] [blame]325 nodeoffset = fdt_path_offset (blob, "/localbus");
326 if (nodeoffset >= 0) {
327 ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data,
328 sizeof(flash_data));
329 if (ret < 0)
330 printf("ft_blob_update): cannot set /localbus/ranges "
331 "property err:%s\n", fdt_strerror(ret));
332 }
333 else {
334 /* memory node is required in dts */
335 printf("ft_blob_update(): cannot find /localbus node "
336 "err:%s\n", fdt_strerror(nodeoffset));
337 }
338 /* MAC Adresse */
339 nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet");
340 if (nodeoffset >= 0) {
341 ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr,
342 sizeof(uchar) * 6);
343 if (ret < 0)
344 printf("ft_blob_update): cannot set /soc/cpm/ethernet/mac-address "
345 "property err:%s\n", fdt_strerror(ret));
346 }
347 else {
348 /* memory node is required in dts */
Heiko Schochere492c902008-03-07 08:13:41 +0100[diff] [blame]349 printf("ft_blob_update(): cannot find /soc/cpm/ethernet node "
Heiko Schocherac9db062008-01-11 01:12:08 +0100[diff] [blame]350 "err:%s\n", fdt_strerror(nodeoffset));
351 }
352
353}
354
355void ft_board_setup(void *blob, bd_t *bd)
356{
357 ft_cpu_setup( blob, bd);
358 ft_blob_update(blob, bd);
359}
360#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */