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Andy Fleming9082eea2011-04-07 21:56:05 -05001/*
2 * National Semiconductor PHY drivers
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming9082eea2011-04-07 21:56:05 -05005 *
6 * Copyright 2010-2011 Freescale Semiconductor, Inc.
7 * author Andy Fleming
Andy Fleming9082eea2011-04-07 21:56:05 -05008 */
9#include <phy.h>
10
Heiko Schocher96d0b9e2013-06-04 10:58:09 +020011/* NatSemi DP83630 */
12
13#define DP83630_PHY_PAGESEL_REG 0x13
14#define DP83630_PHY_PTP_COC_REG 0x14
15#define DP83630_PHY_PTP_CLKOUT_EN (1<<15)
16#define DP83630_PHY_RBR_REG 0x17
17
18static int dp83630_config(struct phy_device *phydev)
19{
20 int ptp_coc_reg;
21
22 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
23 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6);
24 ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE,
25 DP83630_PHY_PTP_COC_REG);
26 ptp_coc_reg &= ~DP83630_PHY_PTP_CLKOUT_EN;
27 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG,
28 ptp_coc_reg);
29 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0);
30
31 genphy_config_aneg(phydev);
32
33 return 0;
34}
35
36static struct phy_driver DP83630_driver = {
37 .name = "NatSemi DP83630",
38 .uid = 0x20005ce1,
39 .mask = 0xfffffff0,
40 .features = PHY_BASIC_FEATURES,
41 .config = &dp83630_config,
42 .startup = &genphy_startup,
43 .shutdown = &genphy_shutdown,
44};
45
46
Andy Fleming9082eea2011-04-07 21:56:05 -050047/* DP83865 Link and Auto-Neg Status Register */
48#define MIIM_DP83865_LANR 0x11
49#define MIIM_DP83865_SPD_MASK 0x0018
50#define MIIM_DP83865_SPD_1000 0x0010
51#define MIIM_DP83865_SPD_100 0x0008
52#define MIIM_DP83865_DPX_FULL 0x0002
53
54
55/* NatSemi DP83865 */
Vincent BENOIT5ea667e2015-11-02 18:50:23 +010056static int dp838xx_config(struct phy_device *phydev)
Andy Fleming9082eea2011-04-07 21:56:05 -050057{
58 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
59 genphy_config_aneg(phydev);
60
61 return 0;
62}
63
64static int dp83865_parse_status(struct phy_device *phydev)
65{
66 int mii_reg;
67
68 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR);
69
70 switch (mii_reg & MIIM_DP83865_SPD_MASK) {
71
72 case MIIM_DP83865_SPD_1000:
73 phydev->speed = SPEED_1000;
74 break;
75
76 case MIIM_DP83865_SPD_100:
77 phydev->speed = SPEED_100;
78 break;
79
80 default:
81 phydev->speed = SPEED_10;
82 break;
83
84 }
85
86 if (mii_reg & MIIM_DP83865_DPX_FULL)
87 phydev->duplex = DUPLEX_FULL;
88 else
89 phydev->duplex = DUPLEX_HALF;
90
91 return 0;
92}
93
94static int dp83865_startup(struct phy_device *phydev)
95{
Michal Simekb733c272016-05-18 12:46:12 +020096 int ret;
Andy Fleming9082eea2011-04-07 21:56:05 -050097
Michal Simekb733c272016-05-18 12:46:12 +020098 ret = genphy_update_link(phydev);
99 if (ret)
100 return ret;
101
102 return dp83865_parse_status(phydev);
Andy Fleming9082eea2011-04-07 21:56:05 -0500103}
104
105
106static struct phy_driver DP83865_driver = {
107 .name = "NatSemi DP83865",
108 .uid = 0x20005c70,
109 .mask = 0xfffffff0,
110 .features = PHY_GBIT_FEATURES,
Vincent BENOIT5ea667e2015-11-02 18:50:23 +0100111 .config = &dp838xx_config,
Andy Fleming9082eea2011-04-07 21:56:05 -0500112 .startup = &dp83865_startup,
113 .shutdown = &genphy_shutdown,
114};
115
Vincent BENOIT5ea667e2015-11-02 18:50:23 +0100116/* NatSemi DP83848 */
117static int dp83848_parse_status(struct phy_device *phydev)
118{
119 int mii_reg;
120
121 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
122
123 if(mii_reg & (BMSR_100FULL | BMSR_100HALF)) {
124 phydev->speed = SPEED_100;
125 } else {
126 phydev->speed = SPEED_10;
127 }
128
129 if (mii_reg & (BMSR_10FULL | BMSR_100FULL)) {
130 phydev->duplex = DUPLEX_FULL;
131 } else {
132 phydev->duplex = DUPLEX_HALF;
133 }
134
135 return 0;
136}
137
138static int dp83848_startup(struct phy_device *phydev)
139{
Michal Simekb733c272016-05-18 12:46:12 +0200140 int ret;
Vincent BENOIT5ea667e2015-11-02 18:50:23 +0100141
Michal Simekb733c272016-05-18 12:46:12 +0200142 ret = genphy_update_link(phydev);
143 if (ret)
144 return ret;
145
146 return dp83848_parse_status(phydev);
Vincent BENOIT5ea667e2015-11-02 18:50:23 +0100147}
148
149static struct phy_driver DP83848_driver = {
150 .name = "NatSemi DP83848",
151 .uid = 0x20005c90,
152 .mask = 0x2000ff90,
153 .features = PHY_BASIC_FEATURES,
154 .config = &dp838xx_config,
155 .startup = &dp83848_startup,
156 .shutdown = &genphy_shutdown,
157};
158
Andy Fleming9082eea2011-04-07 21:56:05 -0500159int phy_natsemi_init(void)
160{
Heiko Schocher96d0b9e2013-06-04 10:58:09 +0200161 phy_register(&DP83630_driver);
Andy Fleming9082eea2011-04-07 21:56:05 -0500162 phy_register(&DP83865_driver);
Vincent BENOIT5ea667e2015-11-02 18:50:23 +0100163 phy_register(&DP83848_driver);
Andy Fleming9082eea2011-04-07 21:56:05 -0500164
165 return 0;
166}