wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * armboot - Startup Code for XScale |
| 3 | * |
| 4 | * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> |
| 5 | * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> |
| 6 | * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> |
| 7 | * Copyright (c) 2001 Alex Züpke <azu@sysgo.de> |
| 8 | * Copyright (c) 2002 Kyle Harris <kharris@nexus-tech.net> |
| 9 | * |
| 10 | * See file CREDITS for list of people who contributed to this |
| 11 | * project. |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or |
| 14 | * modify it under the terms of the GNU General Public License as |
| 15 | * published by the Free Software Foundation; either version 2 of |
| 16 | * the License, or (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 26 | * MA 02111-1307 USA |
| 27 | */ |
| 28 | |
| 29 | |
| 30 | |
| 31 | #include <config.h> |
| 32 | #include <version.h> |
| 33 | |
| 34 | .globl _start |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 35 | _start: b reset |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 36 | ldr pc, _undefined_instruction |
| 37 | ldr pc, _software_interrupt |
| 38 | ldr pc, _prefetch_abort |
| 39 | ldr pc, _data_abort |
| 40 | ldr pc, _not_used |
| 41 | ldr pc, _irq |
| 42 | ldr pc, _fiq |
| 43 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 44 | _undefined_instruction: .word undefined_instruction |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 45 | _software_interrupt: .word software_interrupt |
| 46 | _prefetch_abort: .word prefetch_abort |
| 47 | _data_abort: .word data_abort |
| 48 | _not_used: .word not_used |
| 49 | _irq: .word irq |
| 50 | _fiq: .word fiq |
| 51 | |
| 52 | .balignl 16,0xdeadbeef |
| 53 | |
| 54 | |
| 55 | /* |
| 56 | * Startup Code (reset vector) |
| 57 | * |
| 58 | * do important init only if we don't start from memory! |
| 59 | * - relocate armboot to ram |
| 60 | * - setup stack |
| 61 | * - jump to second stage |
| 62 | */ |
| 63 | |
| 64 | /* |
| 65 | * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h) |
| 66 | */ |
| 67 | _TEXT_BASE: |
| 68 | .word TEXT_BASE |
| 69 | |
| 70 | .globl _armboot_start |
| 71 | _armboot_start: |
| 72 | .word _start |
| 73 | |
| 74 | /* |
| 75 | * Note: _armboot_end_data and _armboot_end are defined |
| 76 | * by the (board-dependent) linker script. |
| 77 | * _armboot_end_data is the first usable FLASH address after armboot |
| 78 | */ |
| 79 | .globl _armboot_end_data |
| 80 | _armboot_end_data: |
| 81 | .word armboot_end_data |
| 82 | .globl _armboot_end |
| 83 | _armboot_end: |
| 84 | .word armboot_end |
| 85 | |
| 86 | /* |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame^] | 87 | * This is defined in the board specific linker script |
| 88 | */ |
| 89 | .globl _bss_start |
| 90 | _bss_start: |
| 91 | .word bss_start |
| 92 | |
| 93 | .globl _bss_end |
| 94 | _bss_end: |
| 95 | .word bss_end |
| 96 | |
| 97 | /* |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 98 | * _armboot_real_end is the first usable RAM address behind armboot |
| 99 | * and the various stacks |
| 100 | */ |
| 101 | .globl _armboot_real_end |
| 102 | _armboot_real_end: |
| 103 | .word 0x0badc0de |
| 104 | |
| 105 | /* |
| 106 | * We relocate uboot to this address (end of RAM - 128 KiB) |
| 107 | */ |
| 108 | .globl _uboot_reloc |
| 109 | _uboot_reloc: |
wdenk | 699b13a | 2002-11-03 18:03:52 +0000 | [diff] [blame] | 110 | .word TEXT_BASE |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 111 | |
| 112 | #ifdef CONFIG_USE_IRQ |
| 113 | /* IRQ stack memory (calculated at run-time) */ |
| 114 | .globl IRQ_STACK_START |
| 115 | IRQ_STACK_START: |
| 116 | .word 0x0badc0de |
| 117 | |
| 118 | /* IRQ stack memory (calculated at run-time) */ |
| 119 | .globl FIQ_STACK_START |
| 120 | FIQ_STACK_START: |
| 121 | .word 0x0badc0de |
| 122 | #endif |
| 123 | |
| 124 | |
| 125 | /****************************************************************************/ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 126 | /* */ |
| 127 | /* the actual reset code */ |
| 128 | /* */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 129 | /****************************************************************************/ |
| 130 | |
| 131 | reset: |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 132 | mrs r0,cpsr /* set the cpu to SVC32 mode */ |
| 133 | bic r0,r0,#0x1f /* (superviser mode, M=10011) */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 134 | orr r0,r0,#0x13 |
| 135 | msr cpsr,r0 |
| 136 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 137 | bl cpu_init_crit /* we do sys-critical inits */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 138 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 139 | relocate: /* relocate U-Boot to RAM */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 140 | adr r0, _start /* r0 <- current position of code */ |
| 141 | ldr r2, _armboot_start |
| 142 | ldr r3, _armboot_end |
| 143 | sub r2, r3, r2 /* r2 <- size of armboot */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 144 | ldr r1, _TEXT_BASE |
| 145 | add r2, r0, r2 /* r2 <- source end address */ |
| 146 | |
| 147 | copy_loop: |
| 148 | ldmia r0!, {r3-r10} /* copy from source address [r0] */ |
| 149 | stmia r1!, {r3-r10} /* copy to target address [r1] */ |
| 150 | cmp r0, r2 /* until source end addreee [r2] */ |
| 151 | ble copy_loop |
| 152 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 153 | /* Set up the stack */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 154 | ldr r0, _uboot_reloc /* upper 128 KiB: relocated uboot */ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 155 | sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ |
| 156 | /* FIXME: bdinfo should be here */ |
wdenk | 47cd00f | 2003-03-06 13:39:27 +0000 | [diff] [blame^] | 157 | sub sp, r0, #12 /* leave 3 words for abort-stack */ |
| 158 | |
| 159 | clear_bss: |
| 160 | |
| 161 | ldr r0, _bss_start /* find start of bss segment */ |
| 162 | add r0, r0, #4 /* start at first byte of bss */ |
| 163 | ldr r1, _bss_end /* stop here */ |
| 164 | mov r2, #0x00000000 /* clear */ |
| 165 | |
| 166 | clbss_l:str r2, [r0] /* clear loop... */ |
| 167 | add r0, r0, #4 |
| 168 | cmp r0, r1 |
| 169 | bne clbss_l |
| 170 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 171 | |
| 172 | ldr pc, _start_armboot |
| 173 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 174 | _start_armboot: .word start_armboot |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 175 | |
| 176 | |
| 177 | /****************************************************************************/ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 178 | /* */ |
| 179 | /* CPU_init_critical registers */ |
| 180 | /* */ |
| 181 | /* - setup important registers */ |
| 182 | /* - setup memory timing */ |
| 183 | /* */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 184 | /****************************************************************************/ |
| 185 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 186 | /* Interrupt-Controller base address */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 187 | IC_BASE: .word 0x40d00000 |
| 188 | #define ICMR 0x04 |
| 189 | |
| 190 | /* Reset-Controller */ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 191 | RST_BASE: .word 0x40f00030 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 192 | #define RCSR 0x00 |
| 193 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 194 | /* Operating System Timer */ |
| 195 | OSTIMER_BASE: .word 0x40a00000 |
| 196 | #define OSMR3 0x0C |
| 197 | #define OSCR 0x10 |
| 198 | #define OWER 0x18 |
| 199 | #define OIER 0x1C |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 200 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 201 | /* Clock Manager Registers */ |
wdenk | 7f6c2cb | 2002-11-10 22:06:23 +0000 | [diff] [blame] | 202 | #ifdef CFG_CPUSPEED |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 203 | CC_BASE: .word 0x41300000 |
| 204 | #define CCCR 0x00 |
| 205 | cpuspeed: .word CFG_CPUSPEED |
wdenk | 7f6c2cb | 2002-11-10 22:06:23 +0000 | [diff] [blame] | 206 | #endif |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 207 | /* RS: ??? */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 208 | .macro CPWAIT |
wdenk | 699b13a | 2002-11-03 18:03:52 +0000 | [diff] [blame] | 209 | mrc p15,0,r0,c2,c0,0 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 210 | mov r0,r0 |
| 211 | sub pc,pc,#4 |
| 212 | .endm |
| 213 | |
| 214 | |
| 215 | cpu_init_crit: |
| 216 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 217 | /* mask all IRQs */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 218 | ldr r0, IC_BASE |
| 219 | mov r1, #0x00 |
| 220 | str r1, [r0, #ICMR] |
| 221 | |
wdenk | 7f6c2cb | 2002-11-10 22:06:23 +0000 | [diff] [blame] | 222 | #ifdef CFG_CPUSPEED |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 223 | /* set clock speed */ |
| 224 | ldr r0, CC_BASE |
| 225 | ldr r1, cpuspeed |
| 226 | str r1, [r0, #CCCR] |
wdenk | 7f6c2cb | 2002-11-10 22:06:23 +0000 | [diff] [blame] | 227 | mov r0, #3 |
| 228 | mcr p14, 0, r0, c6, c0, 0 |
| 229 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 230 | |
| 231 | /* |
| 232 | * before relocating, we have to setup RAM timing |
| 233 | * because memory timing is board-dependend, you will |
| 234 | * find a memsetup.S in your board directory. |
| 235 | */ |
| 236 | mov ip, lr |
| 237 | bl memsetup |
| 238 | mov lr, ip |
| 239 | |
| 240 | /* Memory interfaces are working. Disable MMU and enable I-cache. */ |
| 241 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 242 | ldr r0, =0x2001 /* enable access to all coproc. */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 243 | mcr p15, 0, r0, c15, c1, 0 |
wdenk | 699b13a | 2002-11-03 18:03:52 +0000 | [diff] [blame] | 244 | CPWAIT |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 245 | |
| 246 | mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */ |
wdenk | 699b13a | 2002-11-03 18:03:52 +0000 | [diff] [blame] | 247 | CPWAIT |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 248 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 249 | mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */ |
wdenk | 699b13a | 2002-11-03 18:03:52 +0000 | [diff] [blame] | 250 | CPWAIT |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 251 | |
| 252 | mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */ |
wdenk | 699b13a | 2002-11-03 18:03:52 +0000 | [diff] [blame] | 253 | CPWAIT |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 254 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 255 | /* Enable the Icache */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 256 | /* |
| 257 | mrc p15, 0, r0, c1, c0, 0 |
| 258 | orr r0, r0, #0x1800 |
| 259 | mcr p15, 0, r0, c1, c0, 0 |
wdenk | 699b13a | 2002-11-03 18:03:52 +0000 | [diff] [blame] | 260 | CPWAIT |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 261 | */ |
| 262 | mov pc, lr |
| 263 | |
| 264 | |
| 265 | /****************************************************************************/ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 266 | /* */ |
| 267 | /* Interrupt handling */ |
| 268 | /* */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 269 | /****************************************************************************/ |
| 270 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 271 | /* IRQ stack frame */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 272 | |
| 273 | #define S_FRAME_SIZE 72 |
| 274 | |
| 275 | #define S_OLD_R0 68 |
| 276 | #define S_PSR 64 |
| 277 | #define S_PC 60 |
| 278 | #define S_LR 56 |
| 279 | #define S_SP 52 |
| 280 | |
| 281 | #define S_IP 48 |
| 282 | #define S_FP 44 |
| 283 | #define S_R10 40 |
| 284 | #define S_R9 36 |
| 285 | #define S_R8 32 |
| 286 | #define S_R7 28 |
| 287 | #define S_R6 24 |
| 288 | #define S_R5 20 |
| 289 | #define S_R4 16 |
| 290 | #define S_R3 12 |
| 291 | #define S_R2 8 |
| 292 | #define S_R1 4 |
| 293 | #define S_R0 0 |
| 294 | |
| 295 | #define MODE_SVC 0x13 |
| 296 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 297 | /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 298 | |
| 299 | .macro bad_save_user_regs |
| 300 | sub sp, sp, #S_FRAME_SIZE |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 301 | stmia sp, {r0 - r12} /* Calling r0-r12 */ |
| 302 | add r8, sp, #S_PC |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 303 | |
| 304 | ldr r2, _armboot_end |
| 305 | add r2, r2, #CONFIG_STACKSIZE |
| 306 | sub r2, r2, #8 |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 307 | ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ |
| 308 | add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 309 | |
| 310 | add r5, sp, #S_SP |
| 311 | mov r1, lr |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 312 | stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 313 | mov r0, sp |
| 314 | .endm |
| 315 | |
| 316 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 317 | /* use irq_save_user_regs / irq_restore_user_regs for */ |
| 318 | /* IRQ/FIQ handling */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 319 | |
| 320 | .macro irq_save_user_regs |
| 321 | sub sp, sp, #S_FRAME_SIZE |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 322 | stmia sp, {r0 - r12} /* Calling r0-r12 */ |
| 323 | add r8, sp, #S_PC |
| 324 | stmdb r8, {sp, lr}^ /* Calling SP, LR */ |
| 325 | str lr, [r8, #0] /* Save calling PC */ |
| 326 | mrs r6, spsr |
| 327 | str r6, [r8, #4] /* Save CPSR */ |
| 328 | str r0, [r8, #8] /* Save OLD_R0 */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 329 | mov r0, sp |
| 330 | .endm |
| 331 | |
| 332 | .macro irq_restore_user_regs |
| 333 | ldmia sp, {r0 - lr}^ @ Calling r0 - lr |
| 334 | mov r0, r0 |
| 335 | ldr lr, [sp, #S_PC] @ Get PC |
| 336 | add sp, sp, #S_FRAME_SIZE |
| 337 | subs pc, lr, #4 @ return & move spsr_svc into cpsr |
| 338 | .endm |
| 339 | |
| 340 | .macro get_bad_stack |
| 341 | ldr r13, _armboot_end @ setup our mode stack |
| 342 | add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack |
| 343 | sub r13, r13, #8 |
| 344 | |
| 345 | str lr, [r13] @ save caller lr / spsr |
| 346 | mrs lr, spsr |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 347 | str lr, [r13, #4] |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 348 | |
| 349 | mov r13, #MODE_SVC @ prepare SVC-Mode |
| 350 | msr spsr_c, r13 |
| 351 | mov lr, pc |
| 352 | movs pc, lr |
| 353 | .endm |
| 354 | |
| 355 | .macro get_irq_stack @ setup IRQ stack |
| 356 | ldr sp, IRQ_STACK_START |
| 357 | .endm |
| 358 | |
| 359 | .macro get_fiq_stack @ setup FIQ stack |
| 360 | ldr sp, FIQ_STACK_START |
| 361 | .endm |
| 362 | |
| 363 | |
| 364 | /****************************************************************************/ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 365 | /* */ |
| 366 | /* exception handlers */ |
| 367 | /* */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 368 | /****************************************************************************/ |
| 369 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 370 | .align 5 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 371 | undefined_instruction: |
| 372 | get_bad_stack |
| 373 | bad_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 374 | bl do_undefined_instruction |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 375 | |
| 376 | .align 5 |
| 377 | software_interrupt: |
| 378 | get_bad_stack |
| 379 | bad_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 380 | bl do_software_interrupt |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 381 | |
| 382 | .align 5 |
| 383 | prefetch_abort: |
| 384 | get_bad_stack |
| 385 | bad_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 386 | bl do_prefetch_abort |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 387 | |
| 388 | .align 5 |
| 389 | data_abort: |
| 390 | get_bad_stack |
| 391 | bad_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 392 | bl do_data_abort |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 393 | |
| 394 | .align 5 |
| 395 | not_used: |
| 396 | get_bad_stack |
| 397 | bad_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 398 | bl do_not_used |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 399 | |
| 400 | #ifdef CONFIG_USE_IRQ |
| 401 | |
| 402 | .align 5 |
| 403 | irq: |
| 404 | get_irq_stack |
| 405 | irq_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 406 | bl do_irq |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 407 | irq_restore_user_regs |
| 408 | |
| 409 | .align 5 |
| 410 | fiq: |
| 411 | get_fiq_stack |
| 412 | irq_save_user_regs /* someone ought to write a more */ |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 413 | bl do_fiq /* effiction fiq_save_user_regs */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 414 | irq_restore_user_regs |
| 415 | |
| 416 | #else |
| 417 | |
| 418 | .align 5 |
| 419 | irq: |
| 420 | get_bad_stack |
| 421 | bad_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 422 | bl do_irq |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 423 | |
| 424 | .align 5 |
| 425 | fiq: |
| 426 | get_bad_stack |
| 427 | bad_save_user_regs |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 428 | bl do_fiq |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 429 | |
| 430 | #endif |
| 431 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 432 | /************************************************************************/ |
| 433 | /* */ |
| 434 | /* Reset function: the PXA250 has no reset function, so we have to */ |
| 435 | /* perform a watchdog timeout to cause a reset. */ |
| 436 | /* */ |
| 437 | /************************************************************************/ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 438 | .align 5 |
| 439 | .globl reset_cpu |
| 440 | reset_cpu: |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 441 | /* We set OWE:WME (watchdog enable) and wait until timeout happens */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 442 | |
wdenk | 384ae02 | 2002-11-05 00:17:55 +0000 | [diff] [blame] | 443 | ldr r0, OSTIMER_BASE |
| 444 | ldr r1, [r0, #OWER] |
| 445 | orr r1, r1, #0x0001 /* bit0: WME */ |
| 446 | str r1, [r0, #OWER] |
| 447 | |
| 448 | /* OS timer does only wrap every 1165 seconds, so we have to set */ |
| 449 | /* the match register as well. */ |
| 450 | |
| 451 | ldr r1, [r0, #OSCR] /* read OS timer */ |
| 452 | add r1, r1, #0x800 /* let OSMR3 match after */ |
| 453 | add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */ |
| 454 | str r1, [r0, #OSMR3] |
| 455 | |
| 456 | reset_endless: |
| 457 | |
| 458 | b reset_endless |