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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 *
26 * Configuration settings for the CU824 board.
27 *
28 */
29
30/* ------------------------------------------------------------------------- */
31
32/*
33 * board/config.h - configuration options, board specific
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
44#define CONFIG_MPC824X 1
45#define CONFIG_MPC8245 1
46#define CONFIG_BMW 1
47
Wolfgang Denk2ae18242010-10-06 09:05:45 +020048#define CONFIG_SYS_TEXT_BASE 0xFFF00000
49
wdenkc837dcb2004-01-20 23:12:12 +000050#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
51
wdenkc6097192002-11-03 00:24:07 +000052#define CONFIG_CONS_INDEX 1
53#define CONFIG_BAUDRATE 9600
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkc6097192002-11-03 00:24:07 +000055
56#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
57
58#define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */
59#define CONFIG_BOOTDELAY 5
60
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Only use Onboard TSOP-16MB device */
wdenkc6097192002-11-03 00:24:07 +000062#define DOC_PASSIVE_PROBE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_DOC_SUPPORT_2000 1
64#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM 1
65#define CONFIG_SYS_DOC_SHORT_TIMEOUT 1
Jon Loeligerde8b2a62007-07-05 19:32:07 -050066
67
68/*
Jon Loeliger11799432007-07-10 09:02:57 -050069 * BOOTP options
70 */
71#define CONFIG_BOOTP_BOOTFILESIZE
72#define CONFIG_BOOTP_BOOTPATH
73#define CONFIG_BOOTP_GATEWAY
74#define CONFIG_BOOTP_HOSTNAME
75
76
77/*
Jon Loeligerde8b2a62007-07-05 19:32:07 -050078 * Command line configuration.
79 */
80#include <config_cmd_default.h>
81
82#define CONFIG_CMD_DATE
Jon Loeligerde8b2a62007-07-05 19:32:07 -050083#define CONFIG_CMD_ELF
Mike Frysinger029cf6b2011-10-02 10:01:25 +000084#undef CONFIG_CMD_NET
85#undef CONFIG_CMD_NFS
Jon Loeligerde8b2a62007-07-05 19:32:07 -050086
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +010087
wdenkc6097192002-11-03 00:24:07 +000088#if 0
wdenkc6097192002-11-03 00:24:07 +000089#define CONFIG_PCI 1
90#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
91#endif
92
wdenkc6097192002-11-03 00:24:07 +000093/*
94 * Miscellaneous configurable options
95 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_LONGHELP /* undef to save memory */
97#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
98#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000099
100/* Print Buffer Size
101 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
wdenkc6097192002-11-03 00:24:07 +0000103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
105#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
106#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
wdenkc6097192002-11-03 00:24:07 +0000107
108/*-----------------------------------------------------------------------
109 * Start addresses for the final memory configuration
110 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000112 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenkc6097192002-11-03 00:24:07 +0000114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank on RCS#0 */
116#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF800000 /* FLASH bank on RCS#1 */
117#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
118#define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM , CONFIG_SYS_FLASH_BASE1_PRELIM }
wdenkc6097192002-11-03 00:24:07 +0000119
120/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
121 * reset vector is actually located at FFB00100, but the 8245
122 * takes care of us.
123 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenkc6097192002-11-03 00:24:07 +0000125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_EUMB_ADDR 0xFC000000
wdenkc6097192002-11-03 00:24:07 +0000127
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200128#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenkc6097192002-11-03 00:24:07 +0000129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
131#define CONFIG_SYS_MALLOC_LEN (2048 << 10) /* Reserve 2MB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
134#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000135
136 /* Maximum amount of RAM.
137 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 64 MB of (S)DRAM */
wdenkc6097192002-11-03 00:24:07 +0000139
140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
142#undef CONFIG_SYS_RAMBOOT
wdenkc6097192002-11-03 00:24:07 +0000143#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_RAMBOOT
wdenkc6097192002-11-03 00:24:07 +0000145#endif
146
147
148/*-----------------------------------------------------------------------
149 * Definitions for initial stack pointer and data area
150 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
Wolfgang Denk553f0982010-10-26 13:32:32 +0200152#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200153#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000155
156/*
157 * Low Level Configuration Settings
158 * (address mappings, register initial values, etc.)
159 * You should know what you are doing if you make changes here.
160 * For the detail description refer to the MPC8240 user's manual.
161 */
162
163#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_HZ 1000
wdenkc6097192002-11-03 00:24:07 +0000165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_ETH_DEV_FN 0x7800
167#define CONFIG_SYS_ETH_IOBASE 0x00104000
wdenkc6097192002-11-03 00:24:07 +0000168
169 /* Bit-field values for MCCR1.
170 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_ROMNAL 0xf
172#define CONFIG_SYS_ROMFAL 0x1f
173#define CONFIG_SYS_DBUS_SIZE 0x3
wdenkc6097192002-11-03 00:24:07 +0000174
175 /* Bit-field values for MCCR2.
176 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
178#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
wdenkc6097192002-11-03 00:24:07 +0000179
180 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
181 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_BSTOPRE 0 /* FIXME: was 192 */
wdenkc6097192002-11-03 00:24:07 +0000183
184 /* Bit-field values for MCCR3.
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
wdenkc6097192002-11-03 00:24:07 +0000187
188 /* Bit-field values for MCCR4.
189 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */
191#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
192#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
193#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
194#define CONFIG_SYS_SDMODE_BURSTLEN 3 /* SDMODE Burst length */
195#define CONFIG_SYS_ACTORW 0xa /* FIXME was 2 */
196#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
wdenkc6097192002-11-03 00:24:07 +0000197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
wdenkc6097192002-11-03 00:24:07 +0000199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
wdenkc6097192002-11-03 00:24:07 +0000201
202/* Memory bank settings.
203 * Only bits 20-29 are actually used from these vales to set the
204 * start/end addresses. The upper two bits will always be 0, and the lower
205 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
206 * address. Refer to the MPC8240 book.
207 */
208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_BANK0_START 0x00000000
210#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
211#define CONFIG_SYS_BANK0_ENABLE 1
212#define CONFIG_SYS_BANK1_START 0x3ff00000
213#define CONFIG_SYS_BANK1_END 0x3fffffff
214#define CONFIG_SYS_BANK1_ENABLE 0
215#define CONFIG_SYS_BANK2_START 0x3ff00000
216#define CONFIG_SYS_BANK2_END 0x3fffffff
217#define CONFIG_SYS_BANK2_ENABLE 0
218#define CONFIG_SYS_BANK3_START 0x3ff00000
219#define CONFIG_SYS_BANK3_END 0x3fffffff
220#define CONFIG_SYS_BANK3_ENABLE 0
221#define CONFIG_SYS_BANK4_START 0x3ff00000
222#define CONFIG_SYS_BANK4_END 0x3fffffff
223#define CONFIG_SYS_BANK4_ENABLE 0
224#define CONFIG_SYS_BANK5_START 0x3ff00000
225#define CONFIG_SYS_BANK5_END 0x3fffffff
226#define CONFIG_SYS_BANK5_ENABLE 0
227#define CONFIG_SYS_BANK6_START 0x3ff00000
228#define CONFIG_SYS_BANK6_END 0x3fffffff
229#define CONFIG_SYS_BANK6_ENABLE 0
230#define CONFIG_SYS_BANK7_START 0x3ff00000
231#define CONFIG_SYS_BANK7_END 0x3fffffff
232#define CONFIG_SYS_BANK7_ENABLE 0
wdenkc6097192002-11-03 00:24:07 +0000233
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_ODCR 0xff
wdenkc6097192002-11-03 00:24:07 +0000235
236#define CONFIG_PCI 1 /* Include PCI support */
237#undef CONFIG_PCI_PNP
238
239/* PCI Memory space(s) */
240#define PCI_MEM_SPACE1_START 0x80000000
241#define PCI_MEM_SPACE2_START 0xfd000000
242
243/* ROM Spaces */
244#include "../board/bmw/bmw.h"
245
246/* BAT configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
248#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
251#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000252
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
254#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
257#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
260#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
261#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
262#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
263#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
264#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
265#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
266#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenkc6097192002-11-03 00:24:07 +0000267
268/*
269 * For booting Linux, the board info and command line data
270 * have to be in the first 8 MB of memory, since this is
271 * the maximum mapped by the Linux kernel during initialization.
272 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000274
275/*
276 * FLASH organization
277 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_MAX_FLASH_BANKS 0 /* Max number of flash banks */
279#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
wdenkc6097192002-11-03 00:24:07 +0000280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
282#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000283
284/*
285 * Warining: environment is not EMBEDDED in the U-Boot code.
286 * It's stored in flash separately.
287 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200288#define CONFIG_ENV_IS_IN_NVRAM 1
wdenkc6097192002-11-03 00:24:07 +0000289#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200291#define CONFIG_ENV_ADDR 0x7c004000 /* right at the start of NVRAM */
292#define CONFIG_ENV_SIZE 0x1ff0 /* Size of the Environment - 8K */
293#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
wdenkc6097192002-11-03 00:24:07 +0000294
295/*
296 * Cache Configuration
297 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500299#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkc6097192002-11-03 00:24:07 +0000301#endif
302
wdenkc6097192002-11-03 00:24:07 +0000303#endif /* __CONFIG_H */