blob: 17ad88e732ede102d5e5880d97c3198c2285b086 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Henrik Nordström518ce472012-11-25 12:41:36 +01002/*
Stefan Roeseb70ed302014-06-09 11:36:59 +02003 * sunxi_emac.c -- Allwinner A10 ethernet driver
Henrik Nordström518ce472012-11-25 12:41:36 +01004 *
5 * (C) Copyright 2012, Stefan Roese <sr@denx.de>
Henrik Nordström518ce472012-11-25 12:41:36 +01006 */
7
8#include <common.h>
Jagan Teki0ed8eaf2019-02-28 00:26:50 +05309#include <clk.h>
Hans de Goede939ed1c2015-04-19 11:48:19 +020010#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Simon Glass336d4612020-02-03 07:36:16 -070012#include <dm/device_compat.h>
Simon Glassc05ed002020-05-10 11:40:11 -060013#include <linux/delay.h>
Henrik Nordström518ce472012-11-25 12:41:36 +010014#include <linux/err.h>
Stefan Roeseb70ed302014-06-09 11:36:59 +020015#include <malloc.h>
16#include <miiphy.h>
17#include <net.h>
Henrik Nordström518ce472012-11-25 12:41:36 +010018#include <asm/io.h>
19#include <asm/arch/clock.h>
20#include <asm/arch/gpio.h>
21
22/* EMAC register */
Stefan Roeseb70ed302014-06-09 11:36:59 +020023struct emac_regs {
Henrik Nordström518ce472012-11-25 12:41:36 +010024 u32 ctl; /* 0x00 */
25 u32 tx_mode; /* 0x04 */
26 u32 tx_flow; /* 0x08 */
27 u32 tx_ctl0; /* 0x0c */
28 u32 tx_ctl1; /* 0x10 */
29 u32 tx_ins; /* 0x14 */
30 u32 tx_pl0; /* 0x18 */
31 u32 tx_pl1; /* 0x1c */
32 u32 tx_sta; /* 0x20 */
33 u32 tx_io_data; /* 0x24 */
Stefan Roeseb70ed302014-06-09 11:36:59 +020034 u32 tx_io_data1;/* 0x28 */
Henrik Nordström518ce472012-11-25 12:41:36 +010035 u32 tx_tsvl0; /* 0x2c */
36 u32 tx_tsvh0; /* 0x30 */
37 u32 tx_tsvl1; /* 0x34 */
38 u32 tx_tsvh1; /* 0x38 */
39 u32 rx_ctl; /* 0x3c */
40 u32 rx_hash0; /* 0x40 */
41 u32 rx_hash1; /* 0x44 */
42 u32 rx_sta; /* 0x48 */
43 u32 rx_io_data; /* 0x4c */
44 u32 rx_fbc; /* 0x50 */
45 u32 int_ctl; /* 0x54 */
46 u32 int_sta; /* 0x58 */
47 u32 mac_ctl0; /* 0x5c */
48 u32 mac_ctl1; /* 0x60 */
49 u32 mac_ipgt; /* 0x64 */
50 u32 mac_ipgr; /* 0x68 */
51 u32 mac_clrt; /* 0x6c */
52 u32 mac_maxf; /* 0x70 */
53 u32 mac_supp; /* 0x74 */
54 u32 mac_test; /* 0x78 */
55 u32 mac_mcfg; /* 0x7c */
56 u32 mac_mcmd; /* 0x80 */
57 u32 mac_madr; /* 0x84 */
58 u32 mac_mwtd; /* 0x88 */
59 u32 mac_mrdd; /* 0x8c */
60 u32 mac_mind; /* 0x90 */
61 u32 mac_ssrr; /* 0x94 */
62 u32 mac_a0; /* 0x98 */
63 u32 mac_a1; /* 0x9c */
64};
65
66/* SRAMC register */
67struct sunxi_sramc_regs {
68 u32 ctrl0;
69 u32 ctrl1;
70};
71
72/* 0: Disable 1: Aborted frame enable(default) */
73#define EMAC_TX_AB_M (0x1 << 0)
74/* 0: CPU 1: DMA(default) */
75#define EMAC_TX_TM (0x1 << 1)
76
77#define EMAC_TX_SETUP (0)
78
79/* 0: DRQ asserted 1: DRQ automatically(default) */
80#define EMAC_RX_DRQ_MODE (0x1 << 1)
81/* 0: CPU 1: DMA(default) */
82#define EMAC_RX_TM (0x1 << 2)
83/* 0: Normal(default) 1: Pass all Frames */
84#define EMAC_RX_PA (0x1 << 4)
85/* 0: Normal(default) 1: Pass Control Frames */
86#define EMAC_RX_PCF (0x1 << 5)
87/* 0: Normal(default) 1: Pass Frames with CRC Error */
88#define EMAC_RX_PCRCE (0x1 << 6)
89/* 0: Normal(default) 1: Pass Frames with Length Error */
90#define EMAC_RX_PLE (0x1 << 7)
91/* 0: Normal 1: Pass Frames length out of range(default) */
92#define EMAC_RX_POR (0x1 << 8)
93/* 0: Not accept 1: Accept unicast Packets(default) */
94#define EMAC_RX_UCAD (0x1 << 16)
95/* 0: Normal(default) 1: DA Filtering */
96#define EMAC_RX_DAF (0x1 << 17)
97/* 0: Not accept 1: Accept multicast Packets(default) */
98#define EMAC_RX_MCO (0x1 << 20)
99/* 0: Disable(default) 1: Enable Hash filter */
100#define EMAC_RX_MHF (0x1 << 21)
101/* 0: Not accept 1: Accept Broadcast Packets(default) */
102#define EMAC_RX_BCO (0x1 << 22)
103/* 0: Disable(default) 1: Enable SA Filtering */
104#define EMAC_RX_SAF (0x1 << 24)
105/* 0: Normal(default) 1: Inverse Filtering */
106#define EMAC_RX_SAIF (0x1 << 25)
107
108#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
109 EMAC_RX_MCO | EMAC_RX_BCO)
110
111/* 0: Disable 1: Enable Receive Flow Control(default) */
112#define EMAC_MAC_CTL0_RFC (0x1 << 2)
113/* 0: Disable 1: Enable Transmit Flow Control(default) */
114#define EMAC_MAC_CTL0_TFC (0x1 << 3)
115
116#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
117
118/* 0: Disable 1: Enable MAC Frame Length Checking(default) */
119#define EMAC_MAC_CTL1_FLC (0x1 << 1)
120/* 0: Disable(default) 1: Enable Huge Frame */
121#define EMAC_MAC_CTL1_HF (0x1 << 2)
122/* 0: Disable(default) 1: Enable MAC Delayed CRC */
123#define EMAC_MAC_CTL1_DCRC (0x1 << 3)
124/* 0: Disable 1: Enable MAC CRC(default) */
125#define EMAC_MAC_CTL1_CRC (0x1 << 4)
126/* 0: Disable 1: Enable MAC PAD Short frames(default) */
127#define EMAC_MAC_CTL1_PC (0x1 << 5)
128/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
129#define EMAC_MAC_CTL1_VC (0x1 << 6)
130/* 0: Disable(default) 1: Enable MAC auto detect Short frames */
131#define EMAC_MAC_CTL1_ADP (0x1 << 7)
132/* 0: Disable(default) 1: Enable */
133#define EMAC_MAC_CTL1_PRE (0x1 << 8)
134/* 0: Disable(default) 1: Enable */
135#define EMAC_MAC_CTL1_LPE (0x1 << 9)
136/* 0: Disable(default) 1: Enable no back off */
137#define EMAC_MAC_CTL1_NB (0x1 << 12)
138/* 0: Disable(default) 1: Enable */
139#define EMAC_MAC_CTL1_BNB (0x1 << 13)
140/* 0: Disable(default) 1: Enable */
141#define EMAC_MAC_CTL1_ED (0x1 << 14)
142
143#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
144 EMAC_MAC_CTL1_PC)
145
146#define EMAC_MAC_IPGT 0x15
147
Stefan Roeseb70ed302014-06-09 11:36:59 +0200148#define EMAC_MAC_NBTB_IPG1 0xc
Henrik Nordström518ce472012-11-25 12:41:36 +0100149#define EMAC_MAC_NBTB_IPG2 0x12
150
151#define EMAC_MAC_CW 0x37
Stefan Roeseb70ed302014-06-09 11:36:59 +0200152#define EMAC_MAC_RM 0xf
Henrik Nordström518ce472012-11-25 12:41:36 +0100153
154#define EMAC_MAC_MFL 0x0600
155
156/* Receive status */
Stefan Roeseb70ed302014-06-09 11:36:59 +0200157#define EMAC_CRCERR (0x1 << 4)
158#define EMAC_LENERR (0x3 << 5)
Henrik Nordström518ce472012-11-25 12:41:36 +0100159
Hans de Goeded88c2f12015-04-25 13:46:28 +0200160#define EMAC_RX_BUFSIZE 2000
Henrik Nordström518ce472012-11-25 12:41:36 +0100161
Stefan Roeseb70ed302014-06-09 11:36:59 +0200162struct emac_eth_dev {
Hans de Goede8145dea2015-04-16 21:47:06 +0200163 struct emac_regs *regs;
Jagan Teki0ed8eaf2019-02-28 00:26:50 +0530164 struct clk clk;
Hans de Goede8145dea2015-04-16 21:47:06 +0200165 struct mii_dev *bus;
166 struct phy_device *phydev;
Henrik Nordström518ce472012-11-25 12:41:36 +0100167 int link_printed;
Hans de Goede939ed1c2015-04-19 11:48:19 +0200168#ifdef CONFIG_DM_ETH
169 uchar rx_buf[EMAC_RX_BUFSIZE];
170#endif
Henrik Nordström518ce472012-11-25 12:41:36 +0100171};
172
Stefan Roeseb70ed302014-06-09 11:36:59 +0200173struct emac_rxhdr {
Henrik Nordström518ce472012-11-25 12:41:36 +0100174 s16 rx_len;
175 u16 rx_status;
176};
177
Stefan Roeseb70ed302014-06-09 11:36:59 +0200178static void emac_inblk_32bit(void *reg, void *data, int count)
Henrik Nordström518ce472012-11-25 12:41:36 +0100179{
180 int cnt = (count + 3) >> 2;
181
182 if (cnt) {
183 u32 *buf = data;
184
185 do {
186 u32 x = readl(reg);
187 *buf++ = x;
188 } while (--cnt);
189 }
190}
191
Stefan Roeseb70ed302014-06-09 11:36:59 +0200192static void emac_outblk_32bit(void *reg, void *data, int count)
Henrik Nordström518ce472012-11-25 12:41:36 +0100193{
194 int cnt = (count + 3) >> 2;
195
196 if (cnt) {
197 const u32 *buf = data;
198
199 do {
200 writel(*buf++, reg);
201 } while (--cnt);
202 }
203}
204
Stefan Roeseb70ed302014-06-09 11:36:59 +0200205/* Read a word from phyxcer */
Hans de Goede8145dea2015-04-16 21:47:06 +0200206static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
Henrik Nordström518ce472012-11-25 12:41:36 +0100207{
Hans de Goede8145dea2015-04-16 21:47:06 +0200208 struct emac_eth_dev *priv = bus->priv;
209 struct emac_regs *regs = priv->regs;
Henrik Nordström518ce472012-11-25 12:41:36 +0100210
211 /* issue the phy address and reg */
212 writel(addr << 8 | reg, &regs->mac_madr);
213
214 /* pull up the phy io line */
215 writel(0x1, &regs->mac_mcmd);
216
217 /* Wait read complete */
218 mdelay(1);
219
220 /* push down the phy io line */
221 writel(0x0, &regs->mac_mcmd);
222
Hans de Goede8145dea2015-04-16 21:47:06 +0200223 /* And read data */
224 return readl(&regs->mac_mrdd);
Henrik Nordström518ce472012-11-25 12:41:36 +0100225}
226
Stefan Roeseb70ed302014-06-09 11:36:59 +0200227/* Write a word to phyxcer */
Hans de Goede8145dea2015-04-16 21:47:06 +0200228static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
229 u16 value)
Henrik Nordström518ce472012-11-25 12:41:36 +0100230{
Hans de Goede8145dea2015-04-16 21:47:06 +0200231 struct emac_eth_dev *priv = bus->priv;
232 struct emac_regs *regs = priv->regs;
Henrik Nordström518ce472012-11-25 12:41:36 +0100233
234 /* issue the phy address and reg */
235 writel(addr << 8 | reg, &regs->mac_madr);
236
237 /* pull up the phy io line */
238 writel(0x1, &regs->mac_mcmd);
239
240 /* Wait write complete */
241 mdelay(1);
242
243 /* push down the phy io line */
244 writel(0x0, &regs->mac_mcmd);
245
246 /* and write data */
247 writel(value, &regs->mac_mwtd);
248
249 return 0;
250}
251
Hans de Goede8145dea2015-04-16 21:47:06 +0200252static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
Henrik Nordström518ce472012-11-25 12:41:36 +0100253{
Hans de Goede8145dea2015-04-16 21:47:06 +0200254 int ret, mask = 0xffffffff;
255
256#ifdef CONFIG_PHY_ADDR
257 mask = 1 << CONFIG_PHY_ADDR;
258#endif
259
260 priv->bus = mdio_alloc();
261 if (!priv->bus) {
262 printf("Failed to allocate MDIO bus\n");
263 return -ENOMEM;
264 }
265
266 priv->bus->read = emac_mdio_read;
267 priv->bus->write = emac_mdio_write;
268 priv->bus->priv = priv;
269 strcpy(priv->bus->name, "emac");
270
271 ret = mdio_register(priv->bus);
272 if (ret)
273 return ret;
274
275 priv->phydev = phy_find_by_mask(priv->bus, mask,
276 PHY_INTERFACE_MODE_MII);
277 if (!priv->phydev)
278 return -ENODEV;
279
280 phy_connect_dev(priv->phydev, dev);
281 phy_config(priv->phydev);
282
283 return 0;
284}
285
286static void emac_setup(struct emac_eth_dev *priv)
287{
288 struct emac_regs *regs = priv->regs;
Henrik Nordström518ce472012-11-25 12:41:36 +0100289 u32 reg_val;
Henrik Nordström518ce472012-11-25 12:41:36 +0100290
291 /* Set up TX */
292 writel(EMAC_TX_SETUP, &regs->tx_mode);
293
294 /* Set up RX */
295 writel(EMAC_RX_SETUP, &regs->rx_ctl);
296
297 /* Set MAC */
298 /* Set MAC CTL0 */
299 writel(EMAC_MAC_CTL0_SETUP, &regs->mac_ctl0);
300
301 /* Set MAC CTL1 */
Henrik Nordström518ce472012-11-25 12:41:36 +0100302 reg_val = 0;
Hans de Goede8145dea2015-04-16 21:47:06 +0200303 if (priv->phydev->duplex == DUPLEX_FULL)
Henrik Nordström518ce472012-11-25 12:41:36 +0100304 reg_val = (0x1 << 0);
305 writel(EMAC_MAC_CTL1_SETUP | reg_val, &regs->mac_ctl1);
306
307 /* Set up IPGT */
308 writel(EMAC_MAC_IPGT, &regs->mac_ipgt);
309
310 /* Set up IPGR */
311 writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), &regs->mac_ipgr);
312
313 /* Set up Collison window */
314 writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), &regs->mac_clrt);
315
316 /* Set up Max Frame Length */
317 writel(EMAC_MAC_MFL, &regs->mac_maxf);
318}
319
Hans de Goedef9f62d22015-04-18 14:44:38 +0200320static void emac_reset(struct emac_eth_dev *priv)
Henrik Nordström518ce472012-11-25 12:41:36 +0100321{
Hans de Goedef9f62d22015-04-18 14:44:38 +0200322 struct emac_regs *regs = priv->regs;
Henrik Nordström518ce472012-11-25 12:41:36 +0100323
324 debug("resetting device\n");
325
326 /* RESET device */
327 writel(0, &regs->ctl);
328 udelay(200);
329
330 writel(1, &regs->ctl);
331 udelay(200);
332}
333
oliver@schinagl.nlace15202016-11-25 16:38:34 +0100334static int _sunxi_write_hwaddr(struct emac_eth_dev *priv, u8 *enetaddr)
335{
336 struct emac_regs *regs = priv->regs;
337 u32 enetaddr_lo, enetaddr_hi;
338
339 enetaddr_lo = enetaddr[2] | (enetaddr[1] << 8) | (enetaddr[0] << 16);
340 enetaddr_hi = enetaddr[5] | (enetaddr[4] << 8) | (enetaddr[3] << 16);
341
Joe Hershberger6e356862018-05-01 16:33:55 -0500342 writel(enetaddr_hi, &regs->mac_a0);
343 writel(enetaddr_lo, &regs->mac_a1);
oliver@schinagl.nlace15202016-11-25 16:38:34 +0100344
345 return 0;
346}
347
Hans de Goedef9f62d22015-04-18 14:44:38 +0200348static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
Henrik Nordström518ce472012-11-25 12:41:36 +0100349{
Hans de Goedef9f62d22015-04-18 14:44:38 +0200350 struct emac_regs *regs = priv->regs;
Hans de Goede8145dea2015-04-16 21:47:06 +0200351 int ret;
Henrik Nordström518ce472012-11-25 12:41:36 +0100352
353 /* Init EMAC */
354
355 /* Flush RX FIFO */
356 setbits_le32(&regs->rx_ctl, 0x8);
357 udelay(1);
358
359 /* Init MAC */
360
361 /* Soft reset MAC */
Stefan Roeseb70ed302014-06-09 11:36:59 +0200362 clrbits_le32(&regs->mac_ctl0, 0x1 << 15);
Henrik Nordström518ce472012-11-25 12:41:36 +0100363
364 /* Clear RX counter */
365 writel(0x0, &regs->rx_fbc);
366 udelay(1);
367
368 /* Set up EMAC */
Hans de Goede8145dea2015-04-16 21:47:06 +0200369 emac_setup(priv);
Henrik Nordström518ce472012-11-25 12:41:36 +0100370
oliver@schinagl.nlace15202016-11-25 16:38:34 +0100371 _sunxi_write_hwaddr(priv, enetaddr);
Henrik Nordström518ce472012-11-25 12:41:36 +0100372
373 mdelay(1);
374
Hans de Goedef9f62d22015-04-18 14:44:38 +0200375 emac_reset(priv);
Henrik Nordström518ce472012-11-25 12:41:36 +0100376
377 /* PHY POWER UP */
Hans de Goede8145dea2015-04-16 21:47:06 +0200378 ret = phy_startup(priv->phydev);
379 if (ret) {
380 printf("Could not initialize PHY %s\n",
381 priv->phydev->dev->name);
382 return ret;
383 }
Henrik Nordström518ce472012-11-25 12:41:36 +0100384
385 /* Print link status only once */
386 if (!priv->link_printed) {
387 printf("ENET Speed is %d Mbps - %s duplex connection\n",
Hans de Goede8145dea2015-04-16 21:47:06 +0200388 priv->phydev->speed,
389 priv->phydev->duplex ? "FULL" : "HALF");
Henrik Nordström518ce472012-11-25 12:41:36 +0100390 priv->link_printed = 1;
391 }
392
393 /* Set EMAC SPEED depend on PHY */
Hans de Goede8145dea2015-04-16 21:47:06 +0200394 if (priv->phydev->speed == SPEED_100)
395 setbits_le32(&regs->mac_supp, 1 << 8);
396 else
397 clrbits_le32(&regs->mac_supp, 1 << 8);
Henrik Nordström518ce472012-11-25 12:41:36 +0100398
399 /* Set duplex depend on phy */
Hans de Goede8145dea2015-04-16 21:47:06 +0200400 if (priv->phydev->duplex == DUPLEX_FULL)
401 setbits_le32(&regs->mac_ctl1, 1 << 0);
402 else
403 clrbits_le32(&regs->mac_ctl1, 1 << 0);
Henrik Nordström518ce472012-11-25 12:41:36 +0100404
405 /* Enable RX/TX */
406 setbits_le32(&regs->ctl, 0x7);
407
408 return 0;
409}
410
Hans de Goedef9f62d22015-04-18 14:44:38 +0200411static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv, void *packet)
Henrik Nordström518ce472012-11-25 12:41:36 +0100412{
Hans de Goedef9f62d22015-04-18 14:44:38 +0200413 struct emac_regs *regs = priv->regs;
Stefan Roeseb70ed302014-06-09 11:36:59 +0200414 struct emac_rxhdr rxhdr;
Henrik Nordström518ce472012-11-25 12:41:36 +0100415 u32 rxcount;
416 u32 reg_val;
417 int rx_len;
418 int rx_status;
419 int good_packet;
420
421 /* Check packet ready or not */
422
Stefan Roeseb70ed302014-06-09 11:36:59 +0200423 /* Race warning: The first packet might arrive with
Henrik Nordström518ce472012-11-25 12:41:36 +0100424 * the interrupts disabled, but the second will fix
425 */
426 rxcount = readl(&regs->rx_fbc);
427 if (!rxcount) {
428 /* Had one stuck? */
429 rxcount = readl(&regs->rx_fbc);
430 if (!rxcount)
Hans de Goedef9f62d22015-04-18 14:44:38 +0200431 return -EAGAIN;
Henrik Nordström518ce472012-11-25 12:41:36 +0100432 }
433
434 reg_val = readl(&regs->rx_io_data);
435 if (reg_val != 0x0143414d) {
436 /* Disable RX */
Stefan Roeseb70ed302014-06-09 11:36:59 +0200437 clrbits_le32(&regs->ctl, 0x1 << 2);
Henrik Nordström518ce472012-11-25 12:41:36 +0100438
439 /* Flush RX FIFO */
Stefan Roeseb70ed302014-06-09 11:36:59 +0200440 setbits_le32(&regs->rx_ctl, 0x1 << 3);
441 while (readl(&regs->rx_ctl) & (0x1 << 3))
Henrik Nordström518ce472012-11-25 12:41:36 +0100442 ;
443
444 /* Enable RX */
Stefan Roeseb70ed302014-06-09 11:36:59 +0200445 setbits_le32(&regs->ctl, 0x1 << 2);
Henrik Nordström518ce472012-11-25 12:41:36 +0100446
Hans de Goedef9f62d22015-04-18 14:44:38 +0200447 return -EAGAIN;
Henrik Nordström518ce472012-11-25 12:41:36 +0100448 }
449
Stefan Roeseb70ed302014-06-09 11:36:59 +0200450 /* A packet ready now
Henrik Nordström518ce472012-11-25 12:41:36 +0100451 * Get status/length
452 */
453 good_packet = 1;
454
Stefan Roeseb70ed302014-06-09 11:36:59 +0200455 emac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));
Henrik Nordström518ce472012-11-25 12:41:36 +0100456
457 rx_len = rxhdr.rx_len;
458 rx_status = rxhdr.rx_status;
459
460 /* Packet Status check */
461 if (rx_len < 0x40) {
462 good_packet = 0;
463 debug("RX: Bad Packet (runt)\n");
464 }
465
466 /* rx_status is identical to RSR register. */
467 if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
468 good_packet = 0;
469 if (rx_status & EMAC_CRCERR)
470 printf("crc error\n");
471 if (rx_status & EMAC_LENERR)
472 printf("length error\n");
473 }
474
Stefan Roeseb70ed302014-06-09 11:36:59 +0200475 /* Move data from EMAC */
Henrik Nordström518ce472012-11-25 12:41:36 +0100476 if (good_packet) {
Hans de Goeded88c2f12015-04-25 13:46:28 +0200477 if (rx_len > EMAC_RX_BUFSIZE) {
Henrik Nordström518ce472012-11-25 12:41:36 +0100478 printf("Received packet is too big (len=%d)\n", rx_len);
Hans de Goedef9f62d22015-04-18 14:44:38 +0200479 return -EMSGSIZE;
Henrik Nordström518ce472012-11-25 12:41:36 +0100480 }
Hans de Goedef9f62d22015-04-18 14:44:38 +0200481 emac_inblk_32bit((void *)&regs->rx_io_data, packet, rx_len);
482 return rx_len;
Henrik Nordström518ce472012-11-25 12:41:36 +0100483 }
484
Hans de Goedef9f62d22015-04-18 14:44:38 +0200485 return -EIO; /* Bad packet */
Henrik Nordström518ce472012-11-25 12:41:36 +0100486}
487
Hans de Goedef9f62d22015-04-18 14:44:38 +0200488static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
489 int len)
Henrik Nordström518ce472012-11-25 12:41:36 +0100490{
Hans de Goedef9f62d22015-04-18 14:44:38 +0200491 struct emac_regs *regs = priv->regs;
Henrik Nordström518ce472012-11-25 12:41:36 +0100492
493 /* Select channel 0 */
494 writel(0, &regs->tx_ins);
495
496 /* Write packet */
Stefan Roeseb70ed302014-06-09 11:36:59 +0200497 emac_outblk_32bit((void *)&regs->tx_io_data, packet, len);
Henrik Nordström518ce472012-11-25 12:41:36 +0100498
499 /* Set TX len */
500 writel(len, &regs->tx_pl0);
501
502 /* Start translate from fifo to phy */
503 setbits_le32(&regs->tx_ctl0, 1);
504
505 return 0;
506}
507
Sean Andersone2f74212020-09-15 10:44:59 -0400508static int sunxi_emac_board_setup(struct udevice *dev,
509 struct emac_eth_dev *priv)
Henrik Nordström518ce472012-11-25 12:41:36 +0100510{
Henrik Nordström518ce472012-11-25 12:41:36 +0100511 struct sunxi_sramc_regs *sram =
512 (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
Hans de Goedef9f62d22015-04-18 14:44:38 +0200513 struct emac_regs *regs = priv->regs;
Jagan Teki0ed8eaf2019-02-28 00:26:50 +0530514 int pin, ret;
Hans de Goedef9f62d22015-04-18 14:44:38 +0200515
516 /* Map SRAM to EMAC */
517 setbits_le32(&sram->ctrl1, 0x5 << 2);
518
519 /* Configure pin mux settings for MII Ethernet */
520 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
521 sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
522
523 /* Set up clock gating */
Jagan Teki0ed8eaf2019-02-28 00:26:50 +0530524 ret = clk_enable(&priv->clk);
525 if (ret) {
526 dev_err(dev, "failed to enable emac clock\n");
527 return ret;
528 }
Hans de Goedef9f62d22015-04-18 14:44:38 +0200529
530 /* Set MII clock */
531 clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
Jagan Teki0ed8eaf2019-02-28 00:26:50 +0530532
533 return 0;
Hans de Goedef9f62d22015-04-18 14:44:38 +0200534}
535
Hans de Goede939ed1c2015-04-19 11:48:19 +0200536static int sunxi_emac_eth_start(struct udevice *dev)
537{
Simon Glassc69cda22020-12-03 16:55:20 -0700538 struct eth_pdata *pdata = dev_get_plat(dev);
Hans de Goede939ed1c2015-04-19 11:48:19 +0200539
Simon Glass0fd3d912020-12-22 19:30:28 -0700540 return _sunxi_emac_eth_init(dev_get_priv(dev), pdata->enetaddr);
Hans de Goede939ed1c2015-04-19 11:48:19 +0200541}
542
543static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length)
544{
545 struct emac_eth_dev *priv = dev_get_priv(dev);
546
547 return _sunxi_emac_eth_send(priv, packet, length);
548}
549
Simon Glassa1ca92e2015-07-06 16:47:49 -0600550static int sunxi_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
Hans de Goede939ed1c2015-04-19 11:48:19 +0200551{
552 struct emac_eth_dev *priv = dev_get_priv(dev);
553 int rx_len;
554
555 rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf);
556 *packetp = priv->rx_buf;
557
558 return rx_len;
559}
560
561static void sunxi_emac_eth_stop(struct udevice *dev)
562{
563 /* Nothing to do here */
564}
565
566static int sunxi_emac_eth_probe(struct udevice *dev)
567{
Simon Glassc69cda22020-12-03 16:55:20 -0700568 struct eth_pdata *pdata = dev_get_plat(dev);
Hans de Goede939ed1c2015-04-19 11:48:19 +0200569 struct emac_eth_dev *priv = dev_get_priv(dev);
Jagan Teki0ed8eaf2019-02-28 00:26:50 +0530570 int ret;
Hans de Goede939ed1c2015-04-19 11:48:19 +0200571
572 priv->regs = (struct emac_regs *)pdata->iobase;
Jagan Teki0ed8eaf2019-02-28 00:26:50 +0530573
574 ret = clk_get_by_index(dev, 0, &priv->clk);
575 if (ret) {
576 dev_err(dev, "failed to get emac clock\n");
577 return ret;
578 }
579
Sean Andersone2f74212020-09-15 10:44:59 -0400580 ret = sunxi_emac_board_setup(dev, priv);
Jagan Teki0ed8eaf2019-02-28 00:26:50 +0530581 if (ret)
582 return ret;
Hans de Goede939ed1c2015-04-19 11:48:19 +0200583
584 return sunxi_emac_init_phy(priv, dev);
585}
586
587static const struct eth_ops sunxi_emac_eth_ops = {
588 .start = sunxi_emac_eth_start,
589 .send = sunxi_emac_eth_send,
590 .recv = sunxi_emac_eth_recv,
591 .stop = sunxi_emac_eth_stop,
592};
593
Simon Glassd1998a92020-12-03 16:55:21 -0700594static int sunxi_emac_eth_of_to_plat(struct udevice *dev)
Hans de Goede939ed1c2015-04-19 11:48:19 +0200595{
Simon Glassc69cda22020-12-03 16:55:20 -0700596 struct eth_pdata *pdata = dev_get_plat(dev);
Hans de Goede939ed1c2015-04-19 11:48:19 +0200597
Masahiro Yamada25484932020-07-17 14:36:48 +0900598 pdata->iobase = dev_read_addr(dev);
Hans de Goede939ed1c2015-04-19 11:48:19 +0200599
600 return 0;
601}
602
603static const struct udevice_id sunxi_emac_eth_ids[] = {
604 { .compatible = "allwinner,sun4i-a10-emac" },
605 { }
606};
607
608U_BOOT_DRIVER(eth_sunxi_emac) = {
609 .name = "eth_sunxi_emac",
610 .id = UCLASS_ETH,
611 .of_match = sunxi_emac_eth_ids,
Simon Glassd1998a92020-12-03 16:55:21 -0700612 .of_to_plat = sunxi_emac_eth_of_to_plat,
Hans de Goede939ed1c2015-04-19 11:48:19 +0200613 .probe = sunxi_emac_eth_probe,
614 .ops = &sunxi_emac_eth_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700615 .priv_auto = sizeof(struct emac_eth_dev),
Simon Glasscaa4daa2020-12-03 16:55:18 -0700616 .plat_auto = sizeof(struct eth_pdata),
Hans de Goede939ed1c2015-04-19 11:48:19 +0200617};