blob: 0913ce4e6916593e4d3286ea0c573cb3f79d6c5d [file] [log] [blame]
Mike Frysingercb4b5e82008-10-12 23:08:03 -04001/*
2 * U-boot - Configuration file for BF537 PNAV board
3 */
4
5#ifndef __CONFIG_BF537_PNAV_H__
6#define __CONFIG_BF537_PNAV_H__
7
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingercb4b5e82008-10-12 23:08:03 -04009
10
11/*
12 * Processor Settings
13 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050014#define CONFIG_BFIN_CPU bf537-0.2
Mike Frysingercb4b5e82008-10-12 23:08:03 -040015#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 24576000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 20
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 4
40
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 10
46#define CONFIG_MEM_SIZE 64
47
48#define CONFIG_EBIU_SDRRC_VAL 0x3b7
49#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
50
51#define CONFIG_EBIU_AMGCTL_VAL 0xFF
52#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0
53#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
54
Mike Frysinger4c95ff62010-10-01 19:42:08 -040055#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
Mike Frysingercb4b5e82008-10-12 23:08:03 -040056#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
57
58
59/*
60 * Network Settings
61 */
62#ifndef __ADSPBF534__
63#define ADI_CMDS_NETWORK 1
64#define CONFIG_BFIN_MAC
65#define CONFIG_RMII
66#define CONFIG_NET_MULTI 1
67#endif
68#define CONFIG_HOSTNAME bf537-pnav
69/* Uncomment next line to use fixed MAC address */
70/* #define CONFIG_ETHADDR 02:80:ad:24:21:18 */
71
72
73/*
74 * Flash Settings
75 */
76#define CONFIG_FLASH_CFI_DRIVER
77#define CONFIG_SYS_FLASH_BASE 0x20000000
78#define CONFIG_SYS_FLASH_CFI
79#define CONFIG_SYS_MAX_FLASH_BANKS 1
80#define CONFIG_SYS_MAX_FLASH_SECT 71
81
82
83/*
84 * SPI Settings
85 */
86#define CONFIG_BFIN_SPI
87#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysingerafac8b02009-06-14 22:29:35 -040088#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysingercb4b5e82008-10-12 23:08:03 -040089#define CONFIG_SPI_FLASH
90#define CONFIG_SPI_FLASH_STMICRO
91
92
93/*
94 * Env Storage Settings
95 */
96#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
Mike Frysinger76d82182009-07-21 22:17:36 -040097#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysingercb4b5e82008-10-12 23:08:03 -040098#define CONFIG_ENV_IS_IN_SPI_FLASH
99#define CONFIG_ENV_OFFSET 0x4000
100#else
101#define ENV_IS_EMBEDDED
102#define CONFIG_ENV_IS_IN_FLASH 1
103#define CONFIG_ENV_ADDR 0x20004000
104#define CONFIG_ENV_OFFSET 0x4000
105#endif
106#define CONFIG_ENV_SIZE 0x1000
107#define CONFIG_ENV_SECT_SIZE 0x2000
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400108#ifdef ENV_IS_EMBEDDED
109/* WARNING - the following is hand-optimized to fit within
110 * the sector before the environment sector. If it throws
111 * an error during compilation remove an object here to get
112 * it linked after the configuration sector.
113 */
114# define LDS_BOARD_TEXT \
Mike Frysingerc70e7dd2010-11-19 19:28:56 -0500115 arch/blackfin/lib/libblackfin.o (.text*); \
116 arch/blackfin/cpu/libblackfin.o (.text*); \
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400117 . = DEFINED(env_offset) ? env_offset : .; \
Mike Frysingerc70e7dd2010-11-19 19:28:56 -0500118 common/env_embedded.o (.text*);
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400119#endif
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400120
121
122/*
123 * NAND Settings
124 */
125#define CONFIG_NAND_PLAT
126
127#define CONFIG_SYS_NAND_BASE 0x20100000
128#define CONFIG_SYS_MAX_NAND_DEVICE 1
129
130#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
131#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400132#define BFIN_NAND_WRITE(addr, cmd) \
133 do { \
134 bfin_write8(addr, cmd); \
135 SSYNC(); \
136 } while (0)
137
138#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
139#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
Mike Frysinger67ceefa2010-07-05 04:55:05 -0400140#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400141
142
143/*
144 * I2C settings
145 */
146#define CONFIG_BFIN_TWI_I2C 1
147#define CONFIG_HARD_I2C 1
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400148
149
150/*
151 * Misc Settings
152 */
153#define CONFIG_BAUDRATE 115200
154#define CONFIG_MISC_INIT_R
155#define CONFIG_RTC_BFIN
156#define CONFIG_UART_CONSOLE 0
157
158/* JFFS Partition offset set */
159#define CONFIG_SYS_JFFS2_FIRST_BANK 0
160#define CONFIG_SYS_JFFS2_NUM_BANKS 1
161/* 512k reserved for u-boot */
162#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
163
164#define CONFIG_BOOTCOMMAND "run nandboot"
165#define CONFIG_BOOTARGS_ROOT "/dev/mtdblock1 rw rootfstype=yaffs"
166
167
168/*
169 * Pull in common ADI header for remaining command/environment setup
170 */
171#include <configs/bfin_adi_common.h>
172
Mike Frysingercb4b5e82008-10-12 23:08:03 -0400173#endif