Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Source for AM33XX SoC |
| 3 | * |
| 4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of any |
| 8 | * kind, whether express or implied. |
| 9 | */ |
| 10 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 11 | #include <dt-bindings/bus/ti-sysc.h> |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 12 | #include <dt-bindings/gpio/gpio.h> |
| 13 | #include <dt-bindings/pinctrl/am33xx.h> |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 14 | #include <dt-bindings/clock/am3.h> |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 15 | |
| 16 | / { |
| 17 | compatible = "ti,am33xx"; |
| 18 | interrupt-parent = <&intc>; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 19 | #address-cells = <1>; |
| 20 | #size-cells = <1>; |
| 21 | chosen { }; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 22 | |
| 23 | aliases { |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 24 | i2c0 = &i2c0; |
| 25 | i2c1 = &i2c1; |
| 26 | i2c2 = &i2c2; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 27 | serial0 = &uart0; |
| 28 | serial1 = &uart1; |
| 29 | serial2 = &uart2; |
| 30 | serial3 = &uart3; |
| 31 | serial4 = &uart4; |
| 32 | serial5 = &uart5; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 33 | d-can0 = &dcan0; |
| 34 | d-can1 = &dcan1; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 35 | usb0 = &usb0; |
| 36 | usb1 = &usb1; |
| 37 | phy0 = &usb0_phy; |
| 38 | phy1 = &usb1_phy; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 39 | ethernet0 = &cpsw_emac0; |
| 40 | ethernet1 = &cpsw_emac1; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 41 | spi0 = &spi0; |
| 42 | spi1 = &spi1; |
Lukasz Majewski | ab9e48f | 2022-02-18 13:28:42 +0100 | [diff] [blame^] | 43 | mmc0 = &mmc1; |
| 44 | mmc1 = &mmc2; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 45 | }; |
| 46 | |
| 47 | cpus { |
| 48 | #address-cells = <1>; |
| 49 | #size-cells = <0>; |
| 50 | cpu@0 { |
| 51 | compatible = "arm,cortex-a8"; |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 52 | enable-method = "ti,am3352"; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 53 | device_type = "cpu"; |
| 54 | reg = <0>; |
| 55 | |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 56 | operating-points-v2 = <&cpu0_opp_table>; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 57 | |
| 58 | clocks = <&dpll_mpu_ck>; |
| 59 | clock-names = "cpu"; |
| 60 | |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 61 | clock-latency = <300000>; /* From omap-cpufreq driver */ |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 62 | cpu-idle-states = <&mpu_gate>; |
| 63 | }; |
| 64 | |
| 65 | idle-states { |
| 66 | mpu_gate: mpu_gate { |
| 67 | compatible = "arm,idle-state"; |
| 68 | entry-latency-us = <40>; |
| 69 | exit-latency-us = <90>; |
| 70 | min-residency-us = <300>; |
| 71 | ti,idle-wkup-m3; |
| 72 | }; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 73 | }; |
| 74 | }; |
| 75 | |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 76 | cpu0_opp_table: opp-table { |
| 77 | compatible = "operating-points-v2-ti-cpu"; |
| 78 | syscon = <&scm_conf>; |
| 79 | |
| 80 | /* |
| 81 | * The three following nodes are marked with opp-suspend |
| 82 | * because the can not be enabled simultaneously on a |
| 83 | * single SoC. |
| 84 | */ |
| 85 | opp50-300000000 { |
| 86 | opp-hz = /bits/ 64 <300000000>; |
| 87 | opp-microvolt = <950000 931000 969000>; |
| 88 | opp-supported-hw = <0x06 0x0010>; |
| 89 | opp-suspend; |
| 90 | }; |
| 91 | |
| 92 | opp100-275000000 { |
| 93 | opp-hz = /bits/ 64 <275000000>; |
| 94 | opp-microvolt = <1100000 1078000 1122000>; |
| 95 | opp-supported-hw = <0x01 0x00FF>; |
| 96 | opp-suspend; |
| 97 | }; |
| 98 | |
| 99 | opp100-300000000 { |
| 100 | opp-hz = /bits/ 64 <300000000>; |
| 101 | opp-microvolt = <1100000 1078000 1122000>; |
| 102 | opp-supported-hw = <0x06 0x0020>; |
| 103 | opp-suspend; |
| 104 | }; |
| 105 | |
| 106 | opp100-500000000 { |
| 107 | opp-hz = /bits/ 64 <500000000>; |
| 108 | opp-microvolt = <1100000 1078000 1122000>; |
| 109 | opp-supported-hw = <0x01 0xFFFF>; |
| 110 | }; |
| 111 | |
| 112 | opp100-600000000 { |
| 113 | opp-hz = /bits/ 64 <600000000>; |
| 114 | opp-microvolt = <1100000 1078000 1122000>; |
| 115 | opp-supported-hw = <0x06 0x0040>; |
| 116 | }; |
| 117 | |
| 118 | opp120-600000000 { |
| 119 | opp-hz = /bits/ 64 <600000000>; |
| 120 | opp-microvolt = <1200000 1176000 1224000>; |
| 121 | opp-supported-hw = <0x01 0xFFFF>; |
| 122 | }; |
| 123 | |
| 124 | opp120-720000000 { |
| 125 | opp-hz = /bits/ 64 <720000000>; |
| 126 | opp-microvolt = <1200000 1176000 1224000>; |
| 127 | opp-supported-hw = <0x06 0x0080>; |
| 128 | }; |
| 129 | |
| 130 | oppturbo-720000000 { |
| 131 | opp-hz = /bits/ 64 <720000000>; |
| 132 | opp-microvolt = <1260000 1234800 1285200>; |
| 133 | opp-supported-hw = <0x01 0xFFFF>; |
| 134 | }; |
| 135 | |
| 136 | oppturbo-800000000 { |
| 137 | opp-hz = /bits/ 64 <800000000>; |
| 138 | opp-microvolt = <1260000 1234800 1285200>; |
| 139 | opp-supported-hw = <0x06 0x0100>; |
| 140 | }; |
| 141 | |
| 142 | oppnitro-1000000000 { |
| 143 | opp-hz = /bits/ 64 <1000000000>; |
| 144 | opp-microvolt = <1325000 1298500 1351500>; |
| 145 | opp-supported-hw = <0x04 0x0200>; |
| 146 | }; |
| 147 | }; |
| 148 | |
| 149 | pmu@4b000000 { |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 150 | compatible = "arm,cortex-a8-pmu"; |
| 151 | interrupts = <3>; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 152 | reg = <0x4b000000 0x1000000>; |
| 153 | ti,hwmods = "debugss"; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 154 | }; |
| 155 | |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 156 | /* |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 157 | * The soc node represents the soc top level view. It is used for IPs |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 158 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 159 | */ |
| 160 | soc { |
| 161 | compatible = "ti,omap-infra"; |
| 162 | mpu { |
| 163 | compatible = "ti,omap3-mpu"; |
| 164 | ti,hwmods = "mpu"; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 165 | pm-sram = <&pm_sram_code |
| 166 | &pm_sram_data>; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 167 | }; |
| 168 | }; |
| 169 | |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 170 | /* |
| 171 | * XXX: Use a flat representation of the AM33XX interconnect. |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 172 | * The real AM33XX interconnect network is quite complex. Since |
| 173 | * it will not bring real advantage to represent that in DT |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 174 | * for the moment, just use a fake OCP bus entry to represent |
| 175 | * the whole bus hierarchy. |
| 176 | */ |
| 177 | ocp { |
| 178 | compatible = "simple-bus"; |
| 179 | #address-cells = <1>; |
| 180 | #size-cells = <1>; |
| 181 | ranges; |
| 182 | ti,hwmods = "l3_main"; |
| 183 | |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 184 | l4_wkup: l4_wkup@44c00000 { |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 185 | wkup_m3: wkup_m3@100000 { |
| 186 | compatible = "ti,am3352-wkup-m3"; |
| 187 | reg = <0x100000 0x4000>, |
| 188 | <0x180000 0x2000>; |
| 189 | reg-names = "umem", "dmem"; |
| 190 | ti,hwmods = "wkup_m3"; |
| 191 | ti,pm-firmware = "am335x-pm-firmware.elf"; |
| 192 | }; |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 193 | }; |
| 194 | l4_per: interconnect@48000000 { |
| 195 | }; |
| 196 | l4_fw: interconnect@47c00000 { |
| 197 | }; |
| 198 | l4_fast: interconnect@4a000000 { |
| 199 | }; |
| 200 | l4_mpuss: interconnect@4b140000 { |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 201 | }; |
| 202 | |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 203 | intc: interrupt-controller@48200000 { |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 204 | compatible = "ti,am33xx-intc"; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 205 | interrupt-controller; |
| 206 | #interrupt-cells = <1>; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 207 | reg = <0x48200000 0x1000>; |
| 208 | }; |
| 209 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 210 | target-module@49000000 { |
| 211 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 212 | reg = <0x49000000 0x4>; |
| 213 | reg-names = "rev"; |
| 214 | clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>; |
| 215 | clock-names = "fck"; |
| 216 | #address-cells = <1>; |
| 217 | #size-cells = <1>; |
| 218 | ranges = <0x0 0x49000000 0x10000>; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 219 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 220 | edma: dma@0 { |
| 221 | compatible = "ti,edma3-tpcc"; |
| 222 | reg = <0 0x10000>; |
| 223 | reg-names = "edma3_cc"; |
| 224 | interrupts = <12 13 14>; |
| 225 | interrupt-names = "edma3_ccint", "edma3_mperr", |
| 226 | "edma3_ccerrint"; |
| 227 | dma-requests = <64>; |
| 228 | #dma-cells = <2>; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 229 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 230 | ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, |
| 231 | <&edma_tptc2 0>; |
| 232 | |
| 233 | ti,edma-memcpy-channels = <20 21>; |
| 234 | }; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 235 | }; |
| 236 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 237 | target-module@49800000 { |
| 238 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 239 | reg = <0x49800000 0x4>, |
| 240 | <0x49800010 0x4>; |
| 241 | reg-names = "rev", "sysc"; |
| 242 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 243 | ti,sysc-midle = <SYSC_IDLE_FORCE>; |
| 244 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 245 | <SYSC_IDLE_SMART>; |
| 246 | clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>; |
| 247 | clock-names = "fck"; |
| 248 | #address-cells = <1>; |
| 249 | #size-cells = <1>; |
| 250 | ranges = <0x0 0x49800000 0x100000>; |
| 251 | |
| 252 | edma_tptc0: dma@0 { |
| 253 | compatible = "ti,edma3-tptc"; |
| 254 | reg = <0 0x100000>; |
| 255 | interrupts = <112>; |
| 256 | interrupt-names = "edma3_tcerrint"; |
| 257 | }; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 258 | }; |
| 259 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 260 | target-module@49900000 { |
| 261 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 262 | reg = <0x49900000 0x4>, |
| 263 | <0x49900010 0x4>; |
| 264 | reg-names = "rev", "sysc"; |
| 265 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 266 | ti,sysc-midle = <SYSC_IDLE_FORCE>; |
| 267 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 268 | <SYSC_IDLE_SMART>; |
| 269 | clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>; |
| 270 | clock-names = "fck"; |
| 271 | #address-cells = <1>; |
| 272 | #size-cells = <1>; |
| 273 | ranges = <0x0 0x49900000 0x100000>; |
| 274 | |
| 275 | edma_tptc1: dma@0 { |
| 276 | compatible = "ti,edma3-tptc"; |
| 277 | reg = <0 0x100000>; |
| 278 | interrupts = <113>; |
| 279 | interrupt-names = "edma3_tcerrint"; |
| 280 | }; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 281 | }; |
| 282 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 283 | target-module@49a00000 { |
| 284 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 285 | reg = <0x49a00000 0x4>, |
| 286 | <0x49a00010 0x4>; |
| 287 | reg-names = "rev", "sysc"; |
| 288 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; |
| 289 | ti,sysc-midle = <SYSC_IDLE_FORCE>; |
| 290 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 291 | <SYSC_IDLE_SMART>; |
| 292 | clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>; |
| 293 | clock-names = "fck"; |
| 294 | #address-cells = <1>; |
| 295 | #size-cells = <1>; |
| 296 | ranges = <0x0 0x49a00000 0x100000>; |
| 297 | |
| 298 | edma_tptc2: dma@0 { |
| 299 | compatible = "ti,edma3-tptc"; |
| 300 | reg = <0 0x100000>; |
| 301 | interrupts = <114>; |
| 302 | interrupt-names = "edma3_tcerrint"; |
| 303 | }; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 304 | }; |
| 305 | |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 306 | i2c0: i2c@44e0b000 { |
| 307 | compatible = "ti,omap4-i2c"; |
| 308 | #address-cells = <1>; |
| 309 | #size-cells = <0>; |
| 310 | ti,hwmods = "i2c1"; |
| 311 | reg = <0x44e0b000 0x1000>; |
| 312 | interrupts = <70>; |
| 313 | status = "disabled"; |
| 314 | }; |
| 315 | |
| 316 | i2c1: i2c@4802a000 { |
| 317 | compatible = "ti,omap4-i2c"; |
| 318 | #address-cells = <1>; |
| 319 | #size-cells = <0>; |
| 320 | ti,hwmods = "i2c2"; |
| 321 | reg = <0x4802a000 0x1000>; |
| 322 | interrupts = <71>; |
| 323 | status = "disabled"; |
| 324 | }; |
| 325 | |
| 326 | i2c2: i2c@4819c000 { |
| 327 | compatible = "ti,omap4-i2c"; |
| 328 | #address-cells = <1>; |
| 329 | #size-cells = <0>; |
| 330 | ti,hwmods = "i2c3"; |
| 331 | reg = <0x4819c000 0x1000>; |
| 332 | interrupts = <30>; |
| 333 | status = "disabled"; |
| 334 | }; |
| 335 | |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 336 | mmc1: mmc@48060000 { |
| 337 | compatible = "ti,omap4-hsmmc"; |
| 338 | ti,hwmods = "mmc1"; |
| 339 | ti,dual-volt; |
| 340 | ti,needs-special-reset; |
| 341 | ti,needs-special-hs-handling; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 342 | dmas = <&edma_xbar 24 0 0 |
| 343 | &edma_xbar 25 0 0>; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 344 | dma-names = "tx", "rx"; |
| 345 | interrupts = <64>; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 346 | reg = <0x48060000 0x1000>; |
| 347 | status = "disabled"; |
| 348 | }; |
| 349 | |
| 350 | mmc2: mmc@481d8000 { |
| 351 | compatible = "ti,omap4-hsmmc"; |
| 352 | ti,hwmods = "mmc2"; |
| 353 | ti,needs-special-reset; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 354 | dmas = <&edma 2 0 |
| 355 | &edma 3 0>; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 356 | dma-names = "tx", "rx"; |
| 357 | interrupts = <28>; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 358 | reg = <0x481d8000 0x1000>; |
| 359 | status = "disabled"; |
| 360 | }; |
| 361 | |
| 362 | mmc3: mmc@47810000 { |
| 363 | compatible = "ti,omap4-hsmmc"; |
| 364 | ti,hwmods = "mmc3"; |
| 365 | ti,needs-special-reset; |
| 366 | interrupts = <29>; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 367 | reg = <0x47810000 0x1000>; |
| 368 | status = "disabled"; |
| 369 | }; |
| 370 | |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 371 | wdt2: wdt@44e35000 { |
| 372 | compatible = "ti,omap3-wdt"; |
| 373 | ti,hwmods = "wd_timer2"; |
| 374 | reg = <0x44e35000 0x1000>; |
| 375 | interrupts = <91>; |
| 376 | }; |
| 377 | |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 378 | usb: usb@47400000 { |
| 379 | compatible = "ti,am33xx-usb"; |
| 380 | reg = <0x47400000 0x1000>; |
| 381 | ranges; |
| 382 | #address-cells = <1>; |
| 383 | #size-cells = <1>; |
| 384 | ti,hwmods = "usb_otg_hs"; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 385 | |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 386 | usb_ctrl_mod: control@44e10620 { |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 387 | compatible = "ti,am335x-usb-ctrl-module"; |
| 388 | reg = <0x44e10620 0x10 |
| 389 | 0x44e10648 0x4>; |
| 390 | reg-names = "phy_ctrl", "wakeup"; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 391 | }; |
| 392 | |
| 393 | usb0_phy: usb-phy@47401300 { |
| 394 | compatible = "ti,am335x-usb-phy"; |
| 395 | reg = <0x47401300 0x100>; |
| 396 | reg-names = "phy"; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 397 | ti,ctrl_mod = <&usb_ctrl_mod>; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 398 | #phy-cells = <0>; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 399 | }; |
| 400 | |
| 401 | usb0: usb@47401000 { |
| 402 | compatible = "ti,musb-am33xx"; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 403 | reg = <0x47401400 0x400 |
| 404 | 0x47401000 0x200>; |
| 405 | reg-names = "mc", "control"; |
| 406 | |
| 407 | interrupts = <18>; |
| 408 | interrupt-names = "mc"; |
| 409 | dr_mode = "otg"; |
| 410 | mentor,multipoint = <1>; |
| 411 | mentor,num-eps = <16>; |
| 412 | mentor,ram-bits = <12>; |
| 413 | mentor,power = <500>; |
| 414 | phys = <&usb0_phy>; |
| 415 | |
| 416 | dmas = <&cppi41dma 0 0 &cppi41dma 1 0 |
| 417 | &cppi41dma 2 0 &cppi41dma 3 0 |
| 418 | &cppi41dma 4 0 &cppi41dma 5 0 |
| 419 | &cppi41dma 6 0 &cppi41dma 7 0 |
| 420 | &cppi41dma 8 0 &cppi41dma 9 0 |
| 421 | &cppi41dma 10 0 &cppi41dma 11 0 |
| 422 | &cppi41dma 12 0 &cppi41dma 13 0 |
| 423 | &cppi41dma 14 0 &cppi41dma 0 1 |
| 424 | &cppi41dma 1 1 &cppi41dma 2 1 |
| 425 | &cppi41dma 3 1 &cppi41dma 4 1 |
| 426 | &cppi41dma 5 1 &cppi41dma 6 1 |
| 427 | &cppi41dma 7 1 &cppi41dma 8 1 |
| 428 | &cppi41dma 9 1 &cppi41dma 10 1 |
| 429 | &cppi41dma 11 1 &cppi41dma 12 1 |
| 430 | &cppi41dma 13 1 &cppi41dma 14 1>; |
| 431 | dma-names = |
| 432 | "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", |
| 433 | "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", |
| 434 | "rx14", "rx15", |
| 435 | "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", |
| 436 | "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", |
| 437 | "tx14", "tx15"; |
| 438 | }; |
| 439 | |
| 440 | usb1_phy: usb-phy@47401b00 { |
| 441 | compatible = "ti,am335x-usb-phy"; |
| 442 | reg = <0x47401b00 0x100>; |
| 443 | reg-names = "phy"; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 444 | ti,ctrl_mod = <&usb_ctrl_mod>; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 445 | #phy-cells = <0>; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 446 | }; |
| 447 | |
| 448 | usb1: usb@47401800 { |
| 449 | compatible = "ti,musb-am33xx"; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 450 | reg = <0x47401c00 0x400 |
| 451 | 0x47401800 0x200>; |
| 452 | reg-names = "mc", "control"; |
| 453 | interrupts = <19>; |
| 454 | interrupt-names = "mc"; |
| 455 | dr_mode = "otg"; |
| 456 | mentor,multipoint = <1>; |
| 457 | mentor,num-eps = <16>; |
| 458 | mentor,ram-bits = <12>; |
| 459 | mentor,power = <500>; |
| 460 | phys = <&usb1_phy>; |
| 461 | |
| 462 | dmas = <&cppi41dma 15 0 &cppi41dma 16 0 |
| 463 | &cppi41dma 17 0 &cppi41dma 18 0 |
| 464 | &cppi41dma 19 0 &cppi41dma 20 0 |
| 465 | &cppi41dma 21 0 &cppi41dma 22 0 |
| 466 | &cppi41dma 23 0 &cppi41dma 24 0 |
| 467 | &cppi41dma 25 0 &cppi41dma 26 0 |
| 468 | &cppi41dma 27 0 &cppi41dma 28 0 |
| 469 | &cppi41dma 29 0 &cppi41dma 15 1 |
| 470 | &cppi41dma 16 1 &cppi41dma 17 1 |
| 471 | &cppi41dma 18 1 &cppi41dma 19 1 |
| 472 | &cppi41dma 20 1 &cppi41dma 21 1 |
| 473 | &cppi41dma 22 1 &cppi41dma 23 1 |
| 474 | &cppi41dma 24 1 &cppi41dma 25 1 |
| 475 | &cppi41dma 26 1 &cppi41dma 27 1 |
| 476 | &cppi41dma 28 1 &cppi41dma 29 1>; |
| 477 | dma-names = |
| 478 | "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", |
| 479 | "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", |
| 480 | "rx14", "rx15", |
| 481 | "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", |
| 482 | "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", |
| 483 | "tx14", "tx15"; |
| 484 | }; |
| 485 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 486 | cppi41dma: dma-controller@2000 { |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 487 | compatible = "ti,am3359-cppi41"; |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 488 | reg = <0x0000 0x1000>, |
| 489 | <0x2000 0x1000>, |
| 490 | <0x3000 0x1000>, |
| 491 | <0x4000 0x4000>; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 492 | reg-names = "glue", "controller", "scheduler", "queuemgr"; |
| 493 | interrupts = <17>; |
| 494 | interrupt-names = "glue"; |
| 495 | #dma-cells = <2>; |
| 496 | #dma-channels = <30>; |
| 497 | #dma-requests = <256>; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 498 | }; |
| 499 | }; |
| 500 | |
| 501 | mac: ethernet@4a100000 { |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 502 | compatible = "ti,am335x-cpsw","ti,cpsw"; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 503 | ti,hwmods = "cpgmac0"; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 504 | clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; |
| 505 | clock-names = "fck", "cpts"; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 506 | cpdma_channels = <8>; |
| 507 | ale_entries = <1024>; |
| 508 | bd_ram_size = <0x2000>; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 509 | mac_control = <0x20>; |
| 510 | slaves = <2>; |
| 511 | active_slave = <0>; |
| 512 | cpts_clock_mult = <0x80000000>; |
| 513 | cpts_clock_shift = <29>; |
| 514 | reg = <0x4a100000 0x800 |
| 515 | 0x4a101200 0x100>; |
| 516 | #address-cells = <1>; |
| 517 | #size-cells = <1>; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 518 | /* |
| 519 | * c0_rx_thresh_pend |
| 520 | * c0_rx_pend |
| 521 | * c0_tx_pend |
| 522 | * c0_misc_pend |
| 523 | */ |
| 524 | interrupts = <40 41 42 43>; |
| 525 | ranges; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 526 | syscon = <&scm_conf>; |
| 527 | status = "disabled"; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 528 | |
| 529 | davinci_mdio: mdio@4a101000 { |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 530 | compatible = "ti,cpsw-mdio","ti,davinci_mdio"; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 531 | #address-cells = <1>; |
| 532 | #size-cells = <0>; |
| 533 | ti,hwmods = "davinci_mdio"; |
| 534 | bus_freq = <1000000>; |
| 535 | reg = <0x4a101000 0x100>; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 536 | status = "disabled"; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 537 | }; |
| 538 | |
| 539 | cpsw_emac0: slave@4a100200 { |
| 540 | /* Filled in by U-Boot */ |
| 541 | mac-address = [ 00 00 00 00 00 00 ]; |
| 542 | }; |
| 543 | |
| 544 | cpsw_emac1: slave@4a100300 { |
| 545 | /* Filled in by U-Boot */ |
| 546 | mac-address = [ 00 00 00 00 00 00 ]; |
| 547 | }; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 548 | |
| 549 | phy_sel: cpsw-phy-sel@44e10650 { |
| 550 | compatible = "ti,am3352-cpsw-phy-sel"; |
| 551 | reg= <0x44e10650 0x4>; |
| 552 | reg-names = "gmii-sel"; |
| 553 | }; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 554 | }; |
| 555 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 556 | ocmcram: sram@40300000 { |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 557 | compatible = "mmio-sram"; |
| 558 | reg = <0x40300000 0x10000>; /* 64k */ |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 559 | ranges = <0x0 0x40300000 0x10000>; |
| 560 | #address-cells = <1>; |
| 561 | #size-cells = <1>; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 562 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 563 | pm_sram_code: pm-code-sram@0 { |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 564 | compatible = "ti,sram"; |
| 565 | reg = <0x0 0x1000>; |
| 566 | protect-exec; |
| 567 | }; |
| 568 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 569 | pm_sram_data: pm-data-sram@1000 { |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 570 | compatible = "ti,sram"; |
| 571 | reg = <0x1000 0x1000>; |
| 572 | pool; |
| 573 | }; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 574 | }; |
| 575 | |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 576 | emif: emif@4c000000 { |
| 577 | compatible = "ti,emif-am3352"; |
| 578 | reg = <0x4c000000 0x1000000>; |
| 579 | ti,hwmods = "emif"; |
| 580 | interrupts = <101>; |
| 581 | sram = <&pm_sram_code |
| 582 | &pm_sram_data>; |
| 583 | ti,no-idle; |
| 584 | }; |
| 585 | |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 586 | gpmc: gpmc@50000000 { |
| 587 | compatible = "ti,am3352-gpmc"; |
| 588 | ti,hwmods = "gpmc"; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 589 | ti,no-idle-on-init; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 590 | reg = <0x50000000 0x2000>; |
| 591 | interrupts = <100>; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 592 | dmas = <&edma 52 0>; |
| 593 | dma-names = "rxtx"; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 594 | gpmc,num-cs = <7>; |
| 595 | gpmc,num-waitpins = <2>; |
| 596 | #address-cells = <2>; |
| 597 | #size-cells = <1>; |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 598 | interrupt-controller; |
| 599 | #interrupt-cells = <2>; |
| 600 | gpio-controller; |
| 601 | #gpio-cells = <2>; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 602 | status = "disabled"; |
| 603 | }; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 604 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 605 | sham_target: target-module@53100000 { |
| 606 | compatible = "ti,sysc-omap3-sham", "ti,sysc"; |
| 607 | reg = <0x53100100 0x4>, |
| 608 | <0x53100110 0x4>, |
| 609 | <0x53100114 0x4>; |
| 610 | reg-names = "rev", "sysc", "syss"; |
| 611 | ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | |
| 612 | SYSC_OMAP2_AUTOIDLE)>; |
| 613 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 614 | <SYSC_IDLE_NO>, |
| 615 | <SYSC_IDLE_SMART>; |
| 616 | ti,syss-mask = <1>; |
| 617 | /* Domains (P, C): per_pwrdm, l3_clkdm */ |
| 618 | clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>; |
| 619 | clock-names = "fck"; |
| 620 | #address-cells = <1>; |
| 621 | #size-cells = <1>; |
| 622 | ranges = <0x0 0x53100000 0x1000>; |
| 623 | |
| 624 | sham: sham@0 { |
| 625 | compatible = "ti,omap4-sham"; |
| 626 | reg = <0 0x200>; |
| 627 | interrupts = <109>; |
| 628 | dmas = <&edma 36 0>; |
| 629 | dma-names = "rx"; |
| 630 | }; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 631 | }; |
| 632 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 633 | aes_target: target-module@53500000 { |
| 634 | compatible = "ti,sysc-omap2", "ti,sysc"; |
| 635 | reg = <0x53500080 0x4>, |
| 636 | <0x53500084 0x4>, |
| 637 | <0x53500088 0x4>; |
| 638 | reg-names = "rev", "sysc", "syss"; |
| 639 | ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | |
| 640 | SYSC_OMAP2_AUTOIDLE)>; |
| 641 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 642 | <SYSC_IDLE_NO>, |
| 643 | <SYSC_IDLE_SMART>, |
| 644 | <SYSC_IDLE_SMART_WKUP>; |
| 645 | ti,syss-mask = <1>; |
| 646 | /* Domains (P, C): per_pwrdm, l3_clkdm */ |
| 647 | clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>; |
| 648 | clock-names = "fck"; |
| 649 | #address-cells = <1>; |
| 650 | #size-cells = <1>; |
| 651 | ranges = <0x0 0x53500000 0x1000>; |
| 652 | |
| 653 | aes: aes@0 { |
| 654 | compatible = "ti,omap4-aes"; |
| 655 | reg = <0 0xa0>; |
| 656 | interrupts = <103>; |
| 657 | dmas = <&edma 6 0>, |
| 658 | <&edma 5 0>; |
| 659 | dma-names = "tx", "rx"; |
| 660 | }; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 661 | }; |
| 662 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 663 | target-module@56000000 { |
| 664 | compatible = "ti,sysc-omap4", "ti,sysc"; |
| 665 | reg = <0x5600fe00 0x4>, |
| 666 | <0x5600fe10 0x4>; |
| 667 | reg-names = "rev", "sysc"; |
| 668 | ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| 669 | <SYSC_IDLE_NO>, |
| 670 | <SYSC_IDLE_SMART>; |
| 671 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 672 | <SYSC_IDLE_NO>, |
| 673 | <SYSC_IDLE_SMART>; |
| 674 | clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>; |
| 675 | clock-names = "fck"; |
| 676 | resets = <&prm_gfx 0>; |
| 677 | reset-names = "rstctrl"; |
| 678 | #address-cells = <1>; |
| 679 | #size-cells = <1>; |
| 680 | ranges = <0 0x56000000 0x1000000>; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 681 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 682 | /* |
| 683 | * Closed source PowerVR driver, no child device |
| 684 | * binding or driver in mainline |
| 685 | */ |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 686 | }; |
Simon Glass | 5cc16cb | 2014-06-02 22:04:55 -0600 | [diff] [blame] | 687 | }; |
| 688 | }; |
Tom Rini | 1480fdf | 2015-07-31 19:55:08 -0400 | [diff] [blame] | 689 | |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 690 | #include "am33xx-l4.dtsi" |
Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 691 | #include "am33xx-clocks.dtsi" |
Dario Binacchi | 6337d53 | 2020-12-30 00:06:30 +0100 | [diff] [blame] | 692 | |
| 693 | &prcm { |
| 694 | prm_per: prm@c00 { |
| 695 | compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; |
| 696 | reg = <0xc00 0x100>; |
| 697 | #reset-cells = <1>; |
| 698 | }; |
| 699 | |
| 700 | prm_wkup: prm@d00 { |
| 701 | compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; |
| 702 | reg = <0xd00 0x100>; |
| 703 | #reset-cells = <1>; |
| 704 | }; |
| 705 | |
| 706 | prm_device: prm@f00 { |
| 707 | compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; |
| 708 | reg = <0xf00 0x100>; |
| 709 | #reset-cells = <1>; |
| 710 | }; |
| 711 | |
| 712 | prm_gfx: prm@1100 { |
| 713 | compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; |
| 714 | reg = <0x1100 0x100>; |
| 715 | #reset-cells = <1>; |
| 716 | }; |
| 717 | }; |