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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 6337d53fdf45df764bc9946d927172397f183d37 / . / arch / arm / dts / am33xx.dtsi
blob: 3e5ed00aae44a4a89a9f2dd6d91b1035dd55348d [file] [log] [blame]
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]11#include <dt-bindings/bus/ti-sysc.h>
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/pinctrl/am33xx.h>
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]14#include <dt-bindings/clock/am3.h>
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
18 interrupt-parent = <&intc>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]19 #address-cells = <1>;
20 #size-cells = <1>;
21 chosen { };
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]22
23 aliases {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]27 serial0 = &uart0;
28 serial1 = &uart1;
29 serial2 = &uart2;
30 serial3 = &uart3;
31 serial4 = &uart4;
32 serial5 = &uart5;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]33 d-can0 = &dcan0;
34 d-can1 = &dcan1;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]35 usb0 = &usb0;
36 usb1 = &usb1;
37 phy0 = &usb0_phy;
38 phy1 = &usb1_phy;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]39 ethernet0 = &cpsw_emac0;
40 ethernet1 = &cpsw_emac1;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]41 spi0 = &spi0;
42 spi1 = &spi1;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48 cpu@0 {
49 compatible = "arm,cortex-a8";
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]50 enable-method = "ti,am3352";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]51 device_type = "cpu";
52 reg = <0>;
53
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]54 operating-points-v2 = <&cpu0_opp_table>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]55
56 clocks = <&dpll_mpu_ck>;
57 clock-names = "cpu";
58
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]59 clock-latency = <300000>; /* From omap-cpufreq driver */
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]60 cpu-idle-states = <&mpu_gate>;
61 };
62
63 idle-states {
64 mpu_gate: mpu_gate {
65 compatible = "arm,idle-state";
66 entry-latency-us = <40>;
67 exit-latency-us = <90>;
68 min-residency-us = <300>;
69 ti,idle-wkup-m3;
70 };
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]71 };
72 };
73
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]74 cpu0_opp_table: opp-table {
75 compatible = "operating-points-v2-ti-cpu";
76 syscon = <&scm_conf>;
77
78 /*
79 * The three following nodes are marked with opp-suspend
80 * because the can not be enabled simultaneously on a
81 * single SoC.
82 */
83 opp50-300000000 {
84 opp-hz = /bits/ 64 <300000000>;
85 opp-microvolt = <950000 931000 969000>;
86 opp-supported-hw = <0x06 0x0010>;
87 opp-suspend;
88 };
89
90 opp100-275000000 {
91 opp-hz = /bits/ 64 <275000000>;
92 opp-microvolt = <1100000 1078000 1122000>;
93 opp-supported-hw = <0x01 0x00FF>;
94 opp-suspend;
95 };
96
97 opp100-300000000 {
98 opp-hz = /bits/ 64 <300000000>;
99 opp-microvolt = <1100000 1078000 1122000>;
100 opp-supported-hw = <0x06 0x0020>;
101 opp-suspend;
102 };
103
104 opp100-500000000 {
105 opp-hz = /bits/ 64 <500000000>;
106 opp-microvolt = <1100000 1078000 1122000>;
107 opp-supported-hw = <0x01 0xFFFF>;
108 };
109
110 opp100-600000000 {
111 opp-hz = /bits/ 64 <600000000>;
112 opp-microvolt = <1100000 1078000 1122000>;
113 opp-supported-hw = <0x06 0x0040>;
114 };
115
116 opp120-600000000 {
117 opp-hz = /bits/ 64 <600000000>;
118 opp-microvolt = <1200000 1176000 1224000>;
119 opp-supported-hw = <0x01 0xFFFF>;
120 };
121
122 opp120-720000000 {
123 opp-hz = /bits/ 64 <720000000>;
124 opp-microvolt = <1200000 1176000 1224000>;
125 opp-supported-hw = <0x06 0x0080>;
126 };
127
128 oppturbo-720000000 {
129 opp-hz = /bits/ 64 <720000000>;
130 opp-microvolt = <1260000 1234800 1285200>;
131 opp-supported-hw = <0x01 0xFFFF>;
132 };
133
134 oppturbo-800000000 {
135 opp-hz = /bits/ 64 <800000000>;
136 opp-microvolt = <1260000 1234800 1285200>;
137 opp-supported-hw = <0x06 0x0100>;
138 };
139
140 oppnitro-1000000000 {
141 opp-hz = /bits/ 64 <1000000000>;
142 opp-microvolt = <1325000 1298500 1351500>;
143 opp-supported-hw = <0x04 0x0200>;
144 };
145 };
146
147 pmu@4b000000 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]148 compatible = "arm,cortex-a8-pmu";
149 interrupts = <3>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]150 reg = <0x4b000000 0x1000000>;
151 ti,hwmods = "debugss";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]152 };
153
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]154 /*
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]155 * The soc node represents the soc top level view. It is used for IPs
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]156 * that are not memory mapped in the MPU view or for the MPU itself.
157 */
158 soc {
159 compatible = "ti,omap-infra";
160 mpu {
161 compatible = "ti,omap3-mpu";
162 ti,hwmods = "mpu";
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]163 pm-sram = <&pm_sram_code
164 &pm_sram_data>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]165 };
166 };
167
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]168 /*
169 * XXX: Use a flat representation of the AM33XX interconnect.
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]170 * The real AM33XX interconnect network is quite complex. Since
171 * it will not bring real advantage to represent that in DT
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]172 * for the moment, just use a fake OCP bus entry to represent
173 * the whole bus hierarchy.
174 */
175 ocp {
176 compatible = "simple-bus";
177 #address-cells = <1>;
178 #size-cells = <1>;
179 ranges;
180 ti,hwmods = "l3_main";
181
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]182 l4_wkup: l4_wkup@44c00000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]183 wkup_m3: wkup_m3@100000 {
184 compatible = "ti,am3352-wkup-m3";
185 reg = <0x100000 0x4000>,
186 <0x180000 0x2000>;
187 reg-names = "umem", "dmem";
188 ti,hwmods = "wkup_m3";
189 ti,pm-firmware = "am335x-pm-firmware.elf";
190 };
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]191 };
192 l4_per: interconnect@48000000 {
193 };
194 l4_fw: interconnect@47c00000 {
195 };
196 l4_fast: interconnect@4a000000 {
197 };
198 l4_mpuss: interconnect@4b140000 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]199 };
200
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]201 intc: interrupt-controller@48200000 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]202 compatible = "ti,am33xx-intc";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]203 interrupt-controller;
204 #interrupt-cells = <1>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]205 reg = <0x48200000 0x1000>;
206 };
207
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]208 target-module@49000000 {
209 compatible = "ti,sysc-omap4", "ti,sysc";
210 reg = <0x49000000 0x4>;
211 reg-names = "rev";
212 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
213 clock-names = "fck";
214 #address-cells = <1>;
215 #size-cells = <1>;
216 ranges = <0x0 0x49000000 0x10000>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]217
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]218 edma: dma@0 {
219 compatible = "ti,edma3-tpcc";
220 reg = <0 0x10000>;
221 reg-names = "edma3_cc";
222 interrupts = <12 13 14>;
223 interrupt-names = "edma3_ccint", "edma3_mperr",
224 "edma3_ccerrint";
225 dma-requests = <64>;
226 #dma-cells = <2>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]227
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]228 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
229 <&edma_tptc2 0>;
230
231 ti,edma-memcpy-channels = <20 21>;
232 };
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]233 };
234
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]235 target-module@49800000 {
236 compatible = "ti,sysc-omap4", "ti,sysc";
237 reg = <0x49800000 0x4>,
238 <0x49800010 0x4>;
239 reg-names = "rev", "sysc";
240 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
241 ti,sysc-midle = <SYSC_IDLE_FORCE>;
242 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
243 <SYSC_IDLE_SMART>;
244 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
245 clock-names = "fck";
246 #address-cells = <1>;
247 #size-cells = <1>;
248 ranges = <0x0 0x49800000 0x100000>;
249
250 edma_tptc0: dma@0 {
251 compatible = "ti,edma3-tptc";
252 reg = <0 0x100000>;
253 interrupts = <112>;
254 interrupt-names = "edma3_tcerrint";
255 };
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]256 };
257
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]258 target-module@49900000 {
259 compatible = "ti,sysc-omap4", "ti,sysc";
260 reg = <0x49900000 0x4>,
261 <0x49900010 0x4>;
262 reg-names = "rev", "sysc";
263 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
264 ti,sysc-midle = <SYSC_IDLE_FORCE>;
265 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
266 <SYSC_IDLE_SMART>;
267 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
268 clock-names = "fck";
269 #address-cells = <1>;
270 #size-cells = <1>;
271 ranges = <0x0 0x49900000 0x100000>;
272
273 edma_tptc1: dma@0 {
274 compatible = "ti,edma3-tptc";
275 reg = <0 0x100000>;
276 interrupts = <113>;
277 interrupt-names = "edma3_tcerrint";
278 };
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]279 };
280
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]281 target-module@49a00000 {
282 compatible = "ti,sysc-omap4", "ti,sysc";
283 reg = <0x49a00000 0x4>,
284 <0x49a00010 0x4>;
285 reg-names = "rev", "sysc";
286 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
287 ti,sysc-midle = <SYSC_IDLE_FORCE>;
288 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
289 <SYSC_IDLE_SMART>;
290 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
291 clock-names = "fck";
292 #address-cells = <1>;
293 #size-cells = <1>;
294 ranges = <0x0 0x49a00000 0x100000>;
295
296 edma_tptc2: dma@0 {
297 compatible = "ti,edma3-tptc";
298 reg = <0 0x100000>;
299 interrupts = <114>;
300 interrupt-names = "edma3_tcerrint";
301 };
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]302 };
303
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]304 gpio0: gpio@44e07000 {
305 compatible = "ti,omap4-gpio";
306 ti,hwmods = "gpio1";
307 gpio-controller;
308 #gpio-cells = <2>;
309 interrupt-controller;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]310 #interrupt-cells = <2>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]311 reg = <0x44e07000 0x1000>;
312 interrupts = <96>;
313 };
314
315 gpio1: gpio@4804c000 {
316 compatible = "ti,omap4-gpio";
317 ti,hwmods = "gpio2";
318 gpio-controller;
319 #gpio-cells = <2>;
320 interrupt-controller;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]321 #interrupt-cells = <2>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]322 reg = <0x4804c000 0x1000>;
323 interrupts = <98>;
324 };
325
326 gpio2: gpio@481ac000 {
327 compatible = "ti,omap4-gpio";
328 ti,hwmods = "gpio3";
329 gpio-controller;
330 #gpio-cells = <2>;
331 interrupt-controller;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]332 #interrupt-cells = <2>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]333 reg = <0x481ac000 0x1000>;
334 interrupts = <32>;
335 };
336
337 gpio3: gpio@481ae000 {
338 compatible = "ti,omap4-gpio";
339 ti,hwmods = "gpio4";
340 gpio-controller;
341 #gpio-cells = <2>;
342 interrupt-controller;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]343 #interrupt-cells = <2>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]344 reg = <0x481ae000 0x1000>;
345 interrupts = <62>;
346 };
347
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]348 i2c0: i2c@44e0b000 {
349 compatible = "ti,omap4-i2c";
350 #address-cells = <1>;
351 #size-cells = <0>;
352 ti,hwmods = "i2c1";
353 reg = <0x44e0b000 0x1000>;
354 interrupts = <70>;
355 status = "disabled";
356 };
357
358 i2c1: i2c@4802a000 {
359 compatible = "ti,omap4-i2c";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 ti,hwmods = "i2c2";
363 reg = <0x4802a000 0x1000>;
364 interrupts = <71>;
365 status = "disabled";
366 };
367
368 i2c2: i2c@4819c000 {
369 compatible = "ti,omap4-i2c";
370 #address-cells = <1>;
371 #size-cells = <0>;
372 ti,hwmods = "i2c3";
373 reg = <0x4819c000 0x1000>;
374 interrupts = <30>;
375 status = "disabled";
376 };
377
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]378 mmc1: mmc@48060000 {
379 compatible = "ti,omap4-hsmmc";
380 ti,hwmods = "mmc1";
381 ti,dual-volt;
382 ti,needs-special-reset;
383 ti,needs-special-hs-handling;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]384 dmas = <&edma_xbar 24 0 0
385 &edma_xbar 25 0 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]386 dma-names = "tx", "rx";
387 interrupts = <64>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]388 reg = <0x48060000 0x1000>;
389 status = "disabled";
390 };
391
392 mmc2: mmc@481d8000 {
393 compatible = "ti,omap4-hsmmc";
394 ti,hwmods = "mmc2";
395 ti,needs-special-reset;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]396 dmas = <&edma 2 0
397 &edma 3 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]398 dma-names = "tx", "rx";
399 interrupts = <28>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]400 reg = <0x481d8000 0x1000>;
401 status = "disabled";
402 };
403
404 mmc3: mmc@47810000 {
405 compatible = "ti,omap4-hsmmc";
406 ti,hwmods = "mmc3";
407 ti,needs-special-reset;
408 interrupts = <29>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]409 reg = <0x47810000 0x1000>;
410 status = "disabled";
411 };
412
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]413 wdt2: wdt@44e35000 {
414 compatible = "ti,omap3-wdt";
415 ti,hwmods = "wd_timer2";
416 reg = <0x44e35000 0x1000>;
417 interrupts = <91>;
418 };
419
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]420 usb: usb@47400000 {
421 compatible = "ti,am33xx-usb";
422 reg = <0x47400000 0x1000>;
423 ranges;
424 #address-cells = <1>;
425 #size-cells = <1>;
426 ti,hwmods = "usb_otg_hs";
427 status = "disabled";
428
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]429 usb_ctrl_mod: control@44e10620 {
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]430 compatible = "ti,am335x-usb-ctrl-module";
431 reg = <0x44e10620 0x10
432 0x44e10648 0x4>;
433 reg-names = "phy_ctrl", "wakeup";
434 status = "disabled";
435 };
436
437 usb0_phy: usb-phy@47401300 {
438 compatible = "ti,am335x-usb-phy";
439 reg = <0x47401300 0x100>;
440 reg-names = "phy";
441 status = "disabled";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]442 ti,ctrl_mod = <&usb_ctrl_mod>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]443 #phy-cells = <0>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]444 };
445
446 usb0: usb@47401000 {
447 compatible = "ti,musb-am33xx";
448 status = "disabled";
449 reg = <0x47401400 0x400
450 0x47401000 0x200>;
451 reg-names = "mc", "control";
452
453 interrupts = <18>;
454 interrupt-names = "mc";
455 dr_mode = "otg";
456 mentor,multipoint = <1>;
457 mentor,num-eps = <16>;
458 mentor,ram-bits = <12>;
459 mentor,power = <500>;
460 phys = <&usb0_phy>;
461
462 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
463 &cppi41dma 2 0 &cppi41dma 3 0
464 &cppi41dma 4 0 &cppi41dma 5 0
465 &cppi41dma 6 0 &cppi41dma 7 0
466 &cppi41dma 8 0 &cppi41dma 9 0
467 &cppi41dma 10 0 &cppi41dma 11 0
468 &cppi41dma 12 0 &cppi41dma 13 0
469 &cppi41dma 14 0 &cppi41dma 0 1
470 &cppi41dma 1 1 &cppi41dma 2 1
471 &cppi41dma 3 1 &cppi41dma 4 1
472 &cppi41dma 5 1 &cppi41dma 6 1
473 &cppi41dma 7 1 &cppi41dma 8 1
474 &cppi41dma 9 1 &cppi41dma 10 1
475 &cppi41dma 11 1 &cppi41dma 12 1
476 &cppi41dma 13 1 &cppi41dma 14 1>;
477 dma-names =
478 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
479 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
480 "rx14", "rx15",
481 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
482 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
483 "tx14", "tx15";
484 };
485
486 usb1_phy: usb-phy@47401b00 {
487 compatible = "ti,am335x-usb-phy";
488 reg = <0x47401b00 0x100>;
489 reg-names = "phy";
490 status = "disabled";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]491 ti,ctrl_mod = <&usb_ctrl_mod>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]492 #phy-cells = <0>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]493 };
494
495 usb1: usb@47401800 {
496 compatible = "ti,musb-am33xx";
497 status = "disabled";
498 reg = <0x47401c00 0x400
499 0x47401800 0x200>;
500 reg-names = "mc", "control";
501 interrupts = <19>;
502 interrupt-names = "mc";
503 dr_mode = "otg";
504 mentor,multipoint = <1>;
505 mentor,num-eps = <16>;
506 mentor,ram-bits = <12>;
507 mentor,power = <500>;
508 phys = <&usb1_phy>;
509
510 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
511 &cppi41dma 17 0 &cppi41dma 18 0
512 &cppi41dma 19 0 &cppi41dma 20 0
513 &cppi41dma 21 0 &cppi41dma 22 0
514 &cppi41dma 23 0 &cppi41dma 24 0
515 &cppi41dma 25 0 &cppi41dma 26 0
516 &cppi41dma 27 0 &cppi41dma 28 0
517 &cppi41dma 29 0 &cppi41dma 15 1
518 &cppi41dma 16 1 &cppi41dma 17 1
519 &cppi41dma 18 1 &cppi41dma 19 1
520 &cppi41dma 20 1 &cppi41dma 21 1
521 &cppi41dma 22 1 &cppi41dma 23 1
522 &cppi41dma 24 1 &cppi41dma 25 1
523 &cppi41dma 26 1 &cppi41dma 27 1
524 &cppi41dma 28 1 &cppi41dma 29 1>;
525 dma-names =
526 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
527 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
528 "rx14", "rx15",
529 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
530 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
531 "tx14", "tx15";
532 };
533
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]534 cppi41dma: dma-controller@2000 {
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]535 compatible = "ti,am3359-cppi41";
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]536 reg = <0x0000 0x1000>,
537 <0x2000 0x1000>,
538 <0x3000 0x1000>,
539 <0x4000 0x4000>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]540 reg-names = "glue", "controller", "scheduler", "queuemgr";
541 interrupts = <17>;
542 interrupt-names = "glue";
543 #dma-cells = <2>;
544 #dma-channels = <30>;
545 #dma-requests = <256>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]546 };
547 };
548
549 mac: ethernet@4a100000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]550 compatible = "ti,am335x-cpsw","ti,cpsw";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]551 ti,hwmods = "cpgmac0";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]552 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
553 clock-names = "fck", "cpts";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]554 cpdma_channels = <8>;
555 ale_entries = <1024>;
556 bd_ram_size = <0x2000>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]557 mac_control = <0x20>;
558 slaves = <2>;
559 active_slave = <0>;
560 cpts_clock_mult = <0x80000000>;
561 cpts_clock_shift = <29>;
562 reg = <0x4a100000 0x800
563 0x4a101200 0x100>;
564 #address-cells = <1>;
565 #size-cells = <1>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]566 /*
567 * c0_rx_thresh_pend
568 * c0_rx_pend
569 * c0_tx_pend
570 * c0_misc_pend
571 */
572 interrupts = <40 41 42 43>;
573 ranges;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]574 syscon = <&scm_conf>;
575 status = "disabled";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]576
577 davinci_mdio: mdio@4a101000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]578 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]579 #address-cells = <1>;
580 #size-cells = <0>;
581 ti,hwmods = "davinci_mdio";
582 bus_freq = <1000000>;
583 reg = <0x4a101000 0x100>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]584 status = "disabled";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]585 };
586
587 cpsw_emac0: slave@4a100200 {
588 /* Filled in by U-Boot */
589 mac-address = [ 00 00 00 00 00 00 ];
590 };
591
592 cpsw_emac1: slave@4a100300 {
593 /* Filled in by U-Boot */
594 mac-address = [ 00 00 00 00 00 00 ];
595 };
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]596
597 phy_sel: cpsw-phy-sel@44e10650 {
598 compatible = "ti,am3352-cpsw-phy-sel";
599 reg= <0x44e10650 0x4>;
600 reg-names = "gmii-sel";
601 };
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]602 };
603
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]604 ocmcram: sram@40300000 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]605 compatible = "mmio-sram";
606 reg = <0x40300000 0x10000>; /* 64k */
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]607 ranges = <0x0 0x40300000 0x10000>;
608 #address-cells = <1>;
609 #size-cells = <1>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]610
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]611 pm_sram_code: pm-code-sram@0 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]612 compatible = "ti,sram";
613 reg = <0x0 0x1000>;
614 protect-exec;
615 };
616
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]617 pm_sram_data: pm-data-sram@1000 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]618 compatible = "ti,sram";
619 reg = <0x1000 0x1000>;
620 pool;
621 };
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]622 };
623
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]624 emif: emif@4c000000 {
625 compatible = "ti,emif-am3352";
626 reg = <0x4c000000 0x1000000>;
627 ti,hwmods = "emif";
628 interrupts = <101>;
629 sram = <&pm_sram_code
630 &pm_sram_data>;
631 ti,no-idle;
632 };
633
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]634 gpmc: gpmc@50000000 {
635 compatible = "ti,am3352-gpmc";
636 ti,hwmods = "gpmc";
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]637 ti,no-idle-on-init;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]638 reg = <0x50000000 0x2000>;
639 interrupts = <100>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]640 dmas = <&edma 52 0>;
641 dma-names = "rxtx";
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]642 gpmc,num-cs = <7>;
643 gpmc,num-waitpins = <2>;
644 #address-cells = <2>;
645 #size-cells = <1>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]646 interrupt-controller;
647 #interrupt-cells = <2>;
648 gpio-controller;
649 #gpio-cells = <2>;
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]650 status = "disabled";
651 };
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]652
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]653 sham_target: target-module@53100000 {
654 compatible = "ti,sysc-omap3-sham", "ti,sysc";
655 reg = <0x53100100 0x4>,
656 <0x53100110 0x4>,
657 <0x53100114 0x4>;
658 reg-names = "rev", "sysc", "syss";
659 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
660 SYSC_OMAP2_AUTOIDLE)>;
661 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
662 <SYSC_IDLE_NO>,
663 <SYSC_IDLE_SMART>;
664 ti,syss-mask = <1>;
665 /* Domains (P, C): per_pwrdm, l3_clkdm */
666 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
667 clock-names = "fck";
668 #address-cells = <1>;
669 #size-cells = <1>;
670 ranges = <0x0 0x53100000 0x1000>;
671
672 sham: sham@0 {
673 compatible = "ti,omap4-sham";
674 reg = <0 0x200>;
675 interrupts = <109>;
676 dmas = <&edma 36 0>;
677 dma-names = "rx";
678 };
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]679 };
680
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]681 aes_target: target-module@53500000 {
682 compatible = "ti,sysc-omap2", "ti,sysc";
683 reg = <0x53500080 0x4>,
684 <0x53500084 0x4>,
685 <0x53500088 0x4>;
686 reg-names = "rev", "sysc", "syss";
687 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
688 SYSC_OMAP2_AUTOIDLE)>;
689 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
690 <SYSC_IDLE_NO>,
691 <SYSC_IDLE_SMART>,
692 <SYSC_IDLE_SMART_WKUP>;
693 ti,syss-mask = <1>;
694 /* Domains (P, C): per_pwrdm, l3_clkdm */
695 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
696 clock-names = "fck";
697 #address-cells = <1>;
698 #size-cells = <1>;
699 ranges = <0x0 0x53500000 0x1000>;
700
701 aes: aes@0 {
702 compatible = "ti,omap4-aes";
703 reg = <0 0xa0>;
704 interrupts = <103>;
705 dmas = <&edma 6 0>,
706 <&edma 5 0>;
707 dma-names = "tx", "rx";
708 };
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]709 };
710
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]711 target-module@56000000 {
712 compatible = "ti,sysc-omap4", "ti,sysc";
713 reg = <0x5600fe00 0x4>,
714 <0x5600fe10 0x4>;
715 reg-names = "rev", "sysc";
716 ti,sysc-midle = <SYSC_IDLE_FORCE>,
717 <SYSC_IDLE_NO>,
718 <SYSC_IDLE_SMART>;
719 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
720 <SYSC_IDLE_NO>,
721 <SYSC_IDLE_SMART>;
722 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
723 clock-names = "fck";
724 resets = <&prm_gfx 0>;
725 reset-names = "rstctrl";
726 #address-cells = <1>;
727 #size-cells = <1>;
728 ranges = <0 0x56000000 0x1000000>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]729
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]730 /*
731 * Closed source PowerVR driver, no child device
732 * binding or driver in mainline
733 */
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]734 };
Simon Glass5cc16cb2014-06-02 22:04:55 -0600[diff] [blame]735 };
736};
Tom Rini1480fdf2015-07-31 19:55:08 -0400[diff] [blame]737
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]738#include "am33xx-l4.dtsi"
Felix Brackfdce9d32018-12-05 14:53:42 +0100[diff] [blame]739#include "am33xx-clocks.dtsi"
Dario Binacchi6337d532020-12-30 00:06:30 +0100[diff] [blame^]740
741&prcm {
742 prm_per: prm@c00 {
743 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
744 reg = <0xc00 0x100>;
745 #reset-cells = <1>;
746 };
747
748 prm_wkup: prm@d00 {
749 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
750 reg = <0xd00 0x100>;
751 #reset-cells = <1>;
752 };
753
754 prm_device: prm@f00 {
755 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
756 reg = <0xf00 0x100>;
757 #reset-cells = <1>;
758 };
759
760 prm_gfx: prm@1100 {
761 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
762 reg = <0x1100 0x100>;
763 #reset-cells = <1>;
764 };
765};