arch/arm/dts/fsl-ls1088a.dtsi

/*
 * NXP ls1088a SOC common device tree source
 *
 * Copyright 2017 NXP
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/ {
	compatible = "fsl,ls1088a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x80000000>;
		      /* DRAM space - 1, size : 2 GB DRAM */
	};

	gic: interrupt-controller@6000000 {
		compatible = "arm,gic-v3";
		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
		      <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <1 9 0x4>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
			     <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
			     <1 11 0x8>, /* Virtual PPI, active-low */
			     <1 10 0x8>; /* Hypervisor PPI, active-low */
	};

	serial0: serial@21c0500 {
		device_type = "serial";
		compatible = "fsl,ns16550", "ns16550a";
		reg = <0x0 0x21c0500 0x0 0x100>;
		clock-frequency = <0>;	/* Updated by bootloader */
		interrupts = <0 32 0x1>; /* edge triggered */
	};

	serial1: serial@21c0600 {
		device_type = "serial";
		compatible = "fsl,ns16550", "ns16550a";
		reg = <0x0 0x21c0600 0x0 0x100>;
		clock-frequency = <0>; 	/* Updated by bootloader */
		interrupts = <0 32 0x1>; /* edge triggered */
	};

	fsl_mc: fsl-mc@80c000000 {
		compatible = "fsl,qoriq-mc";
		reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
	};

	dspi: dspi@2100000 {
		compatible = "fsl,vf610-dspi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x0 0x2100000 0x0 0x10000>;
		interrupts = <0 26 0x4>; /* Level high type */
		num-cs = <6>;
	};

	qspi: quadspi@1550000 {
		compatible = "fsl,vf610-qspi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x0 0x20c0000 0x0 0x10000>,
			<0x0 0x20000000 0x0 0x10000000>;
		reg-names = "QuadSPI", "QuadSPI-memory";
		num-cs = <4>;
	};

	pcie@3400000 {
		compatible = "fsl,ls-pcie", "snps,dw-pcie";
		reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
		       0x00 0x03480000 0x0 0x80000   /* lut registers */
		       0x00 0x034c0000 0x0 0x40000   /* pf controls registers */
		       0x20 0x00000000 0x0 0x20000>; /* configuration space */
		reg-names = "dbi", "lut", "ctrl", "config";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		num-lanes = <4>;
		bus-range = <0x0 0xff>;
		ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000   /* downstream I/O */
			  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	};

	pcie@3500000 {
		compatible = "fsl,ls-pcie", "snps,dw-pcie";
		reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
		       0x00 0x03580000 0x0 0x80000   /* lut registers */
		       0x00 0x035c0000 0x0 0x40000   /* pf controls registers */
		       0x28 0x00000000 0x0 0x20000>; /* configuration space */
		reg-names = "dbi", "lut", "ctrl", "config";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		num-lanes = <4>;
		bus-range = <0x0 0xff>;
		ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000   /* downstream I/O */
			  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	};

	pcie@3600000 {
		compatible = "fsl,ls-pcie", "snps,dw-pcie";
		reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
		       0x00 0x03680000 0x0 0x80000   /* lut registers */
		       0x00 0x036c0000 0x0 0x40000   /* pf controls registers */
		       0x30 0x00000000 0x0 0x20000>; /* configuration space */
		reg-names = "dbi", "lut", "ctrl", "config";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		num-lanes = <8>;
		bus-range = <0x0 0xff>;
		ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000   /* downstream I/O */
			  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	};
};