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wdenkc6097192002-11-03 00:24:07 +00001/*
stroese2a9e02e2003-02-18 11:30:24 +00002 * (C) Copyright 2001-2003
wdenkc6097192002-11-03 00:24:07 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
wdenkc6097192002-11-03 00:24:07 +000038#define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */
39
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
41
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenkc6097192002-11-03 00:24:07 +000043
wdenkc837dcb2004-01-20 23:12:12 +000044#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000045
46#define CONFIG_BAUDRATE 9600
47#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48
49#undef CONFIG_BOOTARGS
50#define CONFIG_BOOTCOMMAND "bootm fff00000"
51
52#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +000054
Ben Warren96e21f82008-10-27 23:50:15 -070055#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +000056#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000057#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000058#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Ben Warren18cc7af2009-04-28 16:50:53 -070059#define CONFIG_NET_MULTI
wdenkc6097192002-11-03 00:24:07 +000060
wdenkc6097192002-11-03 00:24:07 +000061
Jon Loeliger49cf7e82007-07-05 19:52:35 -050062/*
Jon Loeliger11799432007-07-10 09:02:57 -050063 * BOOTP options
64 */
65#define CONFIG_BOOTP_BOOTFILESIZE
66#define CONFIG_BOOTP_BOOTPATH
67#define CONFIG_BOOTP_GATEWAY
68#define CONFIG_BOOTP_HOSTNAME
69
70
71/*
72 * BOOTP options
73 */
74#define CONFIG_BOOTP_BOOTFILESIZE
75#define CONFIG_BOOTP_BOOTPATH
76#define CONFIG_BOOTP_GATEWAY
77#define CONFIG_BOOTP_HOSTNAME
78
79
80/*
Jon Loeliger49cf7e82007-07-05 19:52:35 -050081 * Command line configuration.
82 */
83#include <config_cmd_default.h>
84
85#define CONFIG_CMD_PCI
86#define CONFIG_CMD_IRQ
87#define CONFIG_CMD_MII
88#define CONFIG_CMD_ELF
89#define CONFIG_CMD_EEPROM
90
wdenkc6097192002-11-03 00:24:07 +000091
92#undef CONFIG_WATCHDOG /* watchdog disabled */
93
wdenkc837dcb2004-01-20 23:12:12 +000094#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +000095
96/*
97 * Miscellaneous configurable options
98 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_LONGHELP /* undef to save memory */
100#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500101#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000103#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000105#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
107#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
108#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +0000111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
113#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000114
Stefan Roese550650d2010-09-20 16:05:31 +0200115#define CONFIG_CONS_INDEX 1 /* Use UART0 */
116#define CONFIG_SYS_NS16550
117#define CONFIG_SYS_NS16550_SERIAL
118#define CONFIG_SYS_NS16550_REG_SIZE 1
119#define CONFIG_SYS_NS16550_CLK get_serial_clock()
120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_EXT_SERIAL_CLOCK 1843200 /* use external serial clock */
wdenkc6097192002-11-03 00:24:07 +0000122
123/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000125 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
126 57600, 115200, 230400, 460800, 921600 }
wdenkc6097192002-11-03 00:24:07 +0000127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
129#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkc6097192002-11-03 00:24:07 +0000130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000132
133#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
134
135/*-----------------------------------------------------------------------
136 * PCI stuff
137 *-----------------------------------------------------------------------
138 */
wdenkc837dcb2004-01-20 23:12:12 +0000139#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
140#define PCI_HOST_FORCE 1 /* configure as pci host */
141#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkc6097192002-11-03 00:24:07 +0000142
wdenkc837dcb2004-01-20 23:12:12 +0000143#define CONFIG_PCI /* include pci support */
144#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
145#define CONFIG_PCI_PNP /* do pci plug-and-play */
146 /* resource configuration */
wdenkc6097192002-11-03 00:24:07 +0000147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
149#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */
150#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
151#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
152#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
153#define CONFIG_SYS_PCI_PTM2LA 0xffe00000 /* point to flash */
154#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
155#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000156
157/*-----------------------------------------------------------------------
158 * Start addresses for the final memory configuration
159 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_SDRAM_BASE 0x00000000
163#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
164#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
165#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
166#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000167
168/*
169 * For booting Linux, the board info and command line data
170 * have to be in the first 8 MB of memory, since this is
171 * the maximum mapped by the Linux kernel during initialization.
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000174/*-----------------------------------------------------------------------
175 * FLASH organization
176 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
178#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
181#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
184#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
185#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000186/*
187 * The following defines are added for buggy IOP480 byte interface.
188 * All other boards should use the standard values (CPCI405 etc.)
189 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
191#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
192#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000195
196/*-----------------------------------------------------------------------
197 * I2C EEPROM (CAT24WC08) for environment
198 */
199#define CONFIG_HARD_I2C /* I2C with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200200#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
202#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkc6097192002-11-03 00:24:07 +0000203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
205#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +0000206/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
208#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenkc6097192002-11-03 00:24:07 +0000209 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000210 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +0000212
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200213#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200214#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
215#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
wdenk8bde7f72003-06-27 21:31:46 +0000216 /* total size of a CAT24WC08 is 1024 bytes */
wdenkc6097192002-11-03 00:24:07 +0000217
wdenkc6097192002-11-03 00:24:07 +0000218/*
219 * Init Memory Controller:
220 *
221 * BR0/1 and OR0/1 (FLASH)
222 */
223
224#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
225#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
226
227/*-----------------------------------------------------------------------
228 * External Bus Controller (EBC) Setup
229 */
230
wdenkc837dcb2004-01-20 23:12:12 +0000231/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_EBC_PB0AP 0x92015480
233#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000234
wdenkc837dcb2004-01-20 23:12:12 +0000235/* Memory Bank 1 (Uart 8bit) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_EBC_PB1AP 0x01000480 /* TWT=2,TH=2,no Ready,BEM=0,SOR=1 */
237#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000238
wdenkc837dcb2004-01-20 23:12:12 +0000239/* Memory Bank 2 (Uart 32bit) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */
241#define CONFIG_SYS_EBC_PB2CR 0xF011C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
wdenkc6097192002-11-03 00:24:07 +0000242
wdenkc837dcb2004-01-20 23:12:12 +0000243/* Memory Bank 3 (FPGA Reset) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_EBC_PB3AP 0x010004C0 /* no Ready, BEM=1 */
245#define CONFIG_SYS_EBC_PB3CR 0xF021A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000246
247/*-----------------------------------------------------------------------
248 * Definitions for initial stack pointer and data area (in DPRAM)
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
251#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200252#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200253#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000255
wdenkc6097192002-11-03 00:24:07 +0000256#endif /* __CONFIG_H */