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Stelian Popd99a8ff2008-05-08 20:52:22 +02001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Stelian Popd99a8ff2008-05-08 20:52:22 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * Configuation settings for the AT91SAM9261EK board.
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Stelian Popd99a8ff2008-05-08 20:52:22 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/* ARM asynchronous clock */
Xu, Hongf7aea462011-07-31 22:49:00 +000015#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
Achim Ehrlich7c966a82010-02-24 10:29:16 +010016#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
Stelian Popd99a8ff2008-05-08 20:52:22 +020017
Xu, Hongf7aea462011-07-31 22:49:00 +000018#ifdef CONFIG_AT91SAM9G10
19#define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020020#else
Xu, Hongf7aea462011-07-31 22:49:00 +000021#define CONFIG_AT91SAM9261EK /* It's an Atmel AT91SAM9261 EK*/
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020022#endif
Xu, Hongf7aea462011-07-31 22:49:00 +000023
24#include <asm/hardware.h>
25
Xu, Hongf7aea462011-07-31 22:49:00 +000026#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
27#define CONFIG_SETUP_MEMORY_TAGS
28#define CONFIG_INITRD_TAG
Stelian Popd99a8ff2008-05-08 20:52:22 +020029
30#define CONFIG_SKIP_LOWLEVEL_INIT
Stelian Popd99a8ff2008-05-08 20:52:22 +020031
Xu, Hongf7aea462011-07-31 22:49:00 +000032#define CONFIG_ATMEL_LEGACY
33#define CONFIG_SYS_TEXT_BASE 0x21f00000
34
Stelian Popd99a8ff2008-05-08 20:52:22 +020035/*
36 * Hardware drivers
37 */
Xu, Hongf7aea462011-07-31 22:49:00 +000038
Stelian Pop820f2a92008-05-08 14:52:30 +020039/* LCD */
Stelian Pop820f2a92008-05-08 14:52:30 +020040#define LCD_BPP LCD_COLOR8
Xu, Hongf7aea462011-07-31 22:49:00 +000041#define CONFIG_LCD_LOGO
Stelian Pop820f2a92008-05-08 14:52:30 +020042#undef LCD_TEST_PATTERN
Xu, Hongf7aea462011-07-31 22:49:00 +000043#define CONFIG_LCD_INFO
44#define CONFIG_LCD_INFO_BELOW_LOGO
Xu, Hongf7aea462011-07-31 22:49:00 +000045#define CONFIG_ATMEL_LCD
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020046#ifdef CONFIG_AT91SAM9261EK
Xu, Hongf7aea462011-07-31 22:49:00 +000047#define CONFIG_ATMEL_LCD_BGR555
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020048#endif
Xu, Hongf7aea462011-07-31 22:49:00 +000049
Stelian Popd99a8ff2008-05-08 20:52:22 +020050/*
51 * BOOTP options
52 */
Xu, Hongf7aea462011-07-31 22:49:00 +000053#define CONFIG_BOOTP_BOOTFILESIZE
54#define CONFIG_BOOTP_BOOTPATH
55#define CONFIG_BOOTP_GATEWAY
56#define CONFIG_BOOTP_HOSTNAME
Stelian Popd99a8ff2008-05-08 20:52:22 +020057
Stelian Popd99a8ff2008-05-08 20:52:22 +020058/* SDRAM */
59#define CONFIG_NR_DRAM_BANKS 1
Xu, Hongf7aea462011-07-31 22:49:00 +000060#define CONFIG_SYS_SDRAM_BASE 0x20000000
61#define CONFIG_SYS_SDRAM_SIZE 0x04000000
62#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou.Yang@microchip.com324873e2017-07-21 13:28:40 +080063 (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Stelian Popd99a8ff2008-05-08 20:52:22 +020064
65/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +010066#ifdef CONFIG_CMD_NAND
67#define CONFIG_NAND_ATMEL
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_MAX_NAND_DEVICE 1
69#define CONFIG_SYS_NAND_BASE 0x40000000
Xu, Hongf7aea462011-07-31 22:49:00 +000070#define CONFIG_SYS_NAND_DBW_8
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +010071/* our ALE is AD22 */
72#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
73/* our CLE is AD21 */
74#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
75#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
76#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
Wolfgang Denk2eb99ca2009-07-18 21:52:24 +020077
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +010078#endif
Stelian Popd99a8ff2008-05-08 20:52:22 +020079
Stelian Popd99a8ff2008-05-08 20:52:22 +020080/* Ethernet */
Xu, Hongf7aea462011-07-31 22:49:00 +000081#define CONFIG_DRIVER_DM9000
Stelian Popd99a8ff2008-05-08 20:52:22 +020082#define CONFIG_DM9000_BASE 0x30000000
83#define DM9000_IO CONFIG_DM9000_BASE
84#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
Xu, Hongf7aea462011-07-31 22:49:00 +000085#define CONFIG_DM9000_USE_16BIT
86#define CONFIG_DM9000_NO_SROM
Stelian Popd99a8ff2008-05-08 20:52:22 +020087#define CONFIG_NET_RETRY_COUNT 20
Xu, Hongf7aea462011-07-31 22:49:00 +000088#define CONFIG_RESET_PHY_R
Stelian Popd99a8ff2008-05-08 20:52:22 +020089
90/* USB */
Jean-Christophe PLAGNIOL-VILLARD2b7178a2009-03-27 23:26:44 +010091#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +080092#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Xu, Hongf7aea462011-07-31 22:49:00 +000093#define CONFIG_USB_OHCI_NEW
Xu, Hongf7aea462011-07-31 22:49:00 +000094#define CONFIG_SYS_USB_OHCI_CPU_INIT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +020096#ifdef CONFIG_AT91SAM9G10EK
97#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10"
98#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
Sedji Gaouaou5ccc2d92009-06-25 17:04:15 +0200100#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Stelian Popd99a8ff2008-05-08 20:52:22 +0200102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
Stelian Popd99a8ff2008-05-08 20:52:22 +0200104
Xu, Hongf7aea462011-07-31 22:49:00 +0000105#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_MEMTEST_END 0x23e00000
Stelian Popd99a8ff2008-05-08 20:52:22 +0200107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
Stelian Popd99a8ff2008-05-08 20:52:22 +0200109
110/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Nicolas Ferre89a7a872008-12-06 13:11:14 +0100111#define CONFIG_ENV_OFFSET 0x4200
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200112#define CONFIG_ENV_SIZE 0x4200
Wenyou.Yang@microchip.com324873e2017-07-21 13:28:40 +0800113#define CONFIG_ENV_SECT_SIZE 0x210
114#define CONFIG_ENV_SPI_MAX_HZ 15000000
115#define CONFIG_BOOTCOMMAND "sf probe 0; " \
116 "sf read 0x22000000 0x84000 0x294000; " \
117 "bootm 0x22000000"
Stelian Popd99a8ff2008-05-08 20:52:22 +0200118#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
119 "root=/dev/mtdblock0 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200120 "mtdparts=atmel_nand:-(root) " \
Stelian Popd99a8ff2008-05-08 20:52:22 +0200121 "rw rootfstype=jffs2"
122
Nicolas Ferre89a7a872008-12-06 13:11:14 +0100123#elif CONFIG_SYS_USE_DATAFLASH_CS3
124
125/* bootstrap + u-boot + env + linux in dataflash on CS3 */
Nicolas Ferre89a7a872008-12-06 13:11:14 +0100126#define CONFIG_ENV_OFFSET 0x4200
Nicolas Ferre89a7a872008-12-06 13:11:14 +0100127#define CONFIG_ENV_SIZE 0x4200
Wenyou.Yang@microchip.com324873e2017-07-21 13:28:40 +0800128#define CONFIG_ENV_SECT_SIZE 0x210
129#define CONFIG_ENV_SPI_MAX_HZ 15000000
130#define CONFIG_BOOTCOMMAND "sf probe 0:3; " \
131 "sf read 0x22000000 0x84000 0x294000; " \
132 "bootm 0x22000000"
Nicolas Ferre89a7a872008-12-06 13:11:14 +0100133#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
134 "root=/dev/mtdblock0 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200135 "mtdparts=atmel_nand:-(root) " \
Nicolas Ferre89a7a872008-12-06 13:11:14 +0100136 "rw rootfstype=jffs2"
137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#else /* CONFIG_SYS_USE_NANDFLASH */
Stelian Popd99a8ff2008-05-08 20:52:22 +0200139
140/* bootstrap + u-boot + env + linux in nandflash */
Wenyou.Yang@microchip.com324873e2017-07-21 13:28:40 +0800141#define CONFIG_ENV_OFFSET 0x120000
Bo Shen0c58cfa2013-02-20 00:16:25 +0000142#define CONFIG_ENV_OFFSET_REDUND 0x100000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200143#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
Bo Shen0c58cfa2013-02-20 00:16:25 +0000144#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
145#define CONFIG_BOOTARGS \
146 "console=ttyS0,115200 earlyprintk " \
147 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
148 "256k(env),256k(env_redundant),256k(spare)," \
149 "512k(dtb),6M(kernel)ro,-(rootfs) " \
150 "root=/dev/mtdblock7 rw rootfstype=jffs2"
Stelian Popd99a8ff2008-05-08 20:52:22 +0200151#endif
152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_CBSIZE 256
154#define CONFIG_SYS_MAXARGS 16
Xu, Hongf7aea462011-07-31 22:49:00 +0000155#define CONFIG_SYS_LONGHELP
156#define CONFIG_CMDLINE_EDITING
Alexandre Bellonie139cb32012-07-02 04:26:58 +0000157#define CONFIG_AUTO_COMPLETE
Stelian Popd99a8ff2008-05-08 20:52:22 +0200158
Stelian Popd99a8ff2008-05-08 20:52:22 +0200159/*
160 * Size of malloc() pool
161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
Stelian Popd99a8ff2008-05-08 20:52:22 +0200163
Stelian Popd99a8ff2008-05-08 20:52:22 +0200164#endif