blob: a05c308669209ad5a89dc3b70294902c0580e120 [file] [log] [blame]
Gregory CLEMENT6787c1e2018-12-14 16:16:49 +01001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#include <common.h>
7#include <asm/io.h>
8#include <asm/addrspace.h>
9#include <asm/types.h>
10#include <environment.h>
11#include <spi.h>
Lars Povlsen4deb0962019-01-02 09:52:26 +010012#include <led.h>
Gregory CLEMENT6787c1e2018-12-14 16:16:49 +010013
14DECLARE_GLOBAL_DATA_PTR;
15
Lars Povlsene9f14922018-12-20 09:56:05 +010016enum {
17 BOARD_TYPE_PCB120 = 0xAABBCC00,
18 BOARD_TYPE_PCB123,
19};
Gregory CLEMENT6787c1e2018-12-14 16:16:49 +010020
21void external_cs_manage(struct udevice *dev, bool enable)
22{
23 u32 cs = spi_chip_select(dev);
24 /* IF_SI0_OWNER, select the owner of the SI interface
25 * Encoding: 0: SI Slave
Lars Povlsene9f14922018-12-20 09:56:05 +010026 * 1: SI Boot Master
27 * 2: SI Master Controller
Gregory CLEMENT6787c1e2018-12-14 16:16:49 +010028 */
29 if (!enable) {
30 writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
31 ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), BASE_CFG + ICPU_SW_MODE);
32 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
33 ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
34 ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
35 } else {
36 writel(0, BASE_CFG + ICPU_SW_MODE);
37 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
38 ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
39 ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
40 }
41}
42
43void board_debug_uart_init(void)
44{
45 /* too early for the pinctrl driver, so configure the UART pins here */
Lars Povlsene9f14922018-12-20 09:56:05 +010046 mscc_gpio_set_alternate(6, 1);
47 mscc_gpio_set_alternate(7, 1);
Gregory CLEMENT6787c1e2018-12-14 16:16:49 +010048}
49
50int board_early_init_r(void)
51{
52 /* Prepare SPI controller to be used in master mode */
53 writel(0, BASE_CFG + ICPU_SW_MODE);
54 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
55 ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
56 ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
57
58 /* Address of boot parameters */
59 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
Lars Povlsen4deb0962019-01-02 09:52:26 +010060
61 /* LED setup */
62 if (IS_ENABLED(CONFIG_LED))
63 led_default_state();
64
Gregory CLEMENT6787c1e2018-12-14 16:16:49 +010065 return 0;
66}
Lars Povlsene9f14922018-12-20 09:56:05 +010067
68static void do_board_detect(void)
69{
70 u16 dummy = 0;
71
72 /* Enable MIIM */
73 mscc_gpio_set_alternate(14, 1);
74 mscc_gpio_set_alternate(15, 1);
75 if (mscc_phy_rd(1, 0, 0, &dummy) == 0)
76 gd->board_type = BOARD_TYPE_PCB120;
77 else
78 gd->board_type = BOARD_TYPE_PCB123;
79}
80
81#if defined(CONFIG_MULTI_DTB_FIT)
82int board_fit_config_name_match(const char *name)
83{
84 if (gd->board_type == BOARD_TYPE_PCB120 &&
85 strcmp(name, "ocelot_pcb120") == 0)
86 return 0;
87
88 if (gd->board_type == BOARD_TYPE_PCB123 &&
89 strcmp(name, "ocelot_pcb123") == 0)
90 return 0;
91
92 return -1;
93}
94#endif
95
96#if defined(CONFIG_DTB_RESELECT)
97int embedded_dtb_select(void)
98{
99 do_board_detect();
100 fdtdec_setup();
101
102 return 0;
103}
104#endif